19-2054; Rev 2; 7/02 MAX1181 Evaluation Kit The MAX1181 Evaluation kit (EV Kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the nonmultiplexed MAX1180–MAX1184 and MAX1190 or multiplexed MAX1185 and MAX1186, dual 10-bit analog-to-digital converters (ADC). The MAX1180–MAX1186 and MAX1190 accept differential or single-ended analog inputs and the EV kit allows for evaluation of each ADC with both types of signals from one single-ended analog signal. The digital output produced by the ADC can easily be sampled with a user-provided high-speed logic analyzer or data-acquisition system. The EV kit operates from 3.0V analog and 2.0V digital power supplies. It includes circuitry that generates a clock signal from an AC signal provided by the user. The EV kit comes with the MAX1181 installed. Order free samples of the pin-compatible MAX1180, MAX1182, MAX1183, MAX1184, MAX1185, MAX1186, or MAX1190 to evaluate these parts. Selector Guide PART SPEED (Msps) MAX1190ECM 120 MAX1180ECM 105 MAX1181ECM 80 MAX1182ECM 65 MAX1183ECM 40 MAX1184ECM 20 MAX1185ECM 20, multiplexed MAX1186ECM 40, multiplexed Features ♦ Up to 80Msps Sampling Rate (MAX1181) ♦ Low Voltage and Power Operation ♦ Single-Ended or Fully Differential Signal Input Configuration ♦ Clock-Shaping Circuit ♦ Fully Assembled and Tested ♦ Supports Both Nonmultiplexed (MAX1180–MAX1184/MAX1190) and Multiplexed (MAX1185/MAX1186) Output Operation Ordering Information PART TEMP RANGE MAX1181EVKIT 0°C to +70°C IC PACKAGE 48 TQFP-EP Component List QTY DESCRIPTION DESIGNATION QTY C1–C5, C7, C9, C11, C16–C19, C21, C23, C27, C31, C33, C34, C36–C39, C42–C49, C51, C52 C12–C15 4 32 0.1µF, 16V, X7R, ±10% ceramic capacitors (0603) Taiyo Yuden EMK107BJ104KA or TDK C1608X7R1E104KT 10µF, 10V, tantalum capacitors (B) AVX TAJB106M010 or Kemet T494B106K010AS C6, C50 0 Not installed (0603) C24, C25, C28, C29 4 DESIGNATION C8, C10, C20, C22, C26, C32, C35, C40, C41 C30 9 1 22pF, 50V, ±5% ceramic capacitors (0603) TDK C1608CCOG1H220JT 2.2µF, 10V tantalum capacitors (A) AVX TAJA225K010 or Kemet T494A225K010AS 1000pF, 50V ±10% ceramic capacitor (0603) TDK C1608X7R1H102KT DESCRIPTION R1, R6, R19 0 Not installed (0603) R31–R33 0 Not installed (0805) R7 1 0Ω ±5% resistor (0603) R38 1 3.9Ω ±5% resistor (0805) R2–R5, R35, R51–R71 26 49.9Ω ±1% resistors (0603) R15–R18 4 24.9Ω ±1% resistors (0603) R8, R21–R30, R41–R50 21 100Ω ±1% resistors (0603) Component List continued on next page. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 Evaluates: MAX1180–MAX1186/MAX1190 General Description MAX1181 Evaluation Kit Evaluates: MAX1180–MAX1186/MAX1190 Component List (continued) DESIGNATION QTY DESCRIPTION PHONE FAX AVX 843-448-9411 843-448-1943 Fair-Rite Products 888-324-7748 888-337-7483 Kemet 864-963-6300 864-963-6322 4.02kΩ ±1% resistors (0603) Mini-Circuits 718-934-4500 718-934-7092 1 10kΩ ±1% resistor (0603) Pericom 800-435-2336 408-435-1100 1 5kΩ potentiometer, 12-turn, 1/4” BI Technologies 3266W-1-502 Taiyo Yuden 800-348-2496 847-952-0899 TDK 847-803-6100 847-803-6296 2 RF transformers Mini-Circuits TT1-6-KK81 Texas Instruments 972-644-5580 214-480-7800 R9, R10, R13, R14, R36 5 2kΩ ±1% resistors (0603) R11 1 6.04kΩ ±1% resistor (0603) R12, R37 2 R20 R34 T1, T2 SUPPLIER U1 1 MAX1181ECM (48-pin TQFP-EP) Note: Please indicate that you are using the MAX1181 when contacting these component suppliers. U2 1 Dual CMOS differential line receiver (8-pin SO) Maxim MAX9113ESA • Logic analyzer or data-acquisition system (e.g., HP16500C with HP16517A High-Speed Logic State Card) • 2 Buffer/Driver three-state outputs (48-pin TSSOP) Texas Instrument SN74ALVCH16244DGG Analog bandpass filters (e.g., TTE Elliptical Bandpass Filter Q56 series) • Digital voltmeter U3, U4 L1, L2 2 Ferrite chip beads, 90Ω at 100MHz (1206), Fair-Rite Products Corp. 2512069007Y0 or Mouser 436-2600 (60Ω at 100MHz) J1 1 2 x 25-pin header S/E_INA, D/E_INA, S/E_INB, D/E_ INB, CLOCK 5 SMA PC-mount connectors JU1–JU8 8 3-pin headers None 8 Shunt (JU1-JU8) None 1 MAX1181 PC board None 1 MAX1181 data sheet None 1 MAX1181 EV kit data sheet The MAX1181 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable function generators until all connections are complete. 1) Verify that shunts are installed across pins 2 and 3 of jumpers JU5 (offset binary digital output), JU6 (normal operation), JU7 (MAX1181 operating), and JU8 (outputs enabled). 2) Connect the clock function generator to the CLOCK SMA connector. Quick Start Required equipment: • Component Suppliers DC power supplies Digital 2.0V, 100mA Analog 3.0V, 300mA 3) Connect the output of the analog signal function generator to the input of the bandpass filter. 4) a) To evaluate differential analog signals on Channel A, verify that shunts are installed on pins 2 and 3 of jumpers JU1 and JU2. Connect the output of the analog bandpass filter to the D/E_INA SMA connector. For single-ended analog signal evaluation on Channel A, verify that shunts are installed on pins 1 and 2 of jumpers JU1 and JU2, and connect the output of the bandpass filter to the S/E_INA SMA connector. b) To evaluate differential analog signals on Channel B, verify that shunts are installed on pins 2 and 3 of jumpers JU3 and JU4. Connect the output of the analog bandpass filter to the D/E_INB SMA connector. For single-ended analog signal evaluation on Channel B, verify that shunts are installed on pins 1 and 2 of jumper JU3 and JU4, and connect the output of the bandpass filter to the S/E_INB SMA connector. • Function generator with low-phase noise and lowjitter for clock input (e.g., HP8662A) • Function generators for analog signal inputs (e.g., HP8662A) 2 _______________________________________________________________________________________ MAX1181 Evaluation Kit 5) Connect the logic analyzer to the square pin header (J1). Channel A (Channel B) data is captured on J11 (J1-23) through J1-19 (J1-41). If evaluating the multiplexed ADC (MAX1185 or MAX1186), the output data for Channel A and Channel B is captured on a single 10-bit bus (J1-1 through J1-19) and the A/B indicator signal can be monitored on J1-23 (see Table 4 for bit locations and J1 header designators). The system clock for both multiplexed and nonmultiplexed output operation is available on pin J1-43. 6) Connect a 3.0V, 300mA power supply to VA and VADUT. Connect the ground terminal of this supply to AGND. 7) Connect a 2.0V, 100mA power supply to VD and VDDUT. Connect the ground terminal of this supply to DGND. 8) Turn on both power supplies. 9) With a voltmeter, verify that 1.20V is measured across test points TP1 and TP2. If the voltage is not 1.20V, adjust potentiometer R34 until 1.20V is obtained. 10) Enable the function generators. Set the clock function generator for an output amplitude of 2.4V P-P and frequency (fCLK) ≤ 80MHz. Set the analog input signal generators for an output amplitude ≤ 2VP-P and to the desired frequency. The two function generators should be phase-locked to each other. 11) Set the logic analyzer to capture on the clock’s rising edge. In multiplexed output operation mode capture Channel A data on the falling edge and Channel B data on the rising edge of the logic analyzer clock. 12) Enable the logic analyzer. 13) Collect data using the logic analyzer. Detailed Description The MAX1181 EV kit is a fully-assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1180, MAX1181, MAX1182, MAX1183, MAX1184, MAX1185, MAX1186, or MAX1190, dual 10-bit ADCs (Channel A and Channel B). The MAX1180–MAX1184/MAX1190 dual outputs (Channel A and Channel B) are nonmultiplexed and the data is captured with two separate 10-bit buses. The MAX1185 and MAX1186 dual outputs (Channel A and Channel B) are multiplexed and data is captured with a single 10-bit bus. The EV kit comes with the MAX1181 which can be evaluated with a maximum clock frequency (fCLK) of 80MHz. The MAX1181 accepts differential or single-ended analog input signals. With the proper board configuration (as specified below), the ADC can be evaluated with both types of signals by supplying only one single-ended analog signal to the EV kit. The EV kit was designed as a four-layer PC board to optimize the performance of the MAX1181. Separate analog and digital power planes minimize noise coupling between analog and digital signals. For simple operation, the EV kit is specified to have 3.0V and 2.0V DC power supplies applied to analog and digital power planes, respectively. However, the digital plane can be operated down to 1.7V without compromising the board’s performance. The logic analyzer’s threshold must be adjusted accordingly. Access to Channel A and Channel B outputs is provided through connector J1. The 50-pin connector interfaces directly with a user-provided logic analyzer or data acquisition system. Power Supplies The MAX1181 EV kit requires separate analog and digital power supplies for best performance. A 3.0V power supply is used to power the analog portion of the MAX1181 and the clock signal circuit. The MAX1181 analog supply voltage has a range of 2.7V to 3.6V, however, 3.0V must be supplied to the EV kit (VADUT, VA) to meet the minimum input voltage supply to the clock shaping circuit. A separate 2.0V power supply is used to power the digital portion (VDDUT, VD) of the MAX1181 and the buffer/driver. It will operate with a voltage supply as low as 1.7V and as high as 3.6V. Enhanced dynamic performance is normally achieved when the digital supply voltage is lower than the analog supply voltage. Clock An on-board clock-shaping circuit generates a clock signal from an AC sine-wave signal applied to the CLOCK SMA connector. The input signal should not exceed a magnitude of 2.6VP-P. The frequency of the signal should not exceed 80MHz for the MAX1181. The frequency of the sinusoidal input signal determines the sampling frequency (fCLK) of the ADC. A differential line receiver (U2) processes the input signal to generate the CMOS clock signal. The signal’s duty cycle can be adjusted with potentiometer R34. A clock signal with a 50% duty cycle (recommended) can be achieved by adjusting R34 until 1.20V is produced across test points TP1 and TP2, when the analog voltage supply is set to 3.0V (40% of the analog power supply). The clock signal is available at the J1-J43 pin (CK), which can be used to synchronize the output signal to the logic analyzer. _______________________________________________________________________________________ 3 Evaluates: MAX1180–MAX1186/MAX1190 Note: Both input channels may be configured identically or differently. Evaluates: MAX1180–MAX1186/MAX1190 MAX1181 Evaluation Kit Input Signal The MAX1181 accepts differential or single-ended analog input signals applied to Channels A or B. The EV kit requires only single-ended analog input signals, with an amplitude of less than 2VP-P provided by the user. During single-ended operation the signal is applied directly to the ADC, while in differential mode, an onboard transformer takes the single-ended analog input and generates a differential analog signal at the ADCs differential input pins. To evaluate single-ended signal input, connect the input signal to the S/E_INA (Channel A) or S/E_INB (Channel B) SMA connectors. To evaluate differential signals, connect the input signal to the D/E_INA (Channel A) or D/E_INB (Channel B) SMA connectors. For single-ended or differential operation, see Table 1 for jumper configuration. Note: When a differential signal is applied to the ADC, the positive and negative input pins of the ADC each receive half of the input signal supplied at SMA connector D/E_INA(D/E_INB) centered at the common mode voltage of VADUT/2. Output Enable/Power-Down/Sleep Modes The MAX1181 EV kit also features jumpers that allow the user to enable or disable certain functions or the entire data converter. Jumper JU6 controls the Sleep mode, jumper JU7 controls a full power-down mode, and jumper JU8 controls the outputs enable/disable mode. Operating the ADC in these modes supports the reduction of the IC’s overall power consumption. Refer to Table 2 to configure the board and operate the ADC in these modes. Table 1. Single-Ended/Differential Operation Jumper Configuration JUMPER SHUNT STATUS PIN CONNECTION 1 and 2 INA+ pin connected to SMA connector S/E_INA and INA- pin connected to COM pin Analog input signal is applied to the ADC’s Channel A as a single-ended input 2 and 3 INA+ and INA- pins connected to transformer T1 Analog input signal is applied to Channel A as a differential input 1 and 2 INB+ pin connected to SMA connector S/E_INB and INB- pin connected to COM pin Analog input signal is applied to the ADC’s Channel B as a single-ended input 2 and 3 INB+ and INB- pins connected to transformer T2 Analog input signal is applied to Channel B as a differential input EV KIT OPERATION JU1, JU2 JU3, JU4 Table 2. Output Enable/Power-Down/Sleep Mode Configuration JUMPER JU6 JU7 JU8 4 SHUNT STATUS 1 and 2 PIN CONNECTION SLEEP connected to VDDUT EV KIT OPERATION MAX1181 is disabled except for the internal reference 2 and 3 SLEEP connected to DGND MAX1181 in normal operation mode 1 and 2 PD connected to VDDUT MAX1181 is powered down 2 and 3 PD connected to DGND MAX1181 in normal operation mode 1 and 2 OE connected to VDDUT Digital outputs disabled 2 and 3 OE connected to DGND Digital output enabled _______________________________________________________________________________________ MAX1181 Evaluation Kit Output Signal The MAX1181 requires an input voltage reference at its REFIN pin to set the full-scale analog signal voltage input. The ADC has a stable on-chip voltage reference of 2.048V that can be accessed at REFOUT. The EV kit was designed to use the on-chip voltage reference by connecting REFIN to REFOUT through resistor R20. The user can externally adjust the reference level, and hence the full-scale range, by installing a resistor at the R19 pad. The adjusted reference level can be calculated by applying the following equation: The MAX1181 features two 10-bit, parallel, CMOS-compatible, digital outputs channels (Channels A and B). The digital output coding can be chosen to be either in two’s complement format or straight offset binary format by configuring jumper JU5. Refer to Table 3 for jumper configuration. Two drivers buffer the ADC’s Channel A and B digital outputs. The buffer is able to drive large capacitive loads, which may be present at the logic analyzer connection, without compromising the digital output signal. The outputs of the buffers are connected to a 50-pin header (J1) located on the right side of the EV kit, where the user can connect a logic analyzer or data-acquisition system. Refer to Table 4 for channel and bit location on header J1. R19 VREFIN = × VREFOUT R19 + R20 where R19 is the value of the resistor installed, R20 is a 10kΩ resistor, and VREFOUT is 2.048V. Alternatively, the user can apply a stable, low noise, external voltage reference directly at the REFIN pad to set the full scale. Table 3. Output Format JUMPER SHUNT STATUS JU5 PIN CONNECTION EV KIT OPERATION 1 and 2 T/B connected to VDDUT Digital output in two's complement 2 and 3 T/B connected to DGND Digital output in straight offset binary Table 4. Output Bit Location (Nonmultiplexed/Multiplexed Output Operation) CHANNEL A/B STATE BIT D0 BIT D1 BIT D2 BIT D3 BIT D4 BIT D5 BIT D6 BIT D7 BIT D8 BIT D9 NONMULTIPLEXED OUTPUT OPERATION A CLK ↑ N/A J1-19 A0 J1-17 A1 J1-15 A2 J1-13 A3 J1-11 A4 J1-9 A5 J1-7 A6 J1-5 A7 J1-3 A8 J1-1 A9 B CLK ↑ N/A J1-23 B0 J1-25 B1 J1-27 B2 J1-29 B3 J1-31 B4 J1-33 B5 J1-35 B6 J1-37 B7 J1-39 B8 J1-41 B9 MULTIPLEXED OUTPUT OPERATION* A CLK ↓ J1-23 1 J1-19 A0 J1-17 A1 J1-15 A2 J1-13 A3 J1-11 A4 J1-9 A5 J1-7 A6 J1-5 A7 J1-3 A8 J1-1 A9 B CLK ↑ J1-23 0 J1-19 A0 J1-17 A1 J1-15 A2 J1-13 A3 J1-11 A4 J1-9 A5 J1-7 A6 J1-5 A7 J1-3 A8 J1-1 A9 *For multiplexed output operation, Channel A and Channel B data is captured with a single 10-bit bus. Leave header designators J25 (B1) through J41 (B9) open. _______________________________________________________________________________________ 5 Evaluates: MAX1180–MAX1186/MAX1190 Reference Voltage S/E_INB D/E_INB D/E_INA S/E_INA VADUT AGND Figure 1. MAX1181 EV Kit Schematic _______________________________________________________________________________________ R1 OPEN R5 49.9Ω 1% R4 49.9Ω 1% R16 OPEN C4 0.1µF C3 0.1µF R3 49.9Ω 1% R35 49.9Ω 1% C12 10µF 10V 3 2 1 S/E_B T2 R34 5kΩ 4 5 6 4 3 6 5 COM T1 C18 0.1µF JU1 2 VA R36 2kΩ 1% TP2 TP1 R37 4.02kΩ 1% C52 0.1µF C51 0.1µF C19 0.1µF 2 1 DGND VD VDDUT C5 0.1µF VADUT C15 10µF 10V C1 0.1µF C2 0.1µF R2 49.9Ω 1% CLOCK C17 0.1µF C16 0.1µF VA 1 VA 2 6 3 C30 1000pF 1 3 3 1 C33 0.1µF OUT2 6 GND 5 2 IN1+ 3 IN2+ C23 0.1µF C22 2.2µF 10V R18 24.9Ω 1% R17 24.9Ω 1% R7 0Ω R8 100Ω C26 22pF 10V R16 24.9Ω 1% C29 22pF C28 22pF C27 0.1µF C25 22pF C24 22pF C21 0.1µF C11 0.1µF C9 0.1µF C7 0.1µF C20 2.2µF 10V C10 2.2µF 10V C8 2.2µF 10V C6 OPEN R15 24.9Ω 1% REFIN C34 0.1µF VADUT VADUT VADUT COM REFIN U2 MAX9113 1 8 IN1VCC 4 IN2OUT1 7 R12 4.02kΩ 1% C32 2.2µF 10V JU3 2 R10 2kΩ 1% R14 2kΩ 1% R13 2kΩ 1% R9 2kΩ 1% REFIN JU4 2 3 1 COM JU2 2 C31 0.1µF R11 6.04kΩ 1% COM 3 1 S/E_B S/E_B C13 10µF 10V VDDUT C14 10µF 10V VD 1A1 12 11 10 9 8 7 6 5 4 3 2 1 C35 2.2µF 10V 14 13 47 15 R38 3.9Ω R33 OPEN R32 OPEN 16 T/B REFOUT 44 18 SLEEP D9A VDDUT JU6 1 2 3 VDDUT JU7 1 2 3 19 PO 42 OE JU8 1 2 3 20 D6A R41 100Ω D9B 21 D9B D6A 41 R24 R25 100Ω 100Ω D7A MAX1181 U1 D8A D7A R23 100Ω 43 D8A R22 100Ω D9A VDDUT JU5 1 2 3 17 VDDUT GND C36 0.1µF VDD R31 OPEN VADUT VDD GND CLK VDD GND INB+ INB- GND VDD INA- INA+ GND VDD COM 48 REFN REFP REFIN R20 R21 10kΩ 100Ω 1% 46 45 R19 OPEN 38 D3A 24 D7B D6B D5B D4B D3B D2B D1B D0B DGND OVDD OVDD DGND D0A 25 26 27 28 29 30 31 32 33 34 35 D1A 36 D2A 37 D2A D6B R44 100Ω D7B 23 R43 100Ω D8B R42 100Ω 39 D4A D8B 22 40 D5A D3A R27 R28 100Ω 100Ω D4A R26 100Ω D5A R45 100Ω R46 100Ω R47 100Ω R48 100Ω R49 100Ω R50 100Ω C37 0.1µF R30 100Ω R29 100Ω C38 0.1µF D5B D4B D3B D2B D1B D0B D0A D1A C39 0.1µF C40 2.2pF 10V FERRITE L2 VDDUT Evaluates: MAX1180–MAX1186/MAX1190 MAX1181 Evaluation Kit _______________________________________________________________________________________ VDB C45 0.1µF J1-1 J1-3 J1-5 J1-7 J1-9 J1-11 J1-13 J1-15 J1-17 J1-19 C48 0.1µF R51 49.9Ω 1% R52 49.9Ω 1% R53 49.9Ω 1% R54 49.9Ω 1% R55 49.9Ω 1% R56 49.9Ω 1% R57 49.9Ω 1% R58 49.9Ω 1% R59 49.9Ω 1% R60 49.9Ω 1% VDB 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 40E 4Y4 4Y3 GND 4Y2 4Y1 VCC 3Y4 3Y3 GND 3Y2 3Y1 2Y4 2Y3 GND 2Y2 2Y1 VCC 1Y4 1Y3 GND 1Y2 1Y1 10E 30E 4A4 4A3 GND 4A2 4A1 VCC 3A4 3A3 GND 3A2 3A1 2A4 2A3 GND 2A2 2A1 VCC 1A4 1A3 GND 1A2 1A1 20E 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D9A D8A D7A D6A D5A D4A D3A D2A D1A D0A VDB C42 0.1µF C44 0.1µF C41 2.2µF 10V VDB VDB L1 VDB C49 0.1µF VD J1-23 J1-25 J1-27 J1-29 J1-31 J1-33 J1-35 J1-37 J1-39 J1-41 J1-43 C43 0.1µF R70 49.9Ω 1% R69 49.9Ω 1% R68 49.9Ω 1% R67 49.9Ω 1% R66 49.9Ω 1% R65 49.9Ω 1% R64 49.9Ω 1% R63 49.9Ω 1% R62 49.9Ω 1% R61 49.9Ω 1% VDB R71 49.9Ω 1% 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 40E 4Y4 4Y3 GND 4Y2 4Y1 VCC 3Y4 3Y3 GND 3Y2 3Y1 2Y4 2Y3 GND 2Y2 2Y1 VCC 1Y4 1Y3 GND 1Y2 1Y1 10E 30E 4A4 4A3 GND 4A2 4A1 VCC 3A4 3A3 GND 3A2 3A1 2A4 2A3 GND 2A2 2A1 VCC 1A4 1A3 GND 1A2 1A1 20E U4 SN74ALVCH16244 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B C50 OPEN VDB VDB C46 0.1µF C47 0.1µF 1A1 J1-50 J1-49 J1-48 J1-47 J1-46 J1-45 J1-44 J1-42 J1-40 J1-38 J1-36 J1-34 J1-32 J1-30 J1-28 J1-26 J1-24 J1-22 J1-21 J1-20 J1-18 J1-16 J1-14 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 Evaluates: MAX1180–MAX1186/MAX1190 1 U3 SN74ALVCH16244 MAX1181 Evaluation Kit Figure 2. MAX1181 EV Kit Schematic (continued) 7 Evaluates: MAX1180–MAX1186/MAX1190 MAX1181 Evaluation Kit 1.0" Figure 3. MAX1181 EV Kit Component Placement Guide— Component Side 1.0" Figure 5. MAX1181 EV Kit PC Board Layout—Ground Planes 8 1.0" Figure 4. MAX1181 EV Kit PC Board Layout—Component Side 1.0" Figure 6. MAX1181 EV Kit PC Board Layout—Power Planes _______________________________________________________________________________________ MAX1181 Evaluation Kit 1.0" Figure 7. MAX1181 EV Kit PC Layout—Solder Side Figure 8. MAX1181 EV Kit Component Placement Guide— Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Evaluates: MAX1180–MAX1186/MAX1190 1.0"