PIC16(L)F178X Memory Programming

PIC16(L)F178X
PIC16(L)F178X Memory Programming Specification
This document includes the
programming specifications for the
following devices:
1.1.2
LOW-VOLTAGE ICSP
PROGRAMMING
• PIC16F1782
• PIC16LF1782
• PIC16F1783
• PIC16LF1783
• PIC16F1784
• PIC16LF1784
In Low-Voltage ICSP mode, the PIC16(L)F178X
devices can be programmed using a single VDD source
in the operating range. The MCLR/VPP pin does not
have to be brought to a different voltage, but can
instead be left at the normal operating voltage.
• PIC16F1786
• PIC16LF1786
1.1.2.1
• PIC16F1787
• PIC16LF1787
• PIC16F1788
• PIC16LF1788
• PIC16F1789
• PIC16LF1789
1.0
The LVP bit in Configuration Word 2 enables singlesupply (low-voltage) ICSP programming. The LVP bit
defaults to a ‘1’ (enabled) from the factory. The LVP bit
may only be programmed to ‘0’ by entering the HighVoltage ICSP mode, where the MCLR/VPP pin is raised
to VIHH. Once the LVP bit is programmed to a ‘0’, only
the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
OVERVIEW
The device can be programmed using either the highvoltage In-Circuit Serial Programming™ (ICSP™)
method or the low-voltage ICSP method.
1.1
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP pin.
Hardware Requirements
1.1.1
Single-Supply ICSP Programming
HIGH-VOLTAGE ICSP
PROGRAMMING
2: While in Low-Voltage ICSP mode, MCLR
is always enabled, regardless of the
MCLRE bit, and the port pin can no
longer be used as a general purpose
input.
In High-Voltage ICSP mode, the device requires two
programmable power supplies: one for VDD and one for
the MCLR/VPP pin.
1.2
Pin Utilization
Five pins are needed for ICSP programming. The pins
are listed in Table 1-1.
TABLE 1-1:
Pin Name
PIN DESCRIPTIONS DURING PROGRAMMING FOR PIC16(L)F178X
During Programming
Function
Pin Type
Pin Description
RB6
ICSPCLK
I
RB7
ICSPDAT
I/O
Data Input/Output – Schmitt Trigger Input
Program/Verify mode
P(1)
Program Mode Select/Programming Power Supply
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
RE3/MCLR/VPP
Clock Input – Schmitt Trigger Input
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
 2011-2012 Microchip Technology Inc.
DS41457E-page 1
PIC16(L)F178X
2.0
DEVICE PINOUTS
The pin diagrams for the PIC16(L)F178X family are
shown in Figure 2-1 to Figure 2-7. The pins that are
required for programming are listed in Table 1-1 and
shown in bold lettering in the pin diagrams.
FIGURE 2-1:
28-PIN PDIP/SOIC/SSOP DIAGRAM FOR PIC16(L)F1782/3/6/8
28-PIN PDIP, SOIC, SSOP
FIGURE 2-2:
1
28
2
27
3
26
4
5
6
7
8
9
10
11
PIC16(L)F1782/3/6/8
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3
25
24
23
22
21
20
19
18
12
17
13
16
14
15
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
28-PIN UQFN PACKAGE DIAGRAM FOR PIC16(L)F1782/1783
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28-PIN UQFN
8
9
10
11
12
13
14
1
21
2
20
3 PIC16(L)F1782/1783 19
4
18
5
17
6
16
7
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5
VSS
RA7
RA6
DS41457E-page 2
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 2-3:
28-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1786/1788
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28-PIN QFN
8
9
10
11
12
13
14
1
21
2
20
3PIC16(L)F1786/178819
4
18
5
17
6
16
7
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5
VSS
RA7
RA6
FIGURE 2-4:
40-PIN PDIP PACKAGE DIAGRAM FOR PIC16(L)F1784/7/9
40-PIN PDIP
40
ICSPDAT/RB7
2
39
ICSPCLK/RB6
RA1
3
38
RB5
RA2
4
37
RB4
RA3
5
36
RB3
RA4
6
35
RB2
RA5
7
34
RB1
RE0
8
33
RB0
RE1
 2011-2012 Microchip Technology Inc.
9
RE2
10
VDD
11
VSS
12
RA7
13
PIC16(L)F1784/7/9
1
RA0
VPP/MCLR/RE3
32
VDD
31
VSS
30
RD7
29
RD6
28
RD5
RD4
RA6
14
27
RC0
15
26
RC7
RC1
16
25
RC6
RC2
17
24
RC5
RC3
18
23
RC4
RD0
19
22
RD3
RD1
20
21
RD2
DS41457E-page 3
PIC16(L)F178X
FIGURE 2-5:
40-PIN UQFN PACKAGE DIAGRAM FOR PIC16(L)F1784/7/9
40
39
38
37
36
35
34
33
32
31
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
40-PIN UQFN
PIC16(L)F1784/7/9
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
FIGURE 2-6:
44-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1784/7/9
12
13
14
15
16
17
18
19
20
21
22
1
33 RA6
2
32 RA7
3
31 NC
4
30 VSS
5
29 NC
PIC16(L)F1784/7/9
6
28 VDD
7
27 RE2
8
26 RE1
9
25 RE0
10
24 RA5
11
23 RA4
RB3
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
RB0
RB1
RB2
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44-PIN QFN
DS41457E-page 4
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 2-7:
44-PIN TQFP PACKAGE DIAGRAM FOR PIC16(L)F1784/7/9
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5 PIC16(L)F1784/7/9
6
7
8
9
10
11
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
44-PIN TQFP
 2011-2012 Microchip Technology Inc.
DS41457E-page 5
PIC16(L)F178X
3.0
MEMORY MAP
The memory is broken into two sections: program
memory and configuration memory. Only the size of the
program memory changes between devices, the
configuration memory remains the same.
DS41457E-page 6
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 3-1:
PIC16(L)F1782 PROGRAM MEMORY MAPPING
2 KW
0000h
07FFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Calibration Word 5
800Fh
Calibration Word 6
8010h
Reserved
8011h
Calibration Word 8
8002h
Calibration Word 9
8013h
Reserved
8014h-81FFh
Reserved
Implemented
Maps to
0-07FF
7FFFh
8000h
Program Memory
Implemented
8200h
 2011-2012 Microchip Technology Inc.
Maps to
8000-81FF
Configuration Memory
FFFFh
DS41457E-page 7
PIC16(L)F178X
FIGURE 3-2:
PIC16(L)F1783/4 PROGRAM MEMORY MAPPING
4 KW
0000h
0FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Calibration Word 5
800Fh
Calibration Word 6
8010h
Reserved
8011h
Calibration Word 8
8002h
Calibration Word 9
8013h
Reserved
8014h-81FFh
Reserved
Implemented
Maps to
0-0FFF
7FFFh
8000h
Program Memory
Implemented
8200h
DS41457E-page 8
Maps to
8000-81FF
Configuration Memory
FFFFh
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 3-3:
PIC16(L)F1786/7 PROGRAM MEMORY MAPPING
8 KW
0000h
1FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Calibration Word 5
800Fh
Calibration Word 6
8010h
Reserved
8011h
Calibration Word 8
8002h
Calibration Word 9
8013h
Reserved
8014h-81FFh
Reserved
Implemented
Maps to
0-1FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
 2011-2012 Microchip Technology Inc.
Maps to
8000-81FF
Configuration Memory
FFFFh
DS41457E-page 9
PIC16(L)F178X
FIGURE 3-4:
PIC16(L)F1788/9 PROGRAM MEMORY MAPPING
16 KW
0000h
3FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Calibration Word 5
800Fh
Calibration Word 6
8010h
Reserved
8011h
Calibration Word 8
8002h
Calibration Word 9
8013h
Reserved
8014h-81FFh
Reserved
Implemented
Maps to
0-3FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
DS41457E-page 10
Maps to
8000-81FF
Configuration Memory
FFFFh
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
3.1
User ID Location
3.2
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 8000h-8003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
Note:
Device ID
This device family has two formats for the device/
revision ID. Both formats have the device ID at
address 8006h.
3.2.1
MPLAB® IDE only displays the 7 Least
Significant bits (LSb) of each user ID
location, the upper bits are not read. It is
recommended that only the 7 LSbs be
used if MPLAB IDE is the primary tool
used to read these addresses.
DEVICE/REVISION ID –
PIC16(L)F1782/3/4/6/7 DEVICES
The device/revision ID word is located at 8006h. The
upper nine bits contain the device ID, and the lower
five bits contain the revision ID. This location is readonly and cannot be erased or modified.
DEVICEID: DEVICE ID REGISTER(1),(2)
REGISTER 3-1:
R
R
R
R
R
R
DEV<8:3>
bit 13
R
R
bit 8
R
R
R
DEV<2:0>
R
R
R
REV<4:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
x = Bit is unknown
‘1’ = Bit is set
bit 13-5
DEV<8:0>: Device ID bits
These bits are used to identify the part number.
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision.
Note 1:
2:
This location cannot be written.
Except PIC16(L)F1788/9.
TABLE 3-1:
DEVICE ID VALUES (PIC16(L)F1782/3/4/6/7)
DEVICE
DEVICEID<13:0> VALUES
DEV<8:0>
REV<4:0>
PIC16F1782
10 1010 000
x xxxx
PIC16LF1782
10 1010 101
x xxxx
PIC16F1783
10 1010 001
x xxxx
PIC16LF1783
10 1010 110
x xxxx
PIC16F1784
10 1010 010
x xxxx
PIC16LF1784
10 1010 111
x xxxx
PIC16F1786
10 1010 011
x xxxx
PIC16LF1786
10 1011 000
x xxxx
PIC16F1787
10 1010 100
x xxxx
PIC16LF1787
10 1011 001
x xxxx
 2011-2012 Microchip Technology Inc.
DS41457E-page 11
PIC16(L)F178X
3.2.2
DEVICE/REVISION ID –
PIC16(L)F1788/9 DEVICES
The 14-bit device ID word is located at 8006h and the
14-bit revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified.
REGISTER 3-2:
DEVICEID: DEVICE ID REGISTER(1),(2)
R
R
R
R
R
R
DEV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
x = Bit is unknown
‘1’ = Bit is set
DEV<13:0>: Device ID bits
Refer to Table 3-2 to determine what these bits will read on which device. A value of 3FFFh is invalid.
Note 1:
2:
This location cannot be written.
PIC16(L)F1788/9 devices only.
REGISTER 3-3:
REVISIONID: REVISION ID REGISTER(1),(2)
R
R
R
R
R
R
REV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
‘1’ = Bit is set
x = Bit is unknown
REV<13:0>: Revision ID bits
These bits are used to identify the device revision.
Note 1: This location cannot be written.
2: PIC16(L)F1788/9 devices only.
DS41457E-page 12
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
TABLE 3-2:
DEVICE ID VALUES (PIC16(L)F1788/9)
DEVICE
Device ID
Revision ID
PIC16F1788
302Bh
2xxxh
PIC16LF1788
302Dh
2xxxh
PIC16F1789
302Ah
2xxxh
PIC16LF1789
302Ch
2xxxh
3.3
Configuration Words
The device has two Configuration Words, Configuration
Word 1 (8007h) and Configuration Word 2 (8008h). The
individual bits within these Configuration Words are
used to enable or disable device functions such as the
Brown-out Reset, code protection and Power-up Timer.
3.4
Calibration Words
The internal calibration values are factory calibrated
and stored in the Calibration Word locations. See
Figure 3-1, Figure 3-2, Figure 3-3 and Figure 3-4 for
address information.
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
 2011-2012 Microchip Technology Inc.
DS41457E-page 13
PIC16(L)F178X
REGISTER 3-4:
CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
R/P-1
CPD
bit 8
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0 = CLKOUT function is enabled on RA6/CLKOUT
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 8
CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 7
CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port
pin’s WPU control bit.
bit 5
PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
Note 1:
2:
3:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off during an erase.
The entire program memory will be erased when the code protection is turned off.
DS41457E-page 14
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
REGISTER 3-4:
bit 2-0
Note 1:
2:
3:
CONFIGURATION WORD 1 (CONTINUED)
FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN
110 = ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN
101 = ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN
011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off during an erase.
The entire program memory will be erased when the code protection is turned off.
 2011-2012 Microchip Technology Inc.
DS41457E-page 15
PIC16(L)F178X
REGISTER 3-5:
CONFIGURATION WORD 2
R/P-1(1)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
bit 13
bit 8
U-1
U-1
R/P-1
U-1
U-1
U-1
—
—
VCAPEN
—
—
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = Low-voltage programming enabled
0 = MCLR/VPP must be used for programming high voltage
bit 12
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power Brown-out Reset Enable bit
1 = Low-Power Brown-out is disabled
0 = Low-Power Brown-out is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage, low trip point selected
0 = Brown-out Reset voltage, high trip point selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1 = 4xPLL enabled
0 = 4xPLL disabled
bit 7-6
Unimplemented: Read as ‘1’
bit 5
VCAPEN: Voltage Regulator Capacitor Enable for RA6 bits(2)
1 = VCAP functionality is disabled on RA6. (VDDCORE is not connected to the pad)
0 = VCAP functionality is enabled on RA6. (VDDCORE is connected to the pad)
bit 4-2
Unimplemented: Read as ‘1’
Note 1:
2:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
This bit is implemented on the LF devices only; otherwise, it is unimplemented and reads as ‘1’.
DS41457E-page 16
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
REGISTER 3-5:
bit 1-0
Note 1:
2:
CONFIGURATION WORD 2 (CONTINUED)
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory: PIC16(L)F1782:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control
4 kW Flash memory:PIC16(L)F1783/1784:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory: PIC16(L)F1786/1787:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory: PIC16(L)F1788/1789:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
This bit is implemented on the LF devices only; otherwise, it is unimplemented and reads as ‘1’.
 2011-2012 Microchip Technology Inc.
DS41457E-page 17
PIC16(L)F178X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1
High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
• VPP – First entry mode
• VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and RB6 and RB7 are driven by the user
application, the device will execute code. Since this
may prevent entry, VPP-first entry mode is strongly
recommended. See the timing diagram in Figure 8-2.
4.1.2
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2
Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16(L)F178X devices to be programmed using VDD
only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to ‘1’, the lowvoltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
2.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figures 8-8
and 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figures 8-8 and 8-9.
Note:
To enter LVP mode, the LSb of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired
operating voltage.
Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
DS41457E-page 18
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
4.3
Program/Verify Commands
These devices implement 13 programming commands,
each six bits in length. The commands are summarized
in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
TABLE 4-1:
COMMAND MAPPING FOR PIC16(L)F178X
Mapping
Command
Data/Note
Binary (MSb … LSb)
Hex
Load Configuration
x
0
0
0
0
0
00h
0, data (14), 0
Load Data For Program Memory
x
0
0
0
1
0
02h
0, data (14), 0
Load Data For Data Memory
x
0
0
0
1
1
03h
0, data (8), zero (6), 0
Read Data From Program Memory
x
0
0
1
0
0
04h
0, data (14), 0
Read Data From Data Memory
x
0
0
1
0
1
05h
0, data (8), zero (6), 0
Increment Address
x
0
0
1
1
0
06h
—
Reset Address
x
1
0
1
1
0
16h
—
Begin Internally Timed Programming
x
0
1
0
0
0
08h
—
Begin Externally Timed Programming
x
1
1
0
0
0
18h
—
End Externally Timed Programming
x
0
1
0
1
0
0Ah
—
Bulk Erase Program Memory
x
0
1
0
0
1
09h
Internally Timed
Bulk Erase Data Memory
x
0
1
0
1
1
0Bh
Internally Timed
Row Erase Program Memory
x
1
0
0
0
1
11h
Internally Timed
 2011-2012 Microchip Technology Inc.
DS41457E-page 19
PIC16(L)F178X
4.3.1
LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (User ID Locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the address to 8000h and
loads the data latches with one word of data (see
Figure 4-1).
Note:
The only way to get back to the program memory
(address 0) is to exit Program/Verify mode or issue the
Reset Address command after the configuration memory
has been accessed by the Load Configuration command.
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed
Programming or Begin Externally Timed Programming
command.
FIGURE 4-1:
Externally timed writes are not supported
for Configuration and Calibration bits. Any
externally timed write to the Configuration
or Calibration Word will have no effect on
the targeted word.
LOAD CONFIGURATION
1
2
5
4
3
6
2
1
16
15
TDLY
ICSPCLK
ICSPDAT
4.3.2
0
0
0
0
0
X
0
LSb
1
2
MSb 0
LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used to
load one 14-bit word into the data latches. The word
programs into program memory after the Begin Internally
Timed Programming or Begin Externally Timed
Programming command is issued (see Figure 4-2).
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
3
4
5
6
15
16
TDLY
ICSPCLK
ICSPDAT
DS41457E-page 20
0
1
0
0
0
X
0
LSb
MSb 0
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
4.3.3
LOAD DATA FOR DATA MEMORY
The Load Data for Data Memory command will load a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only eight bits wide and
thus, only the first eight bits of data after the Start bit will
be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow
the internal circuitry to reset properly (see Figure 4-3).
FIGURE 4-3:
LOAD DATA FOR DATA MEMORY COMMAND
1
2
5
4
3
2
1
6
16
15
TDLY
ICSPCLK
1
ICSPDAT
4.3.4
1
0
0
X
0
0
LSb
MSb 0
READ DATA FROM PROGRAM
MEMORY
The Read Data from Program Memory command will
transmit data bits out of the program memory map
currently accessed, starting with the second rising edge
of the clock input. The ICSPDAT pin will go into Output
mode on the first falling clock edge, and it will revert to
Input mode (high-impedance) after the 16th falling edge
of the clock. If the program memory is code-protected
(CP), the data will be read as zeros (see Figure 4-4).
FIGURE 4-4:
READ DATA FROM PROGRAM MEMORY
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
0
0
1
0
0
ICSPDAT
(from device)
x
Input
 2011-2012 Microchip Technology Inc.
X
LSb
MSb
Output
Input
DS41457E-page 21
PIC16(L)F178X
4.3.5
READ DATA FROM DATA MEMORY
The Read Data from Data Memory command will
transmit data bits out of the data memory starting with
the second rising edge of the clock input. The ICSPDAT
pin will go into Output mode on the second rising edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. The data memory is eight bits
wide, and therefore, only the first eight bits that are
output are actual data. If the data memory is codeprotected, the data is read as all zeros. A timing
diagram of this command is shown in Figure 4-5.
FIGURE 4-5:
READ DATA FROM DATA MEMORY COMMAND
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
1
1
0
0
0
X
ICSPDAT
(from device)
x
MSb
Input
Output
Input
4.3.6
LSb
INCREMENT ADDRESS
The address is incremented when this command is
received. It is not possible to decrement the address.
To reset this counter, the user must use the Reset
Address command or exit Program/Verify mode and
re-enter it.
If the address is incremented from address 7FFFh, it
will wrap-around to location 0000h. If the address is
incremented from FFFFh, it will wrap-around to location
8000h.
FIGURE 4-6:
INCREMENT ADDRESS
Next Command
1
2
4
3
1
6
5
2
3
TDLY
ICSPCLK
ICSPDAT
0
1
1
0
0
Address
DS41457E-page 22
X
X
X
X
Address + 1
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
4.3.7
RESET ADDRESS
The Reset Address command will reset the address to
0000h, regardless of the current value. The address is
used in program memory or the configuration memory.
FIGURE 4-7:
RESET ADDRESS
Next Command
1
2
4
3
5
2
1
6
3
TDLY
ICSPCLK
0
ICSPDAT
1
1
0
X
X
X
X
0000h
N
Address
4.3.8
1
BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time,
TPINT, for the programming to complete.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
The program memory address that is being
programmed is not erased prior to being programmed.
However, the EEPROM memory address that is being
programmed is erased prior to being programmed with
internally timed programming.
FIGURE 4-8:
BEGIN INTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
1
2
3
6
TPINT
ICSPCLK
ICSPDAT
0
 2011-2012 Microchip Technology Inc.
0
0
1
0
X
X
X
X
DS41457E-page 23
PIC16(L)F178X
4.3.9
BEGIN EXTERNALLY TIMED
PROGRAMMING
Externally timed writes are not supported for
Configuration and Calibration bits. Any externally timed
write to the Configuration or Calibration Word will have
no effect on the targeted word.
A Load Configuration, Load Data for Program Memory
or Load Data for Data Memory command must be given
before every Begin Programming command. Programming of the addressed memory will begin after this
command is received. To complete the programming,
the End Externally Timed Programming command
must be sent in the specified time window defined by
TPEXT. No internal erase is performed for the data
EEPROM, therefore, the device should be erased prior
to executing this command (see Figure 4-9).
FIGURE 4-9:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
4
3
5
6
2
1
3
TPEXT
ICSPCLK
0
ICSPDAT
4.3.10
0
0
1
0
X
1
1
0
END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands
(see Figure 4-10).
FIGURE 4-10:
END EXTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
2
1
3
6
TDIS
ICSPCLK
ICSPDAT
DS41457E-page 24
0
1
0
1
1
X
X
X
X
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
4.3.11
BULK ERASE PROGRAM MEMORY
After receiving the Bulk Erase Program Memory
command the erase will not complete until the time
interval, TERAB, has expired.
The Bulk Erase Program Memory command performs
two different functions dependent on the current state
of the address.
Note:
Address 0000h-7FFFh:
Program Memory is erased
The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
Configuration Words are erased
If CPD = 0, Data Memory is erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
If CPD = 0, Data Memory is erased
A Bulk Erase Program Memory command should not
be issued when the address is greater than 8008h.
FIGURE 4-11:
BULK ERASE PROGRAM MEMORY
1
2
3
5
4
Next Command
2
1
3
6
TERAB
ICSPCLK
ICSPDAT
4.3.12
0
1
0
0
1
BULK ERASE DATA MEMORY
X
X
X
After receiving the Bulk Erase Data Memory command,
the erase will not complete until the time interval,
TERAB, has expired.
To perform an erase of the data memory, after a Bulk
Erase Data Memory command, wait a minimum of
TERAB to complete Bulk Erase.
Note:
To erase data memory when data code-protect is active
(CPD = 0), the Bulk Erase Program Memory command
should be used.
FIGURE 4-12:
X
Data memory will not erase if codeprotected (CPD = 0).
BULK ERASE DATA MEMORY COMMAND
Wait a minimum of
TERAB
1
2
3
4
5
6
1
Next Command
2
ICSPCLK
ICSPDAT
 2011-2012 Microchip Technology Inc.
1
1
0
1
X
X
X
0
DS41457E-page 25
PIC16(L)F178X
4.3.13
ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase
an individual row. Refer to Table 4-2 for row sizes of
specific devices and the PC bits used to address them.
If the program memory is code-protected, the Row
Erase Program Memory command will be ignored.
When the address is 8000h-8008h the Row Erase
Program Memory command will only erase the user ID
locations regardless of the setting of the CP
Configuration bit.
After receiving the Row Erase Program Memory
command the erase will not complete until the time
interval, TERAR, has expired.
FIGURE 4-13:
ROW ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
1
2
3
6
TERAR
ICSPCLK
ICSPDAT
TABLE 4-2:
0
1
0
0
1
X
X
X
X
PROGRAMMING ROW AND LATCH SIZES
Devices
PC
Erase Row Size (Number of Write Row Size (Number of 14-bit
14-bit Memory Words)
Latches)
PIC16F1782
PIC16F1783
PIC16F1784
PIC16F1786
PIC16F1787
<15:5>
32
32
PIC16F1788
PIC16F1789
PIC16LF1782
PIC16LF1783
PIC16LF1784
PIC16LF1786
PIC16LF1787
PIC16LF1788
PIC16LF1789
DS41457E-page 26
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
5.0
PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store
the 14-bit words used for programming. Refer to
Table 4-2 for specific latch information. The data
latches allow the user to write the program words with
a single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration command is
used to load a single data latch. The data latch will hold
the data until the Begin Externally Timed Programming
or Begin Internally Timed Programming command is
given.
The data latches are aligned with the LSbs of the
address. The PS address bits indicated in Table 4-2 at
the time the Begin Externally Timed Programming or
Begin Internally Timed Programming command is
given will determine which memory row is written.
Writes cannot cross a physical row boundary. For
example, attempting to write from address 0002h0021h in a 32-latch device will result in data being
written to 0020h-003Fh.
If more than the maximum number of latches are
written without a Begin Externally Timed Programming
or Begin Internally Timed Programming command, the
data in the data latches will be overwritten. The
following figures show the recommended flowcharts for
programming.
 2011-2012 Microchip Technology Inc.
DS41457E-page 27
PIC16(L)F178X
FIGURE 5-1:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory(1)
Write User IDs
Write Data
Memory(3)
Verify Program
Memory
Verify User IDs
Verify Data
Memory
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1:
See Figure 5-2.
2:
See Figure 5-5.
3:
See Figure 5-6.
DS41457E-page 28
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 5-2:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
Memory(1, 2)
Program Cycle(3)
Read Data
from
Program Memory
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
All Locations
Done?
Yes
Done
Note 1:
This step is optional if the device has already been erased or has not been previously programmed.
2:
If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-8.
3:
See Figure 5-3 or Figure 5-4.
 2011-2012 Microchip Technology Inc.
DS41457E-page 29
PIC16(L)F178X
FIGURE 5-3:
ONE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Begin
Programming
Command
(Internally timed)
Wait TPINT
Begin
Programming
Command
(Externally timed)(1)
Wait TPEXT
End
Programming
Command
Wait TDIS
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
DS41457E-page 30
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 5-4:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Latch 1
Increment
Address
Command
Load Data
for
Program Memory
Latch 2
Increment
Address
Command
Load Data
for
Program Memory
Latch 32
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
 2011-2012 Microchip Technology Inc.
DS41457E-page 31
PIC16(L)F178X
FIGURE 5-5:
CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
One-word
Program Cycle(2)
(User ID)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
8004h?
Yes
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 1)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 2)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Note
1:
This step is optional if the device is erased or not previously programmed.
2:
See Figure 5-3.
DS41457E-page 32
Done
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 5-6:
DATA MEMORY PROGRAM FLOWCHART
Start
Bulk Erase
Data Memory
Data
Program Cycle(1)
Read Data
From Data
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
All Locations
Done?
Yes
Done
Note 1:
See Figure 5-7.
 2011-2012 Microchip Technology Inc.
DS41457E-page 33
PIC16(L)F178X
FIGURE 5-7:
DATA MEMORY PROGRAM CYCLE
Program Cycle
Load Data
for
Data Memory
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
FIGURE 5-8:
ERASE FLOWCHART
Start
Load Configuration
Bulk Erase
Program Memory
Bulk Erase
Data Memory
Done
Note:
This sequence does not erase the Calibration Words.
DS41457E-page 34
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
6.0
CODE PROTECTION
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as ‘0’. Further programming is disabled for the
program memory (0000h-7FFFh). Program memory
can still be programmed and read during program
execution.
Data memory is protected with its own Code-Protect bit
(CPD). When data code protection is enabled (CPD = 0),
all data memory locations read as ‘0’. Further
programming is disabled for the data memory. Data
memory can still be programmed and read during
program execution.
7.0
HEX FILE USAGE
In the hex file there are two bytes per program word
stored in the Intel® INHX32 hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: The
Configuration Word 1 is stored at 8007h. In the hex file
this will be referenced as 1000Eh-1000Fh).
7.1
Configuration Word
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
6.1
7.2
Program Memory
Code protection is enabled by programming the CP bit
in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
6.2
Data Memory
Data memory protection is enabled by programming
the CPD bit in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
Note:
To ensure system security, if CPD bit = 0,
the Bulk Erase Program Memory
command will also erase data memory.
 2011-2012 Microchip Technology Inc.
Device ID and Revision
If a device ID is present in the hex file at 1000Ch1000Dh (8006h on the part), the programmer should
verify the device ID (excluding the revision) against the
value read from the part. On a mismatch condition the
programmer should generate a warning message.
7.3
Data EEPROM
The programmer should be able to read data memory
information from a hex file and write data memory
contents to a hex file.
The physical address of the Data EEPROM memory
(byte data), starts at address 0000h. However, these
addresses are logically mapped above the Program
Memory Space starting at Word address F000h. This
provides a way of differentiating between the data and
program memory locations in this range. The format
for data memory storage is one data byte per 14-bit
word address location, LSb aligned. The hex file
format uses byte addressing, logically mapping Data
EEPROM memory starting at byte address 1E000h.
DS41457E-page 35
PIC16(L)F178X
7.4
Checksum Computation
The checksum is calculated by two different methods
dependent on the setting of the CP Configuration bit.
TABLE 7-1:
CONFIGURATION WORD
MASK VALUES
Config. Word 1
Mask
Config. Word 2
Mask
PIC16F1782
3FFFh
3F23h
PIC16LF1782
3FFFh
3F03h
Device
PIC16F1783
3FFFh
3F23h
PIC16LF1783
3FFFh
3F03h
PIC16F1784
3FFFh
3F23h
PIC16LF1784
3FFFh
3F03h
PIC16F1786
3FFFh
3F23h
PIC16LF1786
3FFFh
3F03h
PIC16F1787
3FFFh
3F23h
PIC16LF1787
3FFFh
3F03h
PIC16F1788
3FFFh
3F23h
PIC16LF1788
3FFFh
3F03h
PIC16F1789
3FFFh
3F23h
PIC16LF1789
3FFFh
3F03h
7.4.1
PROGRAM CODE PROTECTION
DISABLED
With the program code protection disabled, the
checksum is computed by reading the contents of the
PIC16(L)F178X program memory locations and adding
up the program memory data starting at address 0000h,
up to the maximum user addressable location (e.g.,
7FFh for the PIC16F1782). Any Carry bits exceeding 16
bits are ignored. Additionally, the relevant bits of the
Configuration Words are added to the checksum. All
unimplemented Configuration bits are masked to ‘0’.
Note:
Data memory
checksum.
DS41457E-page 36
does
not
effect
the
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
7.4.2
PROGRAM CODE PROTECTION
ENABLED
When the MPLAB IDE check box for Configure->ID
Memory...-> Use Unprotected Checksum is checked,
then the 16-bit checksum of the equivalent
unprotected device is computed and stored in the user
ID. Each nibble of the unprotected checksum is stored
in the Least Significant nibble of each of the four user
ID locations. The Most Significant checksum nibble is
stored in the user ID at location 8000h, the second
Most Significant nibble is stored at location 8001h, and
so forth for the remaining nibbles and ID locations.
The protected checksums in Table 7-2 assume that
the Use Unprotected Checksum box is checked.
The checksum of a code-protected device is computed
in the following manner: the Least Significant nibble of
each user ID is used to create a 16-bit value. The
Least Significant nibble of user ID location 8000h is the
Most Significant nibble of the 16-bit value. The Least
Significant nibble of user ID location 8001h is the
second Most Significant nibble, and so forth for the
remaining user IDs and 16-bit value nibbles. The
thusly created 16-bit value is summed with the
Configuration
Words.
All
unimplemented
Configuration bits are masked to ‘0’.
Note:
Data memory
checksum.
TABLE 7-2:
does
not
affect
the
CHECKSUMS
Config1
Config2
Checksum
Unprotected
Device
Unprotected Protected
Mask
Word
Mask
Blank
00AAh
First and
Last
Code-protected
Blank
00AAh
First and
Last
PIC16F1782
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
7722h
F878h
F5C4h
771Ah
PIC16F1783
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
6F22h
F078h
EDC4h
6F1Ah
PIC16F1784
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
6F22h
F078h
EDC4h
6F1Ah
PIC16F1786
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
5F22h
E078h
DDC4h
5F1Ah
PIC16F1787
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
5F22h
E078h
DDC4h
5F1Ah
PIC16F1788
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
3F22h
C078h
BDC4h
3F1Ah
PIC16F1789
3FFFh
3F7Fh
3FFFh
3FFFh
3F23h
3F22h
C078h
BDC4h
3F1Ah
PIC16LF1782
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
7702h
F858h
F584h
76DAh
PIC16LF1783
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
6F02h
F058h
ED84h
6EDAh
PIC16LF1784
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
6F02h
F058h
ED84h
6EDAh
PIC16LF1786
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
5F02h
E058h
DD84h
5EDAh
PIC16LF1787
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
5F02h
E058h
DD84h
5EDAh
PIC16LF1788
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
3F02h
C058h
BD84h
3EDAh
PIC16LF1789
3FFFh
3F7Fh
3FFFh
3FFFh
3F03h
3F02h
C058h
BD84h
3EDAh
 2011-2012 Microchip Technology Inc.
DS41457E-page 37
PIC16(L)F178X
8.0
ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute
maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS
Sym.
Characteristics
Standard Operating Conditions
Production tested at 25°C
Min.
Typ.
Max.
Units
VPEW
VBE
Programming Supply Voltages and Currents
PIC16LF178X
1.80
3.60
Supply Voltage
—
2.70
3.60
(VDDMIN(2), VDDMAX)
PIC16F178X
2.30
5.50
—
2.70
5.50
Read/Write and Row Erase operations
VDDMIN
—
VDDMAX
Bulk Erase operations
2.7
—
VDDMAX
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
3.0
mA
VDD
V
V
V
V
V
V
Conditions/Comments
FOSC 16 MHz
FOSC 32 MHz
FOSC 16 MHz
FOSC 32 MHz
VPP
IPP
Current on MCLR/VPP
—
—
600
A
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
—
—
1.0
s
I/O pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) input high level
0.8 VDD
—
—
V
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
ICSPDAT output high level
—
VDD-0.7
VDD-0.7
VDD-0.7
—
0.2 VDD
V
—
—
V
—
—
VSS+0.6
VSS+0.6
VSS+0.6
V
—
2.70
—
V
VOH
ICSPDAT output low level
VOL
Brown-out Reset Voltage:
BORV = 0 (high trip)
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
PIC16(L)F178X
VBOR
BORV = 1 (low trip)
TENTS
TENTH
TCKL
TCKH
TDS
TDH
TCO
TLZD
THZD
Note
—
2.40
—
V
PIC16F178X
—
1.90
—
V
PIC16LF178X
Programming Mode Entry and Exit
Programing mode entry setup time: ICSPCLK,
100
—
—
ns
ICSPDAT setup time before VDD or MCLR
Programing mode entry hold time: ICSPCLK,
250
—
—
s
ICSPDAT hold time after VDD or MCLR
Serial Program/Verify
Clock Low Pulse Width
100
—
—
ns
Clock High Pulse Width
100
—
—
ns
Data in setup time before clock
100
—
—
ns
Data in hold time after clock
100
—
—
ns
Clock to data out valid (during a
0
—
80
ns
Read Data command)
Clock to data low-impedance (during a
0
—
80
ns
Read Data command)
Clock to data high-impedance (during a
0
—
80
ns
Read Data command)
1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to Brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
DS41457E-page 38
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
TERAB
TERAR
Data input not driven to next clock input (delay
required between command/data or command/
command)
Bulk Erase cycle time
Row Erase cycle time
TPINT
Internally timed programming operation time
TDLY
Min.
Typ.
Max.
Units
1.0
—
—
s
—
—
—
—
ms
ms
—
—
5
2.5
2.5
5
5
ms
Conditions/Comments
Program memory
Configuration Words
Data EEPROM
Externally timed programming pulse
1.0
—
2.1
ms
Note 1
Time delay from program to compare
300
—
—
s
TDIS
(HV discharge time)
TEXIT
Time delay when exiting Program/Verify mode
1
—
—
s
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to Brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
TPEXT
8.1
AC Timing Diagrams
FIGURE 8-1:
FIGURE 8-3:
PROGRAMMING MODE
ENTRY – VDD FIRST
TENTS
TEXIT
VIHH
TENTH
VPP
VIHH
VPP
PROGRAMMING MODE
EXIT – VPP LAST
VIL
VDD
VIL
VDD
ICSPDAT
ICSPCLK
ICSPDAT
ICSPCLK
FIGURE 8-4:
PROGRAMMING MODE
EXIT – VDD LAST
TEXIT
FIGURE 8-2:
PROGRAMMING MODE
ENTRY – VPP FIRST
TENTS
TENTH
VIHH
VPP
VIL
VDD
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
ICSPDAT
ICSPCLK
 2011-2012 Microchip Technology Inc.
DS41457E-page 39
PIC16(L)F178X
FIGURE 8-5:
CLOCK AND DATA
TIMING
TCKL
TCKH
ICSPCLK
TDS TDH
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
FIGURE 8-6:
WRITE COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
X
X
X
X
X
1
6
2
15
16
ICSPCLK
ICSPDAT
Command
DS41457E-page 40
X
0 LSb
MSb
Payload
0
Next
Command
 2011-2012 Microchip Technology Inc.
PIC16(L)F178X
FIGURE 8-7:
READ COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
X
ICSPDAT
(from Programmer)
X
X
X
X
2
1
6
15
16
ICSPCLK
X
x
ICSPDAT
(from Device)
LSb
Payload
Command
FIGURE 8-8:
MSb
0
Next
Command
LVP ENTRY (POWERING UP)
VDD
MCLR
TENTS
TENTH
33 clocks
TCKH
TCKL
ICSPCLK
TDH
ICSPDAT
FIGURE 8-9:
LSb of Pattern
0
TDS
1
2
...
MSb of Pattern
31
LVP ENTRY (POWERED)
VDD
MCLR
TENTH
33 Clocks
TCKH
TCKL
ICSPCLK
TDH
ICSPDAT
LSb of Pattern
0
TDS
1
2
...
MSb of Pattern
31
Note 1: Sequence matching can start with no edge on MCLR first.
 2011-2012 Microchip Technology Inc.
DS41457E-page 41
PIC16(L)F178X
APPENDIX A:
REVISION HISTORY
Revision A (01/2011)
Original release of this document.
Revision B (02/2011)
Revised section 4.3.13; Added Table 4-2; Revised
section 5.0; Changed the Min. value for VDD in
Table 8-1.
Revision C (02/2012)
Added PIC16(L)F1784/6/7 devices; Added Figures 23, 2-4, 2-5, 2-6 and 3-3; Updated Registers 3-1, 3-2
and 3-3; Updated Table 3-1 and 4-2 with the
PIC16(L)F1784/6/7 devices; Updated section 7.3, Data
EEPROM; Updated Table 7-1 with the PIC16(L)F1784/
6/7 devices; Removed Examples 7-1 to 7-4; Added
Table 7-2, Checksums; Updated section 7.4.2,
Program Code Protection Enabled; Updated Table 8-1;
Other minor corrections.
Revision D (03/2012)
Updated Register 3-3, Table 7-1 and Table 7-2.
Revision E (09/2012)
Added PIC16(L)F1788/1789 devices; Updated Figure
2-1 to add PIC16(L)F1788 devices; Updated Figures
2-4, 2-5, 2-6 and 2-7 to add PIC16(L)F1789 devices;
Added new Figure 2-3; Updated Section 3.2, Device
ID; Updated Figure 3-3; Added Figure 3-4; Added Note
2 to Register 3-1; Added Register 3-2 and Register 33; Updated Register 3-5; Added Table 3-2; Updated
Table 4-2, Table 7-1 and Table 7-2 to include
PIC16(L)F1788/9 devices; Updated Table 8-1; Other
minor corrections.
DS41457E-page 42
 2011-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620765678
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2011-2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41457E-page 43
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS41457E-page 44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
11/29/11
 2011-2012 Microchip Technology Inc.