PIC16(L)F157X Memory Programming

PIC16(L)F157X
PIC16(L)F157X Memory Programming Specification
1.1.2
This document includes the
programming specifications for the
following devices:
LOW-VOLTAGE ICSP
PROGRAMMING
• PIC16F1574
• PIC16LF1574
• PIC16F1575
• PIC16LF1575
• PIC16F1578
• PIC16LF1578
In Low-Voltage ICSP mode, these devices can be
programmed using a single VDD source in the
operating range. The MCLR/VPP pin does not have to
be brought to a different voltage, but can instead be left
at the normal operating voltage.
• PIC16F1579
• PIC16LF1579
1.1.2.1
1.0
The LVP bit in Configuration Word 2 enables singlesupply (low-voltage) ICSP programming. The LVP bit
defaults to a ‘1’ (enabled) from the factory. The LVP bit
may only be programmed to ‘0’ by entering the HighVoltage ICSP mode, where the MCLR/VPP pin is raised
to VIHH. Once the LVP bit is programmed to a ‘0’, only
the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
OVERVIEW
The device can be programmed using either the highvoltage In-Circuit Serial Programming™ (ICSP™)
method or the low-voltage ICSP method.
1.1
Hardware Requirements
1.1.1
Single-Supply ICSP Programming
HIGH-VOLTAGE ICSP
PROGRAMMING
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP pin.
In High-Voltage ICSP mode, the device requires two
programmable power supplies: one for VDD and one for
the MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, MCLR
is always enabled, regardless of the
MCLRE bit, and the port pin can no
longer be used as a general purpose
input.
1.2
Pin Utilization
Five pins are needed for ICSP programming. The pins
are listed in Table 1-1.
TABLE 1-1:
PROGRAMMING PIN DESCRIPTIONS
During Programming
Pin Name
Function
Pin Type
Pin Description
ICSPCLK
ICSPCLK
I
ICSPDAT
ICSPDAT
I/O
Data Input/Output – Schmitt Trigger Input
Program/Verify mode
P(1)
Program Mode Select/Programming Power Supply
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
MCLR/VPP
Clock Input – Schmitt Trigger Input
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
 2014 Microchip Technology Inc.
DS40001766A-page 1
PIC16(L)F157X
2.0
DEVICE PINOUTS
The pin diagrams for the PIC16(L)F157X family are
shown below. The pins that are required for
programming are listed in Table 1-1 and shown in bold
lettering in the pin diagram.
Pin Diagram – 14-Pin PDIP, SOIC, TSSOP
1
14
2
13
VSS
RA0/ICSPDAT
12
RA1/ICSPCLK
11
RA2
10
RC0
9
RC1
8
RC2
MCLR/VPP/RA3
3
4
RC5
5
RC4
6
RC3
7
PIC16(L)F1574/5
VDD
RA5
RA4
VDD
NC
NC
VSS
Pin Diagram – 16-PIN QFN, UQFN
1
2
3
4
12
11
10
9
RA0
RA1
RA2
RC0
PI
RA5
RA4
MCLR/VPP/ RA3
RC5
C
16
(L
)F
15
74
/5
16 15 14 13
6
7
8
RC4
RC3
RC2
RC1
5
DS40001766A-page 2
 2014 Microchip Technology Inc.
PIC16(L)F157X
Pin Diagram – 20-Pin PDIP, SOIC
1
20
RA5
RA4
2
19
VSS
RA0
3
4
18
RA1
MCLR/VPP/RA3
17
RA2
RC5
5
16
RC0
RC4
6
15
RC1
RC3
RC6
7
14
RC2
13
RB4
RC7
9
12
RB5
RB7
10
11
RB6
15
14
13
12
11
RA1
RA2
RC0
RC1
RC2
8
PIC16(L)F1578/9
VDD
RA4
RA5
VDD
VSS
RA0
Pin Diagram – 20-Pin QFN, UQFN
RA3/MCLR/VPP
RC5
RC4
RC3
RC6
1
2
3
4
5
PI
C
16
(L
)F
15
78
/9
2019181716
RC7
RB7
RB6
RB5
RB4
6 7 8 9 10
 2014 Microchip Technology Inc.
DS40001766A-page 3
PIC16(L)F157X
3.0
MEMORY MAP
The memory is broken into two sections: program
memory and configuration memory.
FIGURE 3-1:
PIC16(L)F1574/8 PROGRAM MEMORY MAPPING
4 KW
0000h
0FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Reserved
800Dh
Reserved
800Eh
Reserved
800Fh
Reserved
8010h
Reserved
8011h-81FFh
Reserved
Implemented
Maps to
0-0FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
DS40001766A-page 4
Maps to
8000-81FF
Configuration Memory
FFFFh
 2014 Microchip Technology Inc.
PIC16(L)F157X
FIGURE 3-2:
PIC16(L)F1575/9 PROGRAM MEMORY MAPPING
8 KW
0000h
1FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Reserved
800Dh
Reserved
800Eh
Reserved
800Fh
Reserved
8010h
Reserved
8011h-81FFh
Reserved
Implemented
Maps to
0-1FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
 2014 Microchip Technology Inc.
Maps to
8000-81FF
Configuration Memory
FFFFh
DS40001766A-page 5
PIC16(L)F157X
3.1
User ID Location
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 8000h-8003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
Note:
3.2
MPLAB® IDE only displays the seven
Least Significant bits (LSb) of each user
ID location; the upper bits are not read. It
is recommended that only the seven LSbs
be used if MPLAB IDE is the primary tool
used to read these addresses.
Revision ID
The revision ID word is located at 8005h. This location
is read-only and cannot be erased or modified.
3.3
Device ID
The device ID word is located at 8006h. This location is
read-only and cannot be erased or modified.
3.4
Configuration Words
The device has two Configuration Words,
Configuration Word 1 (8007h) and Configuration Word
2 (8008h). The individual bits within these
Configuration Words are used to enable or disable
device functions such as the Brown-out Reset, code
protection and Power-up Timer.
3.5
Calibration Words
The internal calibration values are factory-calibrated
and stored in the Calibration Word locations. See
Figure 3-1 for address information.
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
DS40001766A-page 6
 2014 Microchip Technology Inc.
PIC16(L)F157X
DEVICEID: DEVICE ID REGISTER(1)
REGISTER 3-1:
R
R
R
R
R
R
DEV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
x = Bit is unknown
‘1’ = Bit is set
DEV<13:0>: Device ID bits
Refer to Table 3-1 to determine what these bits will read on which device. A value of 3FFFh is invalid.
Note 1:
This location cannot be written.
REVISIONID: REVISION ID REGISTER(1)
REGISTER 3-2:
R
R
R
R
R
R
REV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
‘1’ = Bit is set
x = Bit is unknown
REV<13:0>: Revision ID bits
These bits are used to identify the device revision.
Note 1: This location cannot be written.
TABLE 3-1:
DEVICE ID VALUES
Device ID
Revision ID
PIC16F1574
DEVICE
3000h
2xxxh
PIC16LF1574
3004h
2xxxh
PIC16F1575
3001h
2xxxh
PIC16LF1575
3005h
2xxxh
PIC16F1578
3002h
2xxxh
PIC16LF1578
3006h
2xxxh
PIC16F1579
3003h
2xxxh
PIC16LF1579
3007h
2xxxh
 2014 Microchip Technology Inc.
DS40001766A-page 7
PIC16(L)F157X
REGISTER 3-3:
CONFIGURATION WORD 1
U-1
U-1
R/P-1
—
—
CLKOUTEN
R/P-1
R/P-1
U-1
BOREN<1:0>(1)
—
bit 13
R/P-1
R/P-1
R/P-1
CP(2)
MCLRE
PWRTE(1)
bit 8
R/P-1
R/P-1
WDTE<1:0>
U-1
R/P-1
—
R/P-1
FOSC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13-12
Unimplemented: Read as ‘1’
bit 11
CLKOUTEN: Clock Out Enable bit
1 = OFF CLKOUT function is disabled. I/O or oscillator function on CLKOUT pin
0 = ON
CLKOUT function is enabled on CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = ON
Brown-out Reset enabled. The SBOREN bit is ignored.
10 = SLEEP Brown-out Reset enabled while running and disabled in Sleep. The SBOREN bit is ignored.
01 = SBODEN Brown-out Reset controlled by the SBOREN bit in the PCON register
00 = OFF
Brown-out Reset disabled. The SBOREN bit is ignored.
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Flash Program Memory Code Protection bit(2)
1 = OFF Code protection off. Program Memory can be read and written.
0 = ON Code protection on. Program Memory cannot be read or written externally.
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1 (ON):
This bit is ignored. MCLR/VPP pin function is MCLR; Weak pull-up enabled.
If LVP bit = 0 (OFF):
1 = ON MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = OFF MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of pin’s WPU
control bit.
bit 5
PWRTE: Power-up Timer Enable bit(1)
1 = OFF PWRT disabled
0 = ON PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = ON
WDT enabled. SWDTEN is ignored.
10 = SLEEP WDT enabled while running and disabled in Sleep. SWDTEN is ignored.
01 = SWDTEN WDT controlled by the SWDTEN bit in the WDTCON register
00 = OFF
WDT disabled. SWDTEN is ignored.
bit 2
Unimplemented: Read as ‘1’
bit 1-0
FOSC<1:0>: Oscillator Selection bits
11 = ECH
External Clock, High-Power mode: CLKI on OSC1/CLKI
10 = ECM
External Clock, Medium-Power mode: CLKI on OSC1/CLKI
01 = ECL
External Clock, Low-Power mode: CLKI on OSC1/CLKI
00 = INTOSC I/O function on OSC1/CLKI
Note 1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Once enabled, code-protect can only be disabled by bulk erasing the device.
DS40001766A-page 8
 2014 Microchip Technology Inc.
PIC16(L)F157X
REGISTER 3-4:
CONFIGURATION WORD 2
R/P-1
(1)
LVP
R/P-1
DEBUG
R/P-1
(2)
LPBOREN
R/P-1
(3)
BORV
R/P-1
R/P-1
STVREN
PLLEN
bit 13
bit 8
U-1
U-1
U-1
U-1
U-1
R/P-1
—
—
—
—
—
PPS1WAY
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = ON
Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE
Configuration bit is ignored.
0 = OFF High Voltage on MCLR/VPP must be used for programming
bit 12
DEBUG: Debugger Mode bit(2)
1 = OFF In-Circuit Debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins.
0 = ON
In-Circuit Debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger.
bit 11
LPBOREN: Low-Power Brown-out Reset Enable bit
1 = OFF Low-power Brown-out Reset is disabled
0 = ON
Low-power Brown-out Reset is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit(3)
1 = LOW Brown-out Reset voltage (Vbor), low trip point selected
0 = HIGH Brown-out Reset voltage (Vbor), high trip point selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON
Stack Overflow or Underflow will cause a Reset
0 = OFF Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1 = ON
4xPLL enabled
0 = OFF 4xPLL disabled
bit 7-3
Unimplemented: Read as ‘1’
bit 2
PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = ON
The PPSLOCK bit is permanently set after the first access sequence that sets it
0 = OFF The PPSLOCK bit can be set and cleared as needed by the PPSLOCK access sequence
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash memory: (PIC16(L)F1574/8):
11 = OFF Write protection off
10 = BOOT 000h to 1FFh write-protected, 200h to FFF may be modified by PMCON control
01 = HALF 000h to 7FFh write-protected, 800h to FFF may be modified by PMCON control
00 = ALL 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory: (PIC16(L)F1575/9)
11 = OFF Write protection off
10 = BOOT 000h to 01FFh write-protected, 200h to 1FFF may be modified by PMCON control
01 = HALF 000h to 0FFFh write-protected, 1000h to 1FFF may be modified by PMCON control
00 = ALL 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
Note 1:
2:
3:
This bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
See Vbor parameter for specific trip point voltages.
 2014 Microchip Technology Inc.
DS40001766A-page 9
PIC16(L)F157X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and is latched on the falling edge. In
Program/Verify mode, both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1
High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high voltage:
• VPP – First entry mode
• VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method,
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and RA0 and RA1 are driven by the user
application, the device will execute code. Since this
may prevent entry, VPP-First Entry mode is strongly
recommended. See the timing diagram in Figure 8-2.
4.1.2
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2
Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
devices to be programmed using VDD only, without high
voltage. When the LVP bit of the Configuration Word 2
register is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’. This can
only be done while in the High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode
requires the following steps:
1.
2.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figures 8-8
and 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figures 8-8 and 8-9.
Note:
To enter LVP mode, the LSb of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method,
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired
operating voltage.
Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
DS40001766A-page 10
 2014 Microchip Technology Inc.
PIC16(L)F157X
4.3
Program/Verify Commands
These devices implement 13 programming commands,
each six bits in length. The commands are summarized
in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay, 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
TABLE 4-1:
COMMAND MAPPING
Mapping
Data/Note
Command
Binary (MSb … LSb)
Hex
Load Configuration
x
0
0
0
0
0
00h
0, data (14), 0
Load Data For Program Memory
x
0
0
0
1
0
02h
0, data (14), 0
Read Data From Program Memory
x
0
0
1
0
0
04h
0, data (14), 0
Increment Address
x
0
0
1
1
0
06h
—
Reset Address
x
1
0
1
1
0
16h
—
Begin Internally Timed Programming
x
0
1
0
0
0
08h
—
Begin Externally Timed Programming
x
1
1
0
0
0
18h
—
End Externally Timed Programming
x
0
1
0
1
0
0Ah
—
Bulk Erase Program Memory
x
0
1
0
0
1
09h
Internally Timed
Row Erase Program Memory
x
1
0
0
0
1
11h
Internally Timed
 2014 Microchip Technology Inc.
DS40001766A-page 11
PIC16(L)F157X
4.3.1
LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (User ID Locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the address to 8000h and
loads the data latches with one word of data (see
Figure 4-1).
Note:
The only way to get back to the program memory
(address 0) is to exit Program/Verify mode or issue the
Reset Address command after the configuration memory
has been accessed by the Load Configuration command.
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then
programmed by issuing either the Begin Internally
Timed Programming or Begin Externally Timed
Programming command.
FIGURE 4-1:
Externally timed writes are not supported
for Configuration and Calibration bits. Any
externally timed write to the Configuration
or Calibration Word will have no effect on
the targeted word.
LOAD CONFIGURATION
1
2
5
4
3
6
2
1
16
15
TDLY
ICSPCLK
ICSPDAT
4.3.2
0
0
0
0
0
X
0
LSb
1
2
MSb 0
LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used to
load one 14-bit word into the data latches. The word
programs into program memory after the Begin Internally
Timed Programming or Begin Externally Timed
Programming command is issued (see Figure 4-2).
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
3
4
5
6
15
16
TDLY
ICSPCLK
ICSPDAT
DS40001766A-page 12
0
1
0
0
0
X
0
LSb
MSb 0
 2014 Microchip Technology Inc.
PIC16(L)F157X
4.3.3
READ DATA FROM PROGRAM
MEMORY
The Read Data from Program Memory command will
transmit data bits out of the program memory map
currently accessed, starting with the second rising edge
of the clock input. The ICSPDAT pin will go into Output
mode on the first falling clock edge, and it will revert to
Input mode (high-impedance) after the 16th falling edge
of the clock. If the program memory is code-protected
(CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3:
READ DATA FROM PROGRAM MEMORY
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
0
0
1
0
0
X
ICSPDAT
(from device)
x
MSb
Input
Output
Input
4.3.4
LSb
INCREMENT ADDRESS
The address is incremented when this command is
received. It is not possible to decrement the address.
To reset this counter, the user must use the Reset
Address command or exit Program/Verify mode and
re-enter it.
If the address is incremented from address 7FFFh, it
will wrap-around to location 0000h. If the address is
incremented from FFFFh, it will wrap-around to location
8000h (see Figure 4-4).
FIGURE 4-4:
INCREMENT ADDRESS
Next Command
1
2
3
4
2
1
6
5
3
TDLY
ICSPCLK
0
1
1
0
0
ICSPDAT
Address
 2014 Microchip Technology Inc.
X
X
X
X
Address + 1
DS40001766A-page 13
PIC16(L)F157X
4.3.5
RESET ADDRESS
The Reset Address command will reset the address to
0000h, regardless of the current value. The address is
used in program memory or the configuration memory
(see Figure 4-5).
FIGURE 4-5:
RESET ADDRESS
Next Command
1
2
5
4
3
1
6
2
3
TDLY
ICSPCLK
0
1
1
0
1
X
X
X
X
ICSPDAT
4.3.6
0000h
N
Address
BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time,
TPINT, in order for the programming to complete.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
The program memory address that is being
programmed is not erased prior to being programmed
(see Figure 4-6).
FIGURE 4-6:
BEGIN INTERNALLY TIMED PROGRAMMING
1
2
3
5
4
Next Command
2
1
3
6
TPINT
ICSPCLK
ICSPDAT
DS40001766A-page 14
0
0
0
1
0
X
X
X
X
 2014 Microchip Technology Inc.
PIC16(L)F157X
4.3.7
BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. To complete the programming, the End
Externally Timed Programming command must be sent
in the specified time window defined by TPEXT (see
Figure 4-7).
Externally timed writes are not supported for
Configuration and Calibration bits. Any externally timed
write to the Configuration or Calibration Word will have
no effect on the targeted word.
FIGURE 4-7:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
4
3
5
6
1
2
3
TPEXT
ICSPCLK
0
ICSPDAT
4.3.8
0
0
1
0
X
1
1
0
END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands
(see Figure 4-8).
FIGURE 4-8:
END EXTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
2
1
3
6
TDIS
ICSPCLK
ICSPDAT
 2014 Microchip Technology Inc.
0
1
0
1
1
X
X
X
X
DS40001766A-page 15
PIC16(L)F157X
4.3.9
BULK ERASE PROGRAM MEMORY
After receiving the Bulk Erase Program Memory
command, the erase will not complete until the time
interval, TERAB, has expired.
The Bulk Erase Program Memory command performs
two different functions dependent on the current state
of the address.
Note:
Address 0000h-7FFFh:
Program Memory is erased
The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
Configuration Words are erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
A Bulk Erase Program Memory command should not
be issued when the address is greater than 8008h.
FIGURE 4-9:
BULK ERASE PROGRAM MEMORY
1
2
4
3
5
Next Command
2
1
3
6
TERAB
ICSPCLK
ICSPDAT
4.3.10
1
0
0
0
1
X
X
X
X
ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase
an individual row. Refer to Table 4-2 for row sizes of
specific devices and the PC bits used to address them.
If the program memory is code-protected, the Row
Erase Program Memory command will be ignored.
When the address is 8000h-8008h, the Row Erase
Program Memory command will only erase the user ID
locations, regardless of the setting of the CP
Configuration bit.
After receiving the Row Erase Program Memory
command, the erase will not complete until the time
interval, TERAR, has expired (see Figure 4-10).
FIGURE 4-10:
ROW ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
2
1
3
6
TERAR
ICSPCLK
ICSPDAT
DS40001766A-page 16
1
0
0
0
1
X
X
X
X
 2014 Microchip Technology Inc.
PIC16(L)F157X
TABLE 4-2:
PROGRAMMING ROW AND LATCH SIZES
Devices
PC
Erase Row Size
(Number of 14-bit Words)
Write Row Size
(Number of 14-bit Latches)
<15:5>
32
32
PIC16F1574
PIC16LF1574
PIC16F1575
PIC16LF1575
PIC16F1578
PIC16LF1578
PIC16F1579
PIC16LF1579
 2014 Microchip Technology Inc.
DS40001766A-page 17
PIC16(L)F157X
5.0
PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store
the 14-bit words used for programming. Refer to
Table 4-2 for specific latch information. The data
latches allow the user to write the program words with
a single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration command is
used to load a single data latch. The data latch will hold
the data until the Begin Externally Timed Programming
or Begin Internally Timed Programming command is
given.
The lower bits of the address define the data latch
addresses and are aligned with the LSbs of the
address. The upper bits of the address define the Flash
program memory row. The upper bits that define the
row address are indicated in Table 4-2.
When the Begin Externally Timed Programming or
Begin Internally Timed Programming commands are
given, the data contained in the data latches will be
programmed into the corresponding addresses of the
row specified by the upper bits of the PC. Writes cannot
cross a physical row boundary. For example, in a
16-word latch device, attempting to write from address
0002h-0011h will result in data being written to 0010h001Fh.
If more than the maximum number of latches are
written without a Begin Externally Timed Programming
or Begin Internally Timed Programming command, the
data in the data latches will be overwritten. The
following figures show the recommended flowcharts for
programming.
DS40001766A-page 18
 2014 Microchip Technology Inc.
PIC16(L)F157X
FIGURE 5-1:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory(1)
Write User IDs
Verify Program
Memory
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1:
See Figure 5-2.
2:
See Figure 5-5.
 2014 Microchip Technology Inc.
DS40001766A-page 19
PIC16(L)F157X
FIGURE 5-2:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
Memory(1, 2)
Program Cycle(3)
Read Data
from
Program Memory
No
Data Correct?
Report
Programming
Failure
Yes
Increment
Address
Command
No
All Locations
Done?
Yes
Done
Note 1:
This step is optional if the device has already been erased or has not been previously programmed.
2:
If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6.
3:
See Figure 5-3 or Figure 5-4.
DS40001766A-page 20
 2014 Microchip Technology Inc.
PIC16(L)F157X
FIGURE 5-3:
ONE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Begin
Programming
Command
(Internally timed)
Wait TPINT
Begin
Programming
Command
(Externally timed)(1)
Wait TPEXT
End
Programming
Command
Wait TDIS
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
 2014 Microchip Technology Inc.
DS40001766A-page 21
PIC16(L)F157X
FIGURE 5-4:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Latch 1
Increment
Address
Command
Load Data
for
Program Memory
Latch 2
Increment
Address
Command
Load Data
for
Program Memory
Latch 32
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
DS40001766A-page 22
 2014 Microchip Technology Inc.
PIC16(L)F157X
FIGURE 5-5:
CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
One-word
Program Cycle(2)
(User ID)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
8004h?
Yes
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 1)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 2)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Note
1:
This step is optional if the device is erased or not previously programmed.
2:
See Figure 5-3.
 2014 Microchip Technology Inc.
Done
DS40001766A-page 23
PIC16(L)F157X
FIGURE 5-6:
ERASE FLOWCHART
Start
Load Configuration
Bulk Erase
Program Memory
Done
Note:
This sequence does not erase the Calibration Words.
DS40001766A-page 24
 2014 Microchip Technology Inc.
PIC16(L)F157X
6.0
CODE PROTECTION
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as ‘0’. Further programming is disabled for the
program memory (0000h-7FFFh). Program memory
can still be programmed and read during program
execution.
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
6.1
Program Memory
Code protection is enabled by programming the CP bit
in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
7.0
HEX FILE USAGE
In the hex file there are two bytes per program word
stored in the Intel® INHX32 hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: The
Configuration Word 1 is stored at 8007h. In the hex file
this will be referenced as 1000Eh-1000Fh).
7.1
TABLE 7-1:
CONFIGURATION WORD
MASK VALUES
Config. Word 1
Mask
Config. Word 2
Mask
PIC16F1574
0EFBh
3F07h
PIC16LF1574
0EFBh
3F07h
PIC16F1575
0EFBh
3F03h
PIC16LF1575
0EFBh
3F07h
PIC16F1578
0EFBh
3F07h
PIC16LF1578
0EFBh
3F07h
PIC16F1579
0EFBh
3F07h
PIC16LF1579
0EFBh
3F07h
Device
7.3.1
PROGRAM CODE PROTECTION
DISABLED
With the program code protection disabled, the
checksum is computed by reading the contents of the
program memory locations and adding up the program
memory data starting at address 0000h, up to the
maximum user addressable location. Any Carry bits
exceeding 16 bits are ignored. Additionally, the relevant
bits of the Configuration Words are added to the
checksum. All unimplemented Configuration bits are
masked to ‘0’.
Configuration Word
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
7.2
Device ID
If a device ID is present in the hex file at 1000Ch1000Dh (8006h on the part), the programmer should
verify the device ID against the value read from the
part. On a mismatch condition, the programmer should
generate a warning message.
7.3
Checksum Computation
The checksum is calculated by two different methods
dependent on the setting of the CP Configuration bit.
 2014 Microchip Technology Inc.
DS40001766A-page 25
PIC16(L)F157X
7.3.2
PROGRAM CODE PROTECTION
ENABLED
When the MPLAB IDE check box for Configure->ID
Memory...-> Use Unprotected Checksum is checked,
then the 16-bit checksum of the equivalent
unprotected device is computed and stored in the user
ID. Each nibble of the unprotected checksum is stored
in the Least Significant nibble of each of the four user
ID locations. The Most Significant checksum nibble is
stored in the user ID at location 8000h, the second
Most Significant nibble is stored at location 8001h, and
so forth for the remaining nibbles and ID locations.
The protected checksums in Table 7-2 assume that
the Use Unprotected Checksum box is checked.
The checksum of a code-protected device is computed
in the following manner: the Least Significant nibble of
each user ID is used to create a 16-bit value. The Least
Significant nibble of user ID location 8000h is the Most
Significant nibble of the 16-bit value. The Least
Significant nibble of user ID location 8001h is the
second Most Significant nibble, and so forth for the
remaining user IDs and 16-bit value nibbles. The
resulting 16-bit value is summed with the Configuration
Words. All unimplemented Configuration bits are
masked to ‘0’.
TABLE 7-2:
CHECKSUMS
Config1
Config2
Checksum
Unprotected
Device
Unprotected Protected
0EFBh
Word
3FFFh
Blank
00AAh
First and
Last
Blank
00AAh
First and
Last
3E02h
BF58h
8B84h
0CDAh
Mask
PIC16F1574
3FFFh
PIC16LF1574
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
3E02h
BF58h
8B84h
0CDAh
PIC16F1575
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
2E02h
AF58h
7B84h
FCDAh
PIC16LF1575
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
2E02h
AF58h
7B84h
FCDAh
PIC16F1578
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
3E02h
BF58h
8B84h
0CDAh
PIC16LF1578
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
3E02h
BF58h
8B84h
0CDAh
PIC16F1579
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
2E02h
AF58h
7B84h
FCDAh
PIC16LF1579
3FFFh
3F7Fh
0EFBh
3FFFh
3F07h
2E02h
AF58h
7B84h
FCDAh
DS40001766A-page 26
3F7Fh
Mask
3F07h
Code-protected
 2014 Microchip Technology Inc.
PIC16(L)F157X
8.0
ELECTRICAL SPECIFICATIONS
Refer to device-specific data sheet for absolute
maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS
Sym.
Characteristics
Standard Operating Conditions
Production tested at 25°C
Min.
Typ.
Max.
Units
VPEW
VBE
Programming Supply Voltages and Currents
PIC16LF1574/5/8/9
1.80
3.60
Supply Voltage
—
2.70
3.60
(VDDMIN(2), VDDMAX)
PIC16F1574/5/8/9
2.30
5.50
—
2.70
5.50
Read/Write and Row Erase operations
VDDMIN
—
VDDMAX
Bulk Erase operations
2.7
—
VDDMAX
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
3.0
mA
VDD
V
V
V
V
V
V
Conditions/Comments
FOSC 16 MHz
FOSC 32 MHz
FOSC 16 MHz
FOSC 32 MHz
VPP
IPP
Current on MCLR/VPP
—
—
600
A
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
—
—
1.0
s
I/O pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) input high level
0.8 VDD
—
—
V
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
ICSPDAT output high level
—
VDD-0.7
VDD-0.7
VDD-0.7
—
0.2 VDD
V
—
—
V
—
—
VSS+0.6
VSS+0.6
VSS+0.6
V
—
2.70
—
V
VOH
ICSPDAT output low level
VOL
Brown-out Reset Voltage:
BORV = 0 (high trip)
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
PIC16(L)F1574/5/8/9
VBOR
BORV = 1 (low trip)
TENTS
TENTH
TCKL
TCKH
TDS
TDH
TCO
TLZD
THZD
Note
—
2.45
—
V
PIC16F1574/5/8/9
—
1.90
—
V
PIC16LF1574/5/8/9
Programming Mode Entry and Exit
Programing mode entry setup time: ICSPCLK,
100
—
—
ns
ICSPDAT setup time before VDD or MCLR
Programing mode entry hold time: ICSPCLK, ICSPDAT
250
—
—
s
hold time after VDD or MCLR
Serial Program/Verify
Clock Low Pulse Width
100
—
—
ns
Clock High Pulse Width
100
—
—
ns
Data in setup time before clock
100
—
—
ns
Data in hold time after clock
100
—
—
ns
Clock to data out valid (during a
0
—
80
ns
Read Data command)
Clock to data low-impedance (during a
0
—
80
ns
Read Data command)
Clock to data high-impedance (during a
0
—
80
ns
Read Data command)
1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
 2014 Microchip Technology Inc.
DS40001766A-page 27
PIC16(L)F157X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
TERAB
TERAR
Data input not driven to next clock input (delay required
between command/data or command/command)
Bulk Erase cycle time
Row Erase cycle time
TPINT
Internally timed programming operation time
TDLY
Min.
Typ.
Max.
Units
1.0
—
—
s
—
—
—
—
ms
ms
—
—
5
2.5
2.5
5
ms
Conditions/Comments
Program memory
Configuration Words
TPEXT
Externally timed programming pulse
1.0
—
2.1
ms
Note 1
Time delay from program to compare
300
—
—
s
TDIS
(HV discharge time)
TEXIT
Time delay when exiting Program/Verify mode
1
—
—
s
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
8.1
AC Timing Diagrams
FIGURE 8-1:
FIGURE 8-3:
PROGRAMMING MODE
ENTRY – VDD FIRST
TENTS
PROGRAMMING MODE
EXIT – VPP LAST
TEXIT
VIHH
TENTH
VPP
VIHH
VIL
VPP
VDD
VIL
ICSPDAT
VDD
ICSPCLK
ICSPDAT
ICSPCLK
FIGURE 8-4:
PROGRAMMING MODE
EXIT – VDD LAST
TEXIT
FIGURE 8-2:
PROGRAMMING MODE
ENTRY – VPP FIRST
TENTS
VIHH
VPP
VIL
VDD
TENTH
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
ICSPDAT
ICSPCLK
DS40001766A-page 28
 2014 Microchip Technology Inc.
PIC16(L)F157X
FIGURE 8-5:
CLOCK AND DATA
TIMING
TCKL
TCKH
ICSPCLK
TDS TDH
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
FIGURE 8-6:
WRITE COMMAND – PAYLOAD TIMING
TDLY
1
2
3
4
5
X
X
X
X
X
2
1
6
15
16
ICSPCLK
0 LSb
X
MSb
ICSPDAT
FIGURE 8-7:
Next
Command
Payload
Command
0
READ COMMAND – PAYLOAD TIMING
TDLY
1
2
3
4
5
X
ICSPDAT
(from Programmer)
X
X
X
X
2
1
6
15
16
ICSPCLK
X
x
LSb
MSb
ICSPDAT
(from Device)
Command
 2014 Microchip Technology Inc.
Payload
0
Next
Command
DS40001766A-page 29
PIC16(L)F157X
FIGURE 8-8:
LVP ENTRY (POWERING UP)
VDD
MCLR
TENTS
TENTH
33 clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
ICSPDAT
FIGURE 8-9:
LSb of Pattern
0
1
2
...
MSb of Pattern
31
LVP ENTRY (POWERED)
VDD
MCLR
TENTH
33 Clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
ICSPDAT
LSb of Pattern
0
1
2
...
MSb of Pattern
31
Note 1: Sequence matching can start with no edge on MCLR first.
DS40001766A-page 30
 2014 Microchip Technology Inc.
PIC16(L)F157X
APPENDIX A:
REVISION HISTORY
Revision A (09/2014)
Initial release of this document.
 2014 Microchip Technology Inc.
DS40001766A-page 31
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-587-1
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001766A-page 32
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2014 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
 2014 Microchip Technology Inc.
03/25/14
DS40001766A-page 33