STEVAL-IME009V1 Evaluation board based on the STHV800 high voltage pulser Data brief Description The STEVAL-IME009V1 is a product evaluation board designed around the STHV800 8-channel high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications. The output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative BNCs. 16 preset waveforms are available to test the HV pulser under varying conditions. Features 8-channel outputs: high voltage and low voltage BNC connectors Load simulator using signal equivalent circuits Possibility to set up own load simulator 16 preset waveforms USB connector to connect STM32 with PC and supply power to it 4 MB serial Flash memory to host FPGA code and waveforms Memory expansion connector to add external serial Flash Connectors to supply high voltage and low voltage to the STHV800 output stage LEDs to monitor the power management stage Human machine interface to select, start and stop the generation of the preset waveforms 25 LEDs to monitor board behavior RoHS compliant August 2014 DocID026792 Rev 1 For further information contact your local STMicroelectronics sales office. 1/12 www.st.com BOARD_POWER_BLK MCU_3V3 MCU_3V3 FLASH_3V3 FLASH_3V3 BOARD_POWER USB_DISCONNECT USB_DISCONNECT USB_DM FLASH_C FLASH_DQ0 FLASH_DQ1 FLASH_DQ2 FLASH_DQ3 FLASH_nS DVDD VDDP VDDM HVP0 HVM0 HVPCW HVMCW FPGA FPGA_SPI_CCLK FPGA_SPI_MOSI FPGA_SPI_MISO1 FPGA_SPI_MISO2 FPGA_SPI_MISO3 FPGA_SPI_SEL MCU_FPGA_PROG MCU_FPGA_INIT_B MCU_FPGA_MODE1 FPGA_MCU_DONE MCU_FPGA_OSC_EN FPGA_MCU_AWAKE MCU_FPGA_SUSPEND +VFPGA_IO_3V3 +VFPGA_CORE_1V2 HVM0 HVP0 VDDM VDDP DVDD STM32_FLASH USB_DP USB_DP USB_DM MCU_FPGA_GPIO[0:7] HVPCW DocID026792 Rev 1 HVMCW MCU_FPGA_PROG MCU_FPGA_INIT_B MCU_FPGA_MODE1 FPGA_MCU_DONE MCU_FPGA_OSC_EN FPGA_MCU_AWAKE MCU_FPGA_SUSPEND MCU_FPGA_GPIO[0:7] CW CK DATAOUT14 DATAOUT15 DATAOUT12 DATAOUT13 DATAOUT10 DATAOUT11 DATAOUT8 DATAOUT9 DATAOUT6 DATAOUT7 DATAOUT2 DATAOUT3 DATAOUT0 DATAOUT1 THSD_EN DATAOUT[0:15] DATAOUT4 DATAOUT5 DATAOUT[0:15] +VFPGA_IO_3V3 FPGA_GPIO[0:7] STHV800 CW CK THSD_EN IN8_0 IN8_1 IN7_0 IN7_1 IN6_0 IN6_1 IN5_0 IN5_1 IN4_0 IN4_1 IN3_0 IN3_1 IN2_0 IN2_1 IN1_0 IN1_1 VDDM HVP DVDD VDDP HVP0 HVPCW DVDD STHV800_BLK VDDP VDDM FPGA_BLK HVMCW HVM0 HVP_CW 2/12 HVM_CW 1 HVM STM32_FLASH_BLK Schematic diagrams STEVAL-IME009V1 Schematic diagrams Figure 1. STEVAL-IME009V1 circuit schematic (1 of 9) GSPG01082014DI1330 +VFPGA_CORE_1V2 1 C11 33nF VIN U2 ID nc GND SHELL SHELL SHELL SHELL 1 2 4 3 2 1 D1 SM2T3V3A 5 J41 1 2 NOT ASSEMBLY C12 4u7 6.3V EXT_3V3 USB_3V3 C8 2.2uF 6.3V MMS228T nc ON_2a COM_1a ON_1a SOT23-5L VOUT LDS3985M33R USBDM USBDP 3 2 1 D3 USBUF02W6 D2 Grd 3.3V 4 5 USB_DISCONNECT USB_DM USB_DP DM USB_DISCONNECT U1 SOTT323-6L 6 DP D4 D1 ON_1b nc ON_2b COM_1b DVDD D26 RED USB ON Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 C13 4u7 6.3V 1 4 ST1S12xx EN Vin U3 SW FB/Vo +VFPGA_IO_3V3 FLASH_3V3 5 3 MCU L1 R124 56 D27 RED L1 Detail TDK (VLF4012AT-2R2M1R5) - RS (614-3147) C14 Detail TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 RED D28 FPGA R125 56 5 6 7 8 3.3V Power Management R90 56R C8 Details: DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA) Package 0603 C7 Details: Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K) Package 0402 USB_DISCONNECT USBDM USBDP J4 Details Phoenix Contact (Mfg Code MPT 0.5/2-2.54) RS (220-4260) C12 and C13 Detail TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND) Dimension 0603 - EIA 1608 3V3 3V3 Connector J4 USB_miniB RS (515-1995) Molex (54819-0572) C3 4.7nF 4 5 6 7 8 9 VBUS DM DP CN1 SW1 Details: SW1 RS 711-8329 KNITTER-SWITCH (MMS228T) EXT_3V3 FLASH_3V3 USB_3V3 C7 1uF USB_5V R1 1M DM DP 1 2 3 USB INH 3 BYPS 4 GND 2 2.2uH C14 10u 10V MCU_3V3 HVMCW HVM0 VDDM DVDD VDDP HVPCW HVP0 C9 1 2 3 4 J2 DVDD VDDP GND VDDM LV 1 2 3 J3 HVMCW HVM0 GND HVM GND_POWER C10 J3 Details: 22000n 100V RS (193-0570) Phoenix Contact (Mfg Code MKDS 1.5/3-5.08) HVMCW HVM0 C4 J2 Details RS 2X(193-0564) 22000n 16V Phoenix Contact (Mfg Code 16V MKDS 1.5/2-5.08) VDDM DVDD VDDP GND_POWER GND_POWER 16V HVPCW HVP0 GND HVP C2 J1 Details 22000n 100V RS (193-0570) 100V Phoenix Contact (Mfg Code MKDS 1.5/3-5.08) J1 +VFPGA_CORE_1V2 GND_POWER 0 R2 0 GND_SHIELD R123 C4, C5, C6 Details: Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M) Package 1210 - EIA 3225 C1, C2, C9, C10 Details: Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M) Package 6.5mm x 5.5 mm 100V 100V 22000n 100V 16V C6 100V C1 22000n 16V 22000n 16V C5 22000n 100V HVPCW 1 HVP0 2 3 STHV800 Power Management + HIGH VOLTAGE LOW POWER - HIGH VOLTAGE USB_5V GND DocID026792 Rev 1 2 STEVAL-IME009V1 Schematic diagrams Figure 2. STEVAL-IME009V1 circuit schematic (2 of 9) GSPG01082014DI1335 3/12 12 4/12 DocID026792 Rev 1 IO_0_L01N_VREF IO_0_L01P_HSWAPEN IO_0_L02N IO_0_L02P IO_0_L03N IO_0_L03P IO_0_L04N IO_0_L04P IO_0_L05N IO_0_L05P IO_0_L06N IO_0_L06P IO_0_L07N IO_0_L07P IO_0_L08N_VREF IO_0_L08P IO_0_L09N IO_0_L09P IO_0_L10N IO_0_L10P IO_0_L11N IO_0_L11P IO_0_L32N IO_0_L32P IO_0_L33N IO_0_L33P IO_0_L34N_GCLK18 IO_0_L34P_GCLK19 IO_0_L35N_GCLK16 IO_0_L35P_GCLK17 IO_0_L36N_GCLK14 IO_0_L36P_GCLK15 IO_0_L37N_GCLK12 IO_0_L37P_GCLK13 IO_0_L38N_VREF IO_0_L38P IO_0_L39N IO_0_L39P IO_0_L40N IO_0_L40P IO_0_L41N IO_0_L41P IO_0_L42N IO_0_L42P IO_0_L47N IO_0_L47P IO_0_L50N IO_0_L50P IO_0_L51N IO_0_L51P IO_0_L62N_VREF IO_0_L62P IO_0_L63N_SCP6 IO_0_L63P_SCP7 IO_0_L64N_SCP4 IO_0_L64P_SCP5 IO_0_L65N_SCP2 IO_0_L65P_SCP3 IO_0_L66N_SCP0 IO_0_L66P_SCP1 FPGA - Bank 0 XC6SLX16-2CSG324C U4A C4 D4 A2 B2 C6 D6 A3 B3 A4 B4 A5 C5 E6 F7 A6 B6 E8 E7 A7 C7 C8 D8 F8 G8 A8 B8 C9 D9 A9 B9 C11 D11 A10 C10 F9 G9 A11 B11 F10 G11 A12 B12 E11 F11 C12 D12 A13 C13 E12 F12 A14 B14 E13 F13 A15 C15 C14 D14 A16 B16 Diff. pair DATAOUT8 Diff. pair DATAOUT9 Diff. pair DATAOUT10 Diff. pair DATAOUT11 Diff. pair DATAOUT12 Diff. pair DATAOUT13 Diff. pair DATAOUT14 Diff. pair DATAOUT15 Diff. pair CW IDLE_STATE0 IDLE_STATE1 HI_Z THSD_EN HSWAPEN Diff. pair DATAOUT3 Diff. pair DATAOUT4 Diff. pair DATAOUT2 Diff. pair DATAOUT1 Diff. pair DATAOUT0 Diff. pair DATAOUT5 Diff. pair DATAOUT6 Diff. pair DATAOUT7 Diff. pair CK R120 10K 0402 DATAOUT[0:15] THSD_EN R121 10K 0402 CW DATAOUT[0:15] CK R122 10K 0402 NOT ASSEMBLY JUMPER J5 HSWAPEN 1 2 R3 10K 0402 +VFPGA_IO_3V3 +VFPGA_IO_3V3 C16 10uF 10V 0805 2 2 2 FPGA DISCONNECT NOT ASSEMBLY THESE JUMPERS J35 1 J36 1 J37 1 IDLE STATE C15 100n 0402 CK CW DATAOUT0 DATAOUT1 DATAOUT9 DATAOUT13 DATAOUT10 DATAOUT14 DATAOUT6 DATAOUT15 DATAOUT7 DATAOUT8 DATAOUT5 DATAOUT11 THSD_EN DATAOUT4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 STHV748 I/O CONNECTOR HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 NOT ASSEMBLY DATAOUT3 DATAOUT12 DATAOUT2 +VFPGA_IO_3V3 C17 10uF 10V 0805 Open J37 (default) to connect FPGA outputs Close J37 to disconnect outputs (High-Z) Configure J35 and J36 to setup outputs idle state as follows: 00 - (J35 and J36 open) --> High-Z (default) 01 - (J35 closed and J36 open) --> Clamp/HVR_SW 11 - (J35 and J36 closed) --> High-Z 10 - (J35 open and J36 closed) --> Clamp C18 100n 0402 C16 and C17 Details: TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 Jumpers J35, J36 and J37 are used to set dataout output state. +VFPGA_IO_3V3 J6 Open (default) to float I/O output during FPGA configuration. Set jumper 1:2 to enable I/O pullups during FPGA configuration. Jumper J5 is used to control I/O pullups during FPGA configuration. Schematic diagrams STEVAL-IME009V1 Figure 3. STEVAL-IME009V1 circuit schematic (3 of 9) GSPG01082014DI1340 DocID026792 Rev 1 F16 F15 C18 C17 G14 F14 D18 D17 G13 H12 E18 E16 K13 K12 F18 F17 H14 H13 H16 H15 G18 G16 K14 J13 L13 L12 K16 K15 L16 L15 H18 H17 J18 J16 K18 K17 L18 L17 M18 M16 N18 N17 P18 P17 N16 N15 T18 T17 U18 U17 N14 M14 M13 L14 P16 P15 FPGA_DOUT_BUSY FPGA_AWAKE FPGA_USER_IO_0 FPGA_USER_IO_1 FPGA_USER_IO_2 FPGA_USER_IO_3 FPGA_USER_IO_4 FPGA_USER_IO_5 FPGA_USER_IO_6 FPGA_USER_IO_7 FPGA_USER_IO_8 FPGA_USER_IO_9 FPGA_USER_IO_10 FPGA_USER_IO_11 FPGA_USER_IO_12 FPGA_USER_IO_13 FPGA_USER_IO_14 FPGA_USER_IO_15 CTRL_LED3 CTRL_LED2 FPGA_RESET STOP_PB CTRL_LED1 CTRL_LED0 SEL_PROG_PB FPGA_CLK_66MHZ START_PB FPGA_PMOD1_P2 FPGA_PMOD1_P1 FPGA_PMOD1_P4 FPGA_PMOD1_P3 FPGA_PMOD1_P8 FPGA_PMOD1_P7 FPGA_PMOD1_P10 FPGA_PMOD1_P9 FPGA_PMOD2_P2 FPGA_PMOD2_P1 FPGA_PMOD2_P4 FPGA_PMOD2_P3 FPGA_PMOD2_P8 FPGA_PMOD2_P7 FPGA_PMOD2_P10 FPGA_PMOD2_P9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 NOT ASSEMBLY FPGA_MCU_AWAKE TP1 TEST POINT HEADER 16X2 J7 FPGA USER I/O X1 GND OE ST OUT VCC FPGA_CLK_66MHZ 2 1 BACKUP OF U5 R126 10k 3 4 33R2 R7 2 1 8 7 3 FPGA_PMOD2_P7 FPGA_PMOD2_P9 FPGA_PMOD2_P1 FPGA_PMOD2_P3 C29 100nF J8 2 4 6 8 10 12 C27 C20 10nF FPGA_PMOD1_P8 FPGA_PMOD1_P10 C28 100nF +VFPGA_IO_3V3 R6 10K NM MCU_FPGA_OSC_EN FPGA_PMOD1_P2 FPGA_PMOD1_P4 10uF 10V 0805 5 4 6 C19 100nF J9 DX 2 4 6 8 10 12 NOT ASSEMBLY HEADER 6X2 1 3 5 7 9 11 PMOD2 C30 10uF 10V 0805 FPGA_PMOD2_P8 FPGA_PMOD2_P10 FPGA_PMOD2_P2 FPGA_PMOD2_P4 C31 10uF 10V 0805 C32 100nF +VFPGA_IO_3V3 C26, C27, C30 and C31 Detail HEADER 6X2 TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 SX NOT ASSEMBLY PMOD1 C26 10uF 10V 0805 1 3 5 7 9 11 +VFPGA_IO_3V3 FPGA_PMOD1_P7 FPGA_PMOD1_P9 FPGA_PMOD1_P1 FPGA_PMOD1_P3 C25 100nF +VFPGA_IO_3V3 GND GND PDN 66MHZ OSC DS1088LU-66 OUT n/c n/c VCC VCC U5 PERIPHERRAL MODULE (PMOD) Place R7 (1%) close to the clock source DS1088LU-66 device MCU_FPGA_OSC_EN Two right-angle, 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J8, J9) are interfaced to the FPGA, with each header providing 3.3 V power, ground, and eight I/O's. These headers may be utilized as general-purpose I/Os or may be used to interface to PMODs. J6 and J8 are placed in close proximity (0'9" -centers) on the PCB in order to support dual PMODs. IO_1_L01N_A24_VREF IO_1_L01P_A25 IO_1_L29N_A22_M1A14 IO_1_L29P_A23_M1A13 IO_1_L30N_A20_M1A11 IO_1_L30P_A21_M1RESET IO_1_L31N_A18_M1A12 IO_1_L31P_A19_M1CKE IO_1_L32N_A16_M1A9 IO_1_L32P_A17_M1A8 IO_1_L33N_A14_M1A4 IO_1_L33P_A15_M1A10 IO_1_L34N_A12_M1BA2 IO_1_L34P_A13_M1WE IO_1_L35N_A10_M1A2 IO_1_L35P_A11_M1A7 IO_1_L36N_A8_M1BA1 IO_1_L36P_A9_M1BA0 IO_1_L37N_A6_M1A1 IO_1_L37P_A7_M1A0 IO_1_L38N_A4_M1CLKN IO_1_L38P_A5_M1CLK IO_1_L39N_M1ODT IO_1_L39P_M1A3 IO_1_L40N_GCLK10_M1A6 IO_1_L40P_GCLK11_M1A5 IO_1_L41N_GCLK8_M1CASN IO_1_L41P_GCLK9_IRDY1_M1RASN IO_1_L42N_GCLK6_TRDY1_M1LDM IO_1_L42P_GCLK7_M1UDM IO_1_L43N_GCLK4_M1DQ5 IO_1_L43P_GCLK5_M1DQ4 IO_1_L44N_A2_M1DQ7 IO_1_L44P_A3_M1DQ6 IO_1_L45N_A0_M1LDQSN IO_1_L45P_A1_M1LDQS IO_1_L46N_FOE_B_M1DQ3 IO_1_L46P_FCS_B_M1DQ2 IO_1_L47N_LDC_M1DQ1 IO_1_L47P_FWE_B_M1DQ0 IO_1_L48N_M1DQ9 IO_1_L48P_HDC_M1DQ8 IO_1_L49N_M1DQ11 IO_1_L49P_M1DQ10 IO_1_L50N_M1UDQSN IO_1_L50P_M1UDQS IO_1_L51N_M1DQ13 IO_1_L51P_M1DQ12 IO_1_L52N_M1DQ15 IO_1_L52P_M1DQ14 IO_1_L53N_VREF IO_1_L53P IO_1_L61N IO_1_L61P IO_1_L74N_DOUT_BUSY IO_1_L74P_AWAKE FPGA - Bank 1 XC6SLX16-2CSG324C U4B 1 +VFPGA_IO_3V3 66MHZ EXTERNAL OSCILLATOR When using backup oscillator X1, R126 have to be unmounted and R6 must be placed. STOP SW PUSHBUTTON-DPST RED LED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 CTRL LED R10 56R 0402 R13 56R 0402 R12 56R 0402 R11 56R 0402 RED D5 GREEN D4 GREEN D3 GREEN C24 100nF FPGA_RESET FPGA RESET D2 R5 10K 0402 R9 10K 0402 ERROR ERROR signal IDLE IDLE state signal Near STOP button Near START button SW5 START SW PUSHBUTTON-DPST +VFPGA_IO_3V3 C22 100nF SW3 START_PB +VFPGA_IO_3V3 SW PUSHBUTTON-DPST GREEN LED Kingbright KP2012SURC RS: 466-3778 Farnell: 8529906 LED 0805 CTRL_LED3 CTRL_LED2 CTRL_LED1 CTRL_LED0 SW2, SW3, SW4, Details RS (378-6527) C23 100nF SW4 STOP_PB R8 10K 0402 PROGRAM SW PUSHBUTTON-DPST +VFPGA_IO_3V3 C21 100nF SW2 SEL_PROG_PB R4 10K 0402 +VFPGA_IO_3V3 PUSHBUTTONS STEVAL-IME009V1 Schematic diagrams Figure 4. STEVAL-IME009V1 circuit schematic (4 of 9) GSPG01082014DI1345 5/12 12 DocID026792 Rev 1 MCU_FPGA_GPIO0 MCU_FPGA_GPIO1 MCU_FPGA_GPIO2 MCU_FPGA_GPIO3 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 XC6SLX16-2CSG324C T15 R15 V16 U16 T13 R13 V15 U15 V14 T14 P12 N12 V13 U13 N11 M11 T11 R11 V12 T12 P11 N10 N9 M10 V11 U11 T10 R10 V10 U10 T8 R8 V9 T9 N8 M8 V8 U8 V7 U7 P8 N7 V6 T6 T7 R7 P7 N6 T5 R5 V5 U5 T3 R3 V4 T4 P6 N5 V3 U3 TP2 TEST POINT MCU_FPGA_GPIO[0:7] PROG_LED14 PROG_LED15 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 PROG_LED12 PROG_LED13 MCU_FPGA_GPIO2 MCU_FPGA_GPIO3 MCU_FPGA_GPIO0 MCU_FPGA_GPIO1 PROG_LED10 PROG_LED11 PROG_LED2 PROG_LED3 PROG_LED6 PROG_LED7 PROG_LED0 PROG_LED1 PROG_LED4 PROG_LED5 PROG_LED8 PROG_LED9 FPGA_SPI_SEL FPGA_INIT_B FPGA_MODE1 FPGA_SPI_MISO3 FPGA_SPI_MISO2 FPGA_SPI_MOSI FPGA_SPI_MISO1 FPGA_MODE0 CCLK MCU_FPGA_GPIO[0:7] IO_2_L01N_M0_CMPMISO IO_2_L01P_CCLK IO_2_L02N_CMPMOSI IO_2_L02P_CMPCLK IO_2_L03N_MOSI_CSI_B_MISO0 IO_2_L03P_D0_DIN_MISO_MISO1 IO_2_L05N IO_2_L05P IO_2_L12N_D2_MISO3 IO_2_L12P_D1_MISO2 IO_2_L13N_D10 IO_2_L13P_M1 IO_2_L14N_D12 IO_2_L14P_D11 IO_2_L15N IO_2_L15P IO_2_L16N_VREF IO_2_L16P IO_2_L19N IO_2_L19P IO_2_L20N IO_2_L20P IO_2_L22N IO_2_L22P IO_2_L23N IO_2_L23P IO_2_L29N_GCLK2 IO_2_L29P_GCLK3 IO_2_L30N_GCLK0_USERCCLK IO_2_L30P_GCLK1_D13 IO_2_L31N_GCLK30_D15 IO_2_L31P_GCLK31_D14 IO_2_L32N_GCLK28 IO_2_L32P_GCLK29 IO_2_L40N IO_2_L40P IO_2_L41N_VREF IO_2_L41P IO_2_L43N IO_2_L43P IO_2_L44N IO_2_L44P IO_2_L45N IO_2_L45P IO_2_L46N IO_2_L46P IO_2_L47N IO_2_L47P IO_2_L48N_RDWR_B_VREF IO_2_L48P_D7 IO_2_L49N_D4 IO_2_L49P_D3 IO_2_L62N_D6 IO_2_L62P_D5 IO_2_L63N IO_2_L63P IO_2_L64N_D9 IO_2_L64P_D8 IO_2_L65N_CSO_B IO_2_L65P_INIT_B FPGA - Bank 2 1 6/12 R21 2K43 0402 DNP R17 2K43 0402 R22 2K43 0402 MCU_FPGA_MODE1 MCU_FPGA_INIT_B R18 2K43 0402 DNP 1 2 3 4 5 6 7 8 9 10 Place D29 close to J10 EXT SPI FLASH CON10 R127 56 J10 GREEN C33 Details: TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 C34 100nF R40 NA 0402 R39 NA 0402 FPGA_SPI_CCLK FPGA_SPI_MISO1 FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO2 FPGA_SPI_MISO3 MCU_FPGA_PROG +VFPGA_IO_3V3 C33 10uF 10V 0805 33R2 0402 TO CORRECT D29 CCLK FPGA_SPI_MISO1 FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO2 FPGA_SPI_MISO3 R38 Place R38 close to the FPGA device SPI FLASH CTRL SIGNALS When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. Configuration mode selection: FPGA_MODE0 = Parallel (Low) or Serial (High) FPGA_MODE1 = Master (Low) or Slave (High) FPGA_INIT_B FPGA_MODE0 FPGA_MODE1 R16 10K 0402 +VFPGA_IO_3V3 FPGA CONFIGURATION SPI EXTERNAL PROGRAMMING HEADER U4C PROG_LED7 PROG_LED6 PROG_LED5 PROG_LED4 PROG_LED3 PROG_LED2 PROG_LED1 PROG_LED0 68R 0402 R33 68R 0402 R31 68R 0402 R29 68R 0402 R27 68R 0402 R25 68R 0402 R23 68R 0402 R19 68R 0402 R14 YELLOW D20 PROG 7 YELLOW D18 PROG 6 YELLOW D16 PROG 5 YELLOW D14 PROG 4 YELLOW D12 PROG 3 YELLOW D10 PROG 2 YELLOW D8 PROG 1 YELLOW D6 PROG 0 PROGRAM SELECTOR LEDS 68R 0402 R34 68R 0402 R32 68R 0402 R30 68R 0402 R28 68R 0402 R26 68R 0402 R24 68R 0402 R20 68R 0402 R15 Kingbright KP-3216SYC RS: 466-3942 LED 0805 PROG_LED15 PROG_LED14 PROG_LED13 PROG_LED12 PROG_LED11 PROG_LED10 PROG_LED9 PROG_LED8 YELLOW D21 PROG 15 YELLOW D19 PROG 14 YELLOW D17 PROG 13 YELLOW D15 PROG 12 YELLOW D13 PROG 11 YELLOW D11 PROG 10 YELLOW D9 PROG 9 YELLOW D7 PROG 8 Schematic diagrams STEVAL-IME009V1 Figure 5. STEVAL-IME009V1 circuit schematic (5 of 9) GSPG01082014DI1350 STEVAL-IME009V1 Schematic diagrams Figure 6. STEVAL-IME009V1 circuit schematic (6 of 9) U4D FPGA - Bank 3 IO_3_L01N_VREF IO_3_L01P IO_3_L02N IO_3_L02P IO_3_L31N_VREF IO_3_L31P IO_3_L32N_M3DQ15 IO_3_L32P_M3DQ14 IO_3_L33N_M3DQ13 IO_3_L33P_M3DQ12 IO_3_L34N_M3UDQSN IO_3_L34P_M3UDQS IO_3_L35N_M3DQ11 IO_3_L35P_M3DQ10 IO_3_L36N_M3DQ9 IO_3_L36P_M3DQ8 IO_3_L37N_M3DQ1 IO_3_L37P_M3DQ0 IO_3_L38N_M3DQ3 IO_3_L38P_M3DQ2 IO_3_L39N_M3LDQSN IO_3_L39P_M3LDQS IO_3_L40N_M3DQ7 IO_3_L40P_M3DQ6 IO_3_L41N_GCLK26_M3DQ5 IO_3_L41P_GCLK27_M3DQ4 IO_3_L42N_GCLK24_M3LDM IO_3_L42P_GCLK25_TRDY2_M3UDM IO_3_L43N_GCLK22_IRDY2_M3CASN IO_3_L43P_GCLK23_M3RASN IO_3_L44N_GCLK20_M3A6 IO_3_L44P_GCLK21_M3A5 IO_3_L45N_M3ODT IO_3_L45P_M3A3 IO_3_L46N_M3CLKN IO_3_L46P_M3CLK IO_3_L47N_M3A1 IO_3_L47P_M3A0 IO_3_L48N_M3BA1 IO_3_L48P_M3BA0 IO_3_L49N_M3A2 IO_3_L49P_M3A7 IO_3_L50N_M3BA2 IO_3_L50P_M3WE IO_3_L51N_M3A4 IO_3_L51P_M3A10 IO_3_L52N_M3A9 IO_3_L52P_M3A8 IO_3_L53N_M3A12 IO_3_L53P_M3CKE IO_3_L54N_M3A11 IO_3_L54P_M3RESET IO_3_L55N_M3A14 IO_3_L55P_M3A13 IO_3_L83N_VREF IO_3_L83P N3 N4 P3 P4 M5 L6 U1 U2 T1 T2 P1 P2 N1 N2 M1 M3 L1 L2 K1 K2 L3 L4 J1 J3 H1 H2 K3 K4 K5 L5 H3 H4 K6 L7 G1 G3 J6 J7 F1 F2 H5 H6 E1 E3 F3 F4 D1 D2 G6 H7 D3 E4 F5 F6 C1 C2 FPGA BANK 3 NOT USED XC6SLX16-2CSG324C GSPG01082014DI1355 DocID026792 Rev 1 7/12 12 1 2 3 4 CON14A Xilinx Parallel IV Connector 2.0mm 7x2 shrouded header SUSPEND SW PUSHBUTTON-DPST RS (378-6527) FPGA PROG RST1 1 2 3 JUMPER J13 R49 10K 0402 4 FPGA_PROG To be placed near U3 C73 100nF 74LX1G08CTR 4 A17 B18 D16 D15 FPGA_CMP_CS_B P13 V2 FPGA_PROG FPGA_SUSPEND R16 V17 FPGA_DONE FPGA_TCK FPGA_TMS FPGA_TDO FPGA_TDI Jumper J13 used to prevent FPGA from programming from configuration source. Set 1:2 to disable FPGA programming. Open (default) to enable FPGA programming. 2 1 U7 +VFPGA_IO_3V3 74V1G32CTR U6 10K 0402 R45 NOT ASSEMBLY R43 49R 0402 NOT ASSEMBLY R44 49R 0402 NOT ASSEMBLY R42 49R 0402 NOT ASSEMBLY R41 49R 0402 RESDIP4X1206 RN1 RESISTOR DIP 4 4-Resistor Array 3.2x1.6mm Not Assembly R50 10K 0402 10K 0402 R48 2 1 R46 10K 0402 FPGA PROG DISABLE 1 2 C62 100nF Header 3 J12 MCU_FPGA_PROG PROGRAM_B Jumper J12 1:2 to force FPGA into suspend mode. 2:3 (Default) to allow MCU to control FPGA suspend mode. MCU_FPGA_SUSPEND To be placed near U6 +VFPGA_IO_3V3 SUSPEND & CMPCS_B 1 3 5 7 9 11 13 J11 NOT ASSEMBLY 2 4 6 8 10 12 14 FPGA JTAG D22 STTH102A NOT ASSEMBLY 8 7 6 5 +VFPGA_IO_3V3 5 3 FPGA JTAG 5 CMPCS_B_2 PROGRAM_B_2 SUSPEND DONE_2 TCK TMS TDO TDI U4E XC6SLX16-2CSG324C FPGA - Power & Configuration DONE FPGA_MCU_DONE DONE FPGA_DONE R52 330 0402 +VFPGA_IO_3V3 Q1 2N7002 D23 GREEN R51 56R 0805 R47 0 FPGA BANK 3 NOT USED E2 G4 J2 J5 M4 R2 P9 R12 R6 U14 U4 U9 E17 G15 J14 J17 M15 R17 0.22uF 6.3V 0402 C68 C71 0.22uF 6.3V 0402 C72 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C69 +VFPGA_IO_3V3 0.22uF 6.3V 0402 4.7uF 6.3V 0603 0.22uF 6.3V 0402 100uF 6.3V 1206 C70 C67 4.7uF 6.3V 0603 C66 0.22uF 6.3V 0402 C64 C63 0.22uF 6.3V 0402 0.22uF 6.3V 0402 4.7uF 6.3V 0603 4.7uF 6.3V 0603 100uF 6.3V 1206 C65 C61 C60 C59 C58 +VFPGA_IO_3V3 C57 0.22uF 6.3V 0402 4.7uF 6.3V 0603 C56 C54 0.22uF 6.3V 0402 C53 C55 4.7uF 6.3V 0603 100uF 6.3V 1206 0.22uF 6.3V 0402 C52 C51 +VFPGA_IO_3V3 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C35, C40, C51, C58, C66 Details C36, C37, C38, C41, C42, C52, C53, C59, C60, C67, C68 Details Murata (GRM31CR60J107ME39L) - Digikey (490-4539-1-NDT )DK (C1608X5R0J475K) - Digikey (445-5178-2-ND) Dimension 0603 - EIA 1608 Dimension 1206 - EIA 3216 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 B10 B15 B5 D13 D7 E10 XC6SLX16-3CSG324C 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C50 4.7uF 6.3V 0603 C49 4.7uF 6.3V 0603 C48 C47 C46 100uF 6.3V 1206 0.22uF 6.3V 0402 4.7uF 6.3V 0603 4.7uF 6.3V 0603 C45 4.7uF 6.3V 0603 100uF 6.3V 1206 C42 +VFPGA_CORE_1V2 C41 C43 C40 +VFPGA_IO_3V3 C39 C38 C37 +VFPGA_IO_3V3 +VFPGA_CORE_1V2 C44 C36 C35 +VFPGA_IO_3V3 +VFPGA_CORE_1V2 B1 B17 E14 E5 E9 G10 J12 K7 M9 P10 P14 P5 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 M7 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DocID026792 Rev 1 A18 B13 C3 D10 D5 B7 C16 G17 G2 G5 H10 H8 J11 J15 J4 E15 G12 K8 L11 L9 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 K10 J9 A1 8/12 3 Schematic diagrams STEVAL-IME009V1 Figure 7. STEVAL-IME0089V1 circuit schematic (7 of 9) GSPG01082014DI1400 CW CK THSD_EN IN8_1 IN8_0 IN7_1 IN7_0 IN6_1 IN6_0 IN5_1 IN5_0 IN4_1 IN4_0 IN3_1 IN3_0 IN2_1 IN2_0 IN1_1 IN1_0 HVM HVM_CW XDCR_4 XDCR_8 CW CK THSD_EN IN8_1 IN8_0 IN7_1 IN7_0 IN6_1 IN6_0 IN5_1 IN5_0 IN4_1 IN4_0 IN3_1 IN3_0 IN2_1 IN2_0 IN1_1 IN1_0 HVM HVM_CW DVDD VDDP VDDM BNC BNC 1 Jch8 XDCR_7 1 Jch4 XDCR_3 1 BNC Jch7 D37 DFLS1200 D36 1 Jch1 1 Jch5 HVP HVM C77 CX1 D44 DFLS1200 100 R65 C91 220n C90 220n C86 C88 220n CX5 J28 B2S D46 DFLS1200 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LVOUT_5 C113 270p 100V 1206 J27 B2S XDCR_8 XDCR_7 XDCR_6 XDCR_5 HVM_CW HVM HVM HVM HVM HVM XDCR_4 XDCR_3 XDCR_2 XDCR_1 100 R63 C112 270p 100V 1206 J31 B2S J19 B2S C81 270p 100V 1206 U8 DFLS1200 D31 220n HVM_CW 220n 100V 0805 220n 100V 0805 CX4 CX3 270p 100V 1206 C116 100 R62 J32 B2S DFLS1200 D45 CX2 J21 B2S R56 100 HVM D32 DFLS1200 DFLS1200 D33 J20 B2S R55 100 220n 100V 0805 220n 100V 0805 220n 100V 0805 D34 DFLS1200 HVM J18 B2S 270p 100V 1206 R54 100 HVP D39 DFLS1200 100 R61 DFLS1200 D43 D40 DFLS1200 DFLS1200 D41 D38 DFLS1200 C111 270p 100V 1206 DFLS1200 D42 DFLS1200 HVP BNC 2 1 BNC Jch6 XDCR_5 HVM DFLS1200 XDCR_6 BNC 1 Jch2 XDCR_1 D35 1 BNC Jch3 BNC XDCR_2 R64 100 2 1 DVDD VDDP VDDM C84 270p 100V 1206 2 1 HVP HVP_CW 2 2 2 2 2 2 2 2 1 HVP HVP_CW 1 2 1 54 1 Jlch6 BNC LVOUT_6 Jlch5 BNC B2S J14 B2S J15 B2S J16 B2S J17 STHV800 Jlch7 BNC 1 1 1 1 2 2 2 2 J33 2 2 2 LVOUT_8 Jlch8 BNC B2S J30 B2S J29 1 46 B2S 2 B2S J34 LVOUT_7 1 1 1 1 1 C92 C76 C75 C74 1 Jlch2 BNC IN4_1 IN4_0 IN3_1 IN3_0 IN2_2 IN2_0 IN1_1 IN1_0 2 C118 20p 1206 C117 20p 1206 C115 20p 1206 IN8_1 IN8_0 IN7_1 IN7_0 IN6_1 IN6_0 IN5_1 IN5_0 VDDP 30 29 VDDM 31 32 33 34 35 36 37 HVP 38 CK J25 CON3 220n C101 220n C85 C95 220n CX7 CX9 220n C87 220n 100V 0805 220n 100V 0805 220n 100V 0805 220n C83 CK CX8 220n C89 R59 100k THSD R58 10k THSD_EN DVDD 220n 100V 0805 CX6 220n 100V 0805 1 2 3 CON3 J24 THSD J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401) C77, C80, C111, C112 Details DigiKey (490-1462-2-ND) Murata (GRM188R72A271KA01D) J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401) D1, D2, D3 ,D4, D5, D6, D7, D8 diode DFLS1200 rs-code 708-2324 TEST POINT TP3 HVP_CW LVOUT_4 LVOUT_3 1 Jlch3 BNC CX10 1 Jlch4 BNC LVOUT_2 LVOUT_1 2 C97 220n HVP DVDD 40 39 CW 41 42 STHV800 C114 20p 1206 THSD VDDP VDDM AGND HVP HVP HVP HVP HVP HVP_CW DGND DVDD CW CK 20p 1206 20p 1206 20p 1206 20p 1206 1 Jlch1 BNC 2 C80 1 2 1 2 2 1 1 2 56 GND_PWR GND_PWR 15 55 16 LVOUT_4 LVOUT_5 53 LVOUT_2 LVOUT_3 LVOUT_6 18 52 19 LVOUT_7 17 2 20 LVOUT_1 51 GND_PWR GND_PWR 50 21 IN5_1 22 LVOUT_8 2 IN4_1 49 IN4_0 48 23 IN5_0 2 47 IN3_1 IN6_0 24 IN3_0 IN6_1 45 IN2_1 IN7_0 43 IN1_0 44 IN2_0 25 IN1_1 IN7_1 26 IN8_0 27 IN8_1 28 2 1 2 3 270p 100V 1206 1 DocID026792 Rev 1 2 STEVAL-IME009V1 Schematic diagrams Figure 8. STEVAL-IME009V1 circuit schematic (8 of 9) GSPG01082014DI1405 9/12 12 DocID026792 Rev 1 FLASH_DQ0 FLASH_C FLASH_nS FLASH_DQ2 FLASH_DQ3 4k7 4k7 R69 R70 R71 R72 R73 R74 R75 R80 STM32_GPIO_8 STM32_GPIO_9 STM32_GPIO_10 STM32_GPIO_11 STM32_GPIO_12 STM32_GPIO_13 STM32_GPIO_14 R82 R83 R84 R85 R86 R88 R89 2 N25Q032xSC DQ0 DQ1 C nS nW/Vpp/DQ2 nHOLD/DQ3 56 R128 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A FPGA_GPIO0 FPGA_GPIO1 FPGA_GPIO2 FPGA_GPIO3 FPGA_GPIO4 FPGA_GPIO5 FPGA_GPIO6 FPGA_GPIO7 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A FPGA_MCU_AWAKE FPGA_MCU_DONE MCU_FPGA_OSC_EN MCU_FPGA_INIT_B MCU_FPGA_MODE1 MCU_FPGA_PROG MCU_FPGA_SUSPEND C122 100nF R66 4K7 MCU_3V3 FPGA_GPIO[0:7] C123 1uF 6.3V FPGA_MCU_AWAKE FPGA_MCU_DONE MCU_FPGA_OSC_EN MCU_FPGA_INIT_B MCU_FPGA_MODE1 MCU_FPGA_PROG MCU_FPGA_SUSPEND FPGA_GPIO[0:7] FLASH_DQ1 USB_DISCONNECT USB_DM USB_DP FLASH_DQ1 D30 RED INT SPI FLASH 9 44 20 7 3 4 2 JNTRST JTMS JTCK JTDO JTDI RESET# R76 10k R77 10k R78 10k MCU_3V3 STM32F103C8T6 VDDA BOOT0 PB2-BOOT1 NRST PC14-OSC32_IN PC15-OSC32_OUT PC13-Tamper-RTC PA0-WKUP PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 JTAG/SWD R67 4K7 VDDA BOOT0 BOOT1 RESET# FLASH_3V3 MCU_3V3 MCU 10 STM32_GPIO_0 11 STM32_GPIO_1 12 STM32_GPIO_2 13 STM32_GPIO_3 14 STM32_GPIO_4 15 STM32_GPIO_5 16 STM32_GPIO_6 17 STM32_GPIO_7 29 STM32_GPIO_8 30 STM32_GPIO_9 USB_DISCONNECT31 32 DM_STM32 33 DP_STM32 Use J38 to enable/disable power for SPI flash device. J38 must be open when using external spi flash device on connecto J10. Default value closed. FLASH DISABLE OPTIONAL FPGA CONFIGURATION SIGNALS STM32_GPIO_0 STM32_GPIO_1 STM32_GPIO_2 STM32_GPIO_3 STM32_GPIO_4 STM32_GPIO_5 STM32_GPIO_6 STM32_GPIO_7 5 6 1 3 7 U9 0R - N/A R132 2 1 J38 C123 Details: Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K) Package 0402 R131 C124 100nF 4k7 OPTIONAL FPGA I/O FLASH_DQ0 FLASH_C FLASH_nS FLASH_DQ2 FLASH_DQ3 R130 R129 FLASH_3V3 8 VCC VSS 4 R79 10k 2 R87 10k OSCIN OSCOUT 5 6 2 4 6 8 10 1 3 5 7 9 MCU JTAG SWD/JTAG J40 Male Connector 2x5 Pitch 1.27 mm SAMTEC FTSH-105-01-F-D-K MCU_3V3 USER_LED1 USER_LED2 STM32_GPIO_10 STM32_GPIO_11 STM32_GPIO_12 STM32_GPIO_13 STM32_GPIO_14 FLASH_DQ3 FLASH_DQ2 FLASH_nS FLASH_C FLASH_DQ1 FLASH_DQ0 JNTRST JTDO JTDI JTCK JTMS C120 100nF MCU_3V3 18 19 41 42 43 45 46 21 22 25 26 27 28 STM32F103 PD0 OSC_IN PD1 OSC_OUT PB0 PB1 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB4 JNTRST PB3 JTDO PA15 JTDI PA14 JTCK PA13 JTMS U10 40 39 38 37 34 C119 100nF Place near MCU C126 100nF FLASH_3V3 MCU_3V3 JP1 JUMPER 1 MCU_3V3 48 36 24 1 VDD_3 VDD_2 VDD_1 VBAT VSSA VSS_1 VSS_2 VSS_3 10/12 8 23 35 47 SPI FLASH C121 100nF RST2 MCU RESET Not Assembly RS (505-9186) C&K (Y78B22110FP) SW PUSHBUTTON-DPST OSCOUT 8MHz Y1 R68 56R USER_LED1 R81 56R USER_LED2 RED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 D25 FLASH READY RED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 D24 DOWNLOAD Murata (CSTCE8M00G55-R0) DigiKey (490-1195-1-ND) RS: 283-961 Farnell: 1615352 8MHZ OSC OSCIN OSCILLATOR C125 100nF RESET# R133 10K MCU_3V3 Schematic diagrams STEVAL-IME009V1 Figure 9. STEVAL-IME0089V1 circuit schematic (9 of 9) GSPG01082014DI1410 STEVAL-IME009V1 2 Revision history Revision history Table 1. Document revision history Date Revision 07-Aug-2014 1 Changes Initial release. DocID026792 Rev 1 11/12 12 STEVAL-IME009V1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 12/12 DocID026792 Rev 1