STEVAL-IME008V1 evaluation board based on the STHV749

AN4472
Application note
STEVAL-IME008V1 evaluation board based on the STHV749
transmission pulser
Introduction
The STEVAL-IME008V1 is an evaluation board designed around the STHV749
transmission pulser, a state-of-the-art solution for ultrasound imaging applications.
The system can drive four transducers as 4-channel transmitters and the output waveforms
can be displayed directly on an oscilloscope by connecting the scope probe to the relative
BNCs.
16 preset waveforms are available to test the HV pulser under different conditions.
Figure 1. Photo of STEVAL-IME008V1
Warning:
December 2014
Before applying any voltage supply to the STEVAL-IME008V1,
please read the instructions contained in this document
carefully.
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www.st.com
Contents
AN4472
Contents
1
Board features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Getting starting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
3.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1
Stored patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4.2
Pattern program 0 (3-level and 5-level output option) . . . . . . . . . . . . . . 11
3.4.3
Pattern Program 1 (SEL = 1, 5-level output option) . . . . . . . . . . . . . . . . 13
3.4.4
Pattern Program 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.5
Pattern Program 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.6
Pattern Program 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.7
Pattern Program 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.8
Pattern Program 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5
STHV749 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6
Operating supply conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3
MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4
SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5
Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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1
Board features
Board features
• Suitable for ultrasound imaging applications
• 4 monolithic channels, 5-level high voltage pulser
• Integrated T/R switch
• On-board equivalent piezoelectric load implemented by means of an R/C equivalent
network
• USB interface for uploading customized output waveforms
• 4 Mb serial Flash memory for storing customized waveforms
• Memory expansion connector for expanding the serial Flash size
• High voltage and low voltage connectors to power the STHV749
• 25 LEDs to check board status and proper operation
• Human machine interface to select, start and stop the stored output waveforms
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Getting starting
2
AN4472
Getting starting
The STEVAL-IME008V1 is shipped by STMicroelectronics, ready to use in Normal mode.
The user only needs to:
1.
plug the right power supply to the board (see Section 3.1)
2.
connect the BNC to the oscilloscope
3.
check that switch SW1 is set on the FPGA position
4.
check that the LED indicator DONE (D23) turns on
5.
check that FPGA is in the idle state (LED D4 is on)
6.
select the waveform with the Program button – the corresponding program LED (D6D21) turns on
7.
press the START button to run the selected program – the START LED (D2) turns on
8.
the selected waveform continuous until the STOP button is pressed, which lights the
relative LED (D3) – when the program ends, the FPGA returns to the idle state (LED
D4 is on)
9.
to run the same program again, restart from step 7; to run another program, restart
from step 6
For Programming mode information, please refer to UM1083.
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3
Hardware layout and configuration
Hardware layout and configuration
The hardware block diagram (Figure 2) illustrates the main connection between STHV749,
the FPGA, the STM32F103C8T6 and the SPI Flash memory. Figure 3 shows the
connectors, LEDs and features on the board.
Figure 2. Hardware block diagram
Figure 3. STEVAL-IME008V1 board layout
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Hardware layout and configuration
3.1
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Power supply
The low voltage block of the STEVAL-IME008V1 board is designed to be powered by:
• 3.3 V DC connected to J4 to supply FPGA and SPI Flash memory in Normal mode
• 5 V DC through the USB Mini B connector to supply the STM32 and the SPI Memory in
Programming mode
The power supply is configured by setting SW1 and J41 as described in Table 1.
Table 1. Power related Jumpers
Description
For normal operation mode, supplying power to FPGA and SPI
Flash memory.
Default Setting
LEFT (1)
SW1
For update operation mode, supplying power to STM32F103
and SPI Flash memory
RIGHT (1)
J41
FPGA and SPI Flash memory are powered by DVDD (J2).
Default setting: Not Mounted on PCB
1. Left and Right are conceived by looking the board as depicted in Figure 1.
Note:
Fitting the J41 jumper can create a voltage mismatch between J4 and J2 when either of
these is not 3.3 V.
LED D26, D27 and D28 show the power supply configuration as described in Table 1.
Table 2. Power supply LEDs
Color
Name
Description
D26
Red
USB ON
D27
Red
MCU
Programming mode, supplying power to
STM32F103 and SPI Flash memory
D28
Red
FPGA
Normal mode, supplying power to FPGA and SPI
Flash memory
The USB cable is plugged
The high voltage block of the STEVAL-IME008V1 is designed to be powered by (see
Table 23 for maximum rating):
• HVPCW: Continuous wave high voltage positive supply (J1 conn.)
• HVP0:TX0 High voltage positive supply (J1 conn.)
• HVP1:TX1 High voltage positive supply (J1 conn.)
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Hardware layout and configuration
• GND: Ground (J1 conn.)
• DVDD: Logic voltage, 3.3 V (J2 conn.)
• VDDP: Positive supply voltage 3.3 V (J2 conn.)
• VDDM: Negative supply voltage -3.3 V to 0 (J2 conn.)
• GND: Ground (J2 conn.)
• HVMCW: Continuous wave high voltage negative supply (J3 conn.)
• HVM0: TX0 high voltage negative supply (J3 conn.)
• HVM1:TX1 high voltage negative supply (J3 conn.)
• GND: Ground (J2 conn.)
Note:
Supply high voltage only in Normal mode and not in Programming mode
3.2
MCU
The STM32F103C8T6 is dedicated to updating the waveform and the FPGA bit stream on
the SPI Flash memory. It is pre-programmed as a DFU (device firmware upgrade) device,
and can upgrade internal and external FLASH memory.
The STM32F103 manages all the DFU operations such as product identifier, vendor
identifier and Firmware version authentication as well as the alternate setting number
(Target ID), used to upgrade the SPI Flash memory on the STEVAL-IME008V1 and render
upgrades more secure.
Note:
See AN3156 and UM0412 for further details about the upgrade through DFU.
3.3
SPI Flash memory
The STEVAL-IME008V1 hosts a Micron N25Q032 (U9) 32-Mbit (4 Mb x 8) serial Flash
memory bank with advanced write protection mechanisms. It can be accessed by a high
speed SPI-compatible bus and can function in XIP ("eXecution in Place") mode.
The N25Q032 also supports high-performance quad I/O instructions; these instructions
allow quadrupling of the transfer bandwidth for read and program operations used by the
FPGA.
If this memory is insufficient, the user can disable the on-board Flash by disconnecting J38
(see Table 4) and connect external Flash memory via the J10 connector (see Table 27).
When the external Flash is connected, LED D29 is lit (Table 3).
Table 3. SPI Flash memory LED
Color
Name
Description
D29
Green
EXT SPI-FLASH
The external SPI-Flash Module is connected
D30
Red
On-board SPI-FLASH
The on-board SPI-Flash is used
The Flash memory is configured by setting J38 as described in Table 4.
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Table 4. SPI Flash memory Jumper
Status
Description
Connected, supply power to the on-board SPI Flash memory (U9).
Default setting: Connected
Closed
J38
Not Connected, the on-board SPI Flash memory will not receive the power
supply.
Open
3.4
FPGA
The STEVAL-IME008V1 includes a Xilinx Spartan®-6 XC6SLX16 FPGA, which drives the
STHV749 pulser by generating a suitable sequence of digital control signals (called
programs). The board can store 16 individually selectable programs.
The main features of waveforms generated by a program are summarized in Table 5.
Table 5. Programmable waveforms main features
Feature
Min.
Default
Max.
Programmable Waveforms Number
1
6
16
Pulse Time Resolution
-
5 ns
-
40 ns
-
20.48 µs
40 ns
-
2621.44 µs
1
-
255
Pulse Pattern Duration (1)
Cycle Period (PRF)
(2)
Cycles Number
Infinite cycle
defined by the program
1. Time period of the pulse sequence pattern.
2. Time period of a pulse repetition cycle.
The data required to generate a program is stored in the SPI Flash memory. When the
program starts, data is downloaded from Flash memory and stored in FPGA internal RAM
blocks where it is manipulated to generate the high-speed STHV749 digital control signals.
SPI Flash also contains FPGA configuration data (bit stream) which is automatically loaded
during start-up and after the FPGA reset (SW5) is pressed.
The FPGA is configured by setting jumpers as described in Table 6.
Table 6. FPGA Jumper
Description
J5
J5 is used to control FPGA I/O pull ups during configuration.
It should be connected to enable I/O pull ups during FPGA configuration.
Default setting: Not connected.
Force FPGA into Suspend mode
J12
Allow STM32 to control FPGA Suspend mode
(default setting)
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Hardware layout and configuration
Table 6. FPGA Jumper (continued)
Description
J13
J13 is used to prevent FPGA programming from configuration source.
Connected: disable FPGA programming.
Not Connected: enable FPGA programming.
(default setting: not connected)
Configure J35 and J36 to setup outputs idle state as follows:
(default setting: Not connected)
J35 and
J36
High Z
J35 and J36
not
connected
Clamp / HVR_SW
J35
connected,
J36 not
connected
High Z
J35 and J36
connected
Clamp
J35 not
connected,
J36
connected
Configure J37 to connect FPGA outputs to STHV749
(default setting: Not connected)
J37
Connected: disconnect FPGA outputs (High Z)
Not Connected: connect FPGA outputs
Once the FPGA has been configured, the DONE LED (D23) turns on and the FPGA state
machine initiates the idle state entry sequence (LED D4 turns on).
Use the program button to select and generate the desired waveform (refer to
Section 3.4.1), which is highlighted by a corresponding LED (D6-D21 represent Program 0Program 15 respectively). The selection following the last installed program cycles back to
Program 0.
The START button activates the selected program and the START LED (D2) turns on. When
the program ends, the FPGA returns to the idle state (LED D4 is on). If a continuous wave
program is selected, the STOP button must be pressed to stop program execution; the
FPGA returns to the idle state and the STOP LED (D3) turns on. The LEDs associated with
FPGA operations are described in Table 7.
Table 7. FPGA LED
Color
Name
Description
D2
Green
START
A program is running after the START button SW5 is
pressed.
D3
Green
STOP
The STOP button SW4 has been pressed.
D4
Green
IDLE
The FPGA state machine is in the idle state.
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Table 7. FPGA LED (continued)
Color
Name
D5
Red
ERROR
D23
Green
DONE
D6-D21
Yellow
Description
An error has occurred during FPGA state machine
execution.
The FPGA has been successfully configured.
PROG 0-15 The corresponding program is selected
The FPGA state machine can be also controlled by an external digital device through the
FPGA USER I/O connector (J7); see Table 28 for the relative naming and pin-out
positioning.
To enable remote control of the board through an external device, the REMOTE_ENABLE
pin must be set high. The waveform program can be selected by setting the PROG<3:0>
port. If an uninstalled program is selected, the ERROR output signal goes high. Also, the
idle state can be selected through the IDLE_SEL<1:0> port. If remote control is enabled, the
Program, Start and Stop buttons are disabled.
A waveform program can be started by means of the REMOTE_START signal (active high)
and stopped by setting high the REMOTE_STOP signal. Either the FPGA reset (SW5) or
REMOTE_RESET signal can be used to reset the FPGA.
Some internal FPGA control signals can be monitored through the FPGA USER I/O
connector (regardless of whether remote control is enabled or disabled). Figure 4 and
Figure 5 show the expected behavior of these timing control signals.
Figure 4. FPGA timing control signals (beginning of cycle n)
Figure 5. FPGA timing control signals (ending of cycle n)
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3.4.1
Hardware layout and configuration
Stored patterns
The STEVAL-IME008V1 allows up to 16 patterns to be stored in the on-board Flash memory
in order to demonstrate the potential performance of the pulser outputs. Listed below are the
default patterns already stored in the Flash memory and available for immediate use.
3.4.2
Pattern program 0 (3-level and 5-level output option)
The first pattern stored in the SPI Flash is described in Table 8, where the output pulses are
in phase. The state sequence is given in Table 9.
The test conditions applied to generate the waveforms in Figure 6 and Figure 7 are:
– HVP0 = HVP1 = + 80 V
– HVM0 = HVM1 = - 80 V
– Load: 300 pF // 100 Ω
Table 8. Program 0
Mode
Frequency
[MHz]
Number of
pulses
Initial pulse
PRF
H-Bridge
XDCR_1
PW
5
10
positive
150 µs
TX0, TX0 & 1
XDCR_2
PW
5
10
negative
150 µs
TX0, TX0 & 1
XDCR_3
PW
5
10
positive
150 µs
TX1, TX0 & 1
XDCR_4
PW
5
10
negative
150 µs
TX1, TX0 & 1
Table 9. State sequence Program 0 [SEL=1 (5-level output), SEL=0 (3-level output)]
XDCR_1
XDCR_2
XDCR_3
XDCR_4
SEL
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
“1”
HVP0
100 ns
HVM0
100ns
HVP1
100 ns
HVP1
100 ns
“1”
HVM0
100 ns
HVP0
100ns
HVM1
100 ns
HVM1
100 ns
“1”
HVP0
100 ns
HVM0
100ns
HVP1
100 ns
HVP1
100 ns
“1”
HVM0
100 ns
HVP0
100ns
HVM1
100 ns
HVM1
100 ns
“1”
HVP0
100 ns
HVM0
100ns
HVP1
100 ns
HVP1
100 ns
“1”
HVM0
100 ns
HVP0
100ns
HVM1
100 ns
HVM1
100 ns
“1”
HVP0
100 ns
HVM0
100ns
HVP1
100 ns
HVP1
100 ns
“1”
HVM0
100 ns
HVP0
100ns
HVM1
100 ns
HVM1
100 ns
“1”
HVP0
100 ns
HVM0
100ns
HVP1
100 ns
HVP1
100 ns
“1”
HVM0
100 ns
HVP0
100ns
HVM1
100 ns
HVM1
100 ns
“1”
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
“1”
RX
145 µs
RX
145 µs
RX
145 µs
RX
145us
“1”
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
“0”
HVP
100 ns
HVM
100 ns
HVP
100 ns
HVP
100 ns
“0”
HVM
100 ns
HVP
100 ns
HVM
100 ns
HVM
100 ns
“0”
HVP
100 ns
HVM
100 ns
HVP
100 ns
HVP
100 ns
“0”
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Table 9. State sequence Program 0 [SEL=1 (5-level output), SEL=0 (3-level output)] (continued)
XDCR_1
XDCR_2
XDCR_3
XDCR_4
SEL
HVM
100 ns
HVP
100 ns
HVM
100 ns
HVM
100 ns
“0”
HVP
100 ns
HVM
100 ns
HVP
100 ns
HVP
100 ns
“0”
HVM
100 ns
HVP
100 ns
HVM
100 ns
HVM
100 ns
“0”
HVP
100 ns
HVM
100 ns
HVP
100 ns
HVP
100 ns
“0”
HVM
100 ns
HVP
100 ns
HVM
100 ns
HVM
100 ns
“0”
HVP
100 ns
HVM
100 ns
HVP
100 ns
HVP
100 ns
“0”
HVM
100 ns
HVP
100 ns
HVM
100 ns
HVM
100 ns
“0”
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
“0”
RX
145 µs
RX
145 µs
RX
145 µs
RX
145 µs
“0”
Figure 6. Acquisition by Program 0 with SEL=1, where C1, C2, C3 and C4 are XDCR_1,
XDCR_2, XDCR_3 and XDCR_4 respectively
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Hardware layout and configuration
Figure 7. Acquisition by Program 0 with SEL=0, where C1, C2, C3 and C4 are XDCR_1,
XDCR_2, XDCR_3 and XDCR_4 respectively
3.4.3
Pattern Program 1 (SEL = 1, 5-level output option)
The second pattern stored in the SPI Flash is described in Table 10, where the output
pulses are delayed by 10 ns each. The state sequence is given in Table 11.
The test conditions applied to generate the waveforms in Figure 8 and Figure 9 are:
– HVP0 = + 80 V
– HVP1 = + 40 V
– HVM0 = - 80 V
– HVM1 = - 40 V
– Load: 300 pF // 100 Ω
Table 10. Program “1”
mode
Frequency
[MHz]
Number of
pulses
Initial pulse
PRF
H-Bridge
XDCR_1
PW
5
10
positive
150 µs
TX0, TX1
XDCR_2
PW
5
10
positive
150 µs
TX0, TX1
XDCR_3
PW
5
10
positive
150 µs
TX1, TX1
XDCR_4
PW
5
10
positive
150 µs
TX1, TX1
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Table 11. State sequence Program “1”
XDCR_1
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XDCR_2
XDCR_3
XDCR_4
CLAMP
1 µs
CLAMP
1.01 µs
CLAMP
1.02 µs
CLAMP
1.03 µs
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVP0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
HVM0
100 ns
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
RX
145 µs
RX
145 µs
RX
145 µs
RX
145 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVP1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
HVM1
100 ns
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
RX
145 µs
RX
145 µs
RX
145 µs
RX
145 µs
CLAMP
1 µs
CLAMP
990 ns
CLAMP
980 ns
CLAMP
970 ns
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Hardware layout and configuration
Figure 8. Acquisition by Program "1" with H-Bridge TX0, where C1, C2, C3 and C4 are
XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively
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Figure 9. Acquisition by Program "1" with H-Bridge TX1, where C1, C2, C3 and C4 are
XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively
3.4.4
Pattern Program 2
The third pattern stored in the SPI Flash is described in Table 12, where the output pulses
are in phase. The state sequence is given in Table 13.
The test conditions applied to generate the waveforms in Figure 10 are:
– HVP_CW = + 10 V
– HVM_CW = - 10 V
– Load: 300 pF // 100 Ω
Table 12. Program 2, SEL = don't care
mode
Frequency [MHz]
Number of pulses
Initial pulse
H-Bridge
XDCR_1
CW
5
continuous wave
positive
HV-CW (0.5 A)
XDCR_2
CW
2.5
continuous wave
positive
HV-CW (0.5 A)
XDCR_3
CW
5
continuous wave
positive
HV-CW (0.5 A)
XDCR_4
CW
2.5
continuous wave
positive
HV-CW (0.5 A)
Table 13. State sequence Program 2
XDCR_1
XDCR_2
XDCR_3
XDCR_4
HVP_CW
100 ns
HVP_CW
100 ns
HVP_CW
200 ns
HVP_CW
200 ns
HVM_CW
100 ns
HVM_CW
100 ns
HVM_CW
200 ns
HVM_CW
200 ns
HVP_CW
100 ns
HVP_CW
100 ns
HVP_CW
200 ns
HVP_CW
200 ns
16/44
DocID026198 Rev 1
AN4472
Hardware layout and configuration
Table 13. State sequence Program 2 (continued)
XDCR_1
XDCR_2
XDCR_3
XDCR_4
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVP_CW(.5A)
100 ns
HVP_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
HVM_CW(.5A)
100 ns
HVM_CW(.5A)
200 ns
Figure 10. Acquisition by Program 2, where C1, C2, C3 and C4 are XDCR_1, XDCR_2,
XDCR_3 and XDCR_4 respectively
3.4.5
Pattern Program 3
The fourth pattern stored in the SPI Flash is described in Table 14, where the output pulses
are delayed by 10 ns each. The state sequence is given in Table 15.
The test conditions applied to generate the waveforms in Figure 11 and Figure 12 are:
– HVP_CW = + 10 V
– HVM_CW = - 10 V
– Load: 300 pF // 100 Ω
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Hardware layout and configuration
AN4472
Table 14. Program 3, SEL = don't care
mode
Frequency [MHz]
Number of pulses
Initial pulse
H-Bridge
XDCR_1
CW
5
continuous wave
positive
HV-CW (0.25 A)
XDCR_2
CW
5
continuous wave
positive
HV-CW (0.25 A)
XDCR_3
CW
5
continuous wave
positive
HV-CW (0.25 A)
XDCR_4
CW
5
continuous wave
positive
HV-CW (0.25 A)
Table 15. State sequence Program 3
XDCR_1
XDCR_2
XDCR_3
XDCR_4
HVP_CW (.25 A)
20 ns
HVP_CW (.25 A)
30ns
HVP_CW (.25 A)
40 ns
HVP_CW (.25 A)
50 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
80 ns
HVP_CW (.25 A)
70ns
HVP_CW (.25 A)
60 ns
HVP_CW (.25 A)
50 ns
Figure 11. Acquisition by Program 3, where C1, C2, C3 and C4 are XDCR_1, XDCR_2,
XDCR_3 and XDCR_4 respectively
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DocID026198 Rev 1
AN4472
Hardware layout and configuration
Figure 12. Acquisition by Program 3, where C1, C2, C3 and C4 are XDCR_1, XDCR_2,
XDCR_3 and XDCR_4 respectively
3.4.6
Pattern Program 4
The fifth pattern stored in the SPI Flash is described in Table 16, with the output pulses in
phase and SEL is 1 for the 5-level output option. The state sequence is given in Table 17.
The test conditions applied to generate the waveforms in Figure 13 and Figure 14 are:
– HVP0 = + 80 V
– HVP1 = + 40 V
– HVM0 = - 80 V
– HVM1 = - 40 V
– Load: 300 pF // 100 Ω
Table 16. Program 4, SEL=1
mode
Frequency
[MHz]
Number of
pulses
Initial pulse
PRF
H-Bridge
XDCR_1
PC
2.5
3
positive
150 µs
TX0, TX1
XDCR_2
PC
2.5
3
negative
150 µs
TX0, TX1
XDCR_3
PC
5
3
positive
150 µs
TX0, TX1
XDCR_4
PC
5
3
negative
150 µs
TX0, TX1
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Hardware layout and configuration
AN4472
Table 17. State sequence Program 4
XDCR_1
XDCR_2
XDCR_3
XDCR_4
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
HVP0
200 ns
HVM0
200 ns
HVP0
100 ns
HVM0
100 ns
HVM0
200 ns
HVP0
200 ns
HVM0
100 ns
HVP0
100 ns
HVP0
200 ns
HVM0
200 ns
HVP0
100 ns
HVM0
100 ns
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
RX
145.4 µs
RX
145.4 µs
RX
145.7 µs
RX
145.7 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
HVP1
200 ns
HVM1
200 ns
HVP1
100 ns
HVM1
100 ns
HVM1
200 ns
HVP1
200 ns
HVM1
100 ns
HVP1
100 ns
HVP1
200 ns
HVM1
200 ns
HVP1
100 ns
HVM1
100 ns
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
RX
145.4 µs
RX
145.4 µs
RX
145.7 µs
RX
145.7 µs
Figure 13. Acquisition by Program 4, H-Bridge TX0, where C1, C2, C3 and C4 are
XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively
20/44
DocID026198 Rev 1
AN4472
Hardware layout and configuration
Figure 14. Acquisition by Program 4, H-Bridge TX1, where C1, C2, C3 and C4 are
XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively
3.4.7
Pattern Program 5
The sixth pattern stored in the SPI Flash is described in Table 18, where the output pulses
are in phase and SEL is 1 for the 5-level output option. The state sequence is given in
Table 18.
The test conditions applied to generate the waveforms in Figure 15 and Figure 16 are:
– HVP0 = + 80 V
– HVP1 = + 40 V
– HVM0 = - 80 V
– HVM1 = - 40 V
– Load: 300 pF // 100 Ω
Table 18. Program 5, SEL=1
mode
Frequency
[MHz]
Number of
pulses
Initial pulse
PRF
H-Bridge
XDCR_1
PC
2.5
2
positive
300 µs
TX0
XDCR_2
PC
2.5
2
negative
300 µs
TX1
XDCR_3
PC
5
2
positive
300 µs
TX0
XDCR_4
PC
5
2
negative
300 µs
TX1
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Hardware layout and configuration
AN4472
Table 19. State sequence Program 5
XDCR_1
XDCR_2
XDCR_3
XDCR_4
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
HVP0
200 ns
HVM1
200 ns
HVP0
100 ns
HVM1
100 ns
HVM0
200 ns
HVP1
200 ns
HVM0
100 ns
HVP1
100 ns
CLAMP
6 µs
CLAMP
6 µs
CLAMP
6 µs
CLAMP
6 µs
HVM0
200 ns
HVP1
200 ns
HVM0
100 ns
HVP0
100 ns
HVP0
200 ns
HVM1
200 ns
HVP0
100 ns
HVM0
100 ns
CLAMP
291.2 µs
CLAMP
291.2 µs
CLAMP
291.6 µs
CLAMP
291.6 µs
Figure 15. Acquisition by Program 5, where C1, C2, C3 and C4 are XDCR_1, XDCR_2,
XDCR_3 and XDCR_4 respectively
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AN4472
Hardware layout and configuration
Figure 16. Acquisition by Program 5, zoom of Figure 15, where C1, C2, C3 and C4 are
XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively
3.4.8
Pattern Program 6
The seventh pattern stored in the SPI Flash is described in Table 20, with the output pulses
in phase and SEL is 0 for the 3-level output option. The state sequence is given in Table 21.
The test conditions applied to generate the waveforms in Figure 17 are:
– HVP0 = HVP1 = + 80 V
– HVP_CW = + 40 V
– HVM0 = HVM1 = - 80 V
– HVM_CW = - 40 V
– Load: 300 pF // 100 Ω
Table 20. Program 6, SEL=0
mode
Frequency
[MHz]
Number of pulses
Initial pulse
PRF
H-Bridge
XDCR_1
PW -CW
2.5
10 (PW) + 10 (CW)
positive
300 µs
TX0 & TX1, CW (0.5 A)
XDCR_2
PW -CW
2.5
10 (PW) + 10 (CW)
negative
300 µs
TX0 & TX1, CW (0.5 A)
XDCR_3
PW -CW
5
10 (PW) + 10 (CW)
positive
300 µs
TX0 & TX1, CW (0.5 A)
XDCR_4
PW -CW
5
10 (PW) + 10 (CW)
negative
300 µs
TX0 & TX1, CW (0.5 A)
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44
Hardware layout and configuration
AN4472
Table 21. State sequence Program 6
XDCR_1
XDCR_2
XDCR_3
XDCR_4
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
HVP
200 ns
HVM
200 ns
HVP
100 ns
HVP
100 ns
HVM
200 ns
HVP
200 ns
HVM
100 ns
HVM
100 ns
HVP
200 ns
HVM
200 ns
HVP
100 ns
HVP
100 ns
HVM
200 ns
HVP
200 ns
HVM
100 ns
HVM
100 ns
HVP
200 ns
HVM
200 ns
HVP
100 ns
HVP
100 ns
HVM
200 ns
HVP
200 ns
HVM
100 ns
HVM
100 ns
HVP
200 ns
HVM
200 ns
HVP
100 ns
HVP
100 ns
HVM
200 ns
HVP
200 ns
HVM
100 ns
HVM
100 ns
HVP
200 ns
HVM
200 ns
HVP
100 ns
HVP
100 ns
HVM
200 ns
HVP
200 ns
HVM
100 ns
HVM
100 ns
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP
2 µs
CLAMP_CW
2 µs
CLAMP_CW
2 µs
CLAMP_CW
2 µs
CLAMP_CW
2 µs
HVP_CW (.25 A)
200 ns
HVP_CW(.25A)
200 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
200 ns
HVM_CW(.25A)
200 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
200 ns
HVP_CW(.25A)
200 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
200 ns
HVM_CW(.25A)
200 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
200 ns
HVP_CW(.25A)
200 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
200 ns
HVM_CW(.25A)
200 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
200 ns
HVP_CW(.25A)
200 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
200 ns
HVM_CW(.25A)
200 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
HVP_CW (.25 A)
200 ns
HVP_CW(.25A)
200 ns
HVP_CW (.25 A)
100 ns
HVP_CW (.25 A)
100 ns
HVM_CW (.25 A)
200 ns
HVM_CW(.25A)
200 ns
HVM_CW (.25 A)
100 ns
HVM_CW (.25 A)
100 ns
CLAMP_CW
290 µs
CLAMP_CW
290 µs
CLAMP_CW
292 µs
CLAMP_CW
292 µs
24/44
DocID026198 Rev 1
AN4472
Hardware layout and configuration
Figure 17. Acquisition by Program 6, where C1, C2, C3 and C4 are XDCR_1, XDCR_2,
XDCR_3 and XDCR_4 respectively
Further customized pattern can be uploaded by user into remaining memory slots (thru .dfu
file - see UM1083.pdf), where it's tailored in base of the test necessities from final
application.
3.5
STHV749 stage
The STHV749 high-voltage, high-speed pulser generator features four independent
channels. It is designed for medical ultrasound applications, but can also be used for other
piezoelectric, capacitive, or MEMS transducers.
The device contains a controller logic interface circuit, level translators, MOSFET gate
drivers, noise blocking diodes, and high-power P-channel and N-channel MOSFETs as
output stages for each channel. There is also clamping-to-ground circuitry, anti-leakage, an
anti-memory effect block, a thermal sensor, and a HV receiver switch (HVR_SW) to ensure
strong decoupling during the transmission phase.
The STHV749 also includes self-biasing and thermal shutdown blocks (see block diagram in
Figure 18). Each channel can support up to five active output levels with two main half
bridges. It consists of three independently supplied output stages: two (TX0 and TX1) used
for pulsed wave (PW) and one for continuous wave (CW) operations. TX0 and TX1 are able
to provide up to ± 2 A peak output current each while, to reduce power dissipation and jitter
in continuous wave mode, the fully optimized CW output stage delivers up to ± 0.3 A. The
current capability for CW mode can also be set to 0.6 A.
The device can also be configured to operate as a 3-output-level, ± 4 A, 40 MHz pulser: this
mode can be selected via a dedicated input pin (SEL). In this configuration, the TX0 and
TX1 half bridges are paralleled in order to provide higher peak current and shorter pulse
waveforms, thus providing a higher output frequency.
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44
Hardware layout and configuration
Note:
AN4472
For further information, please refer to the STHV749 datasheet.
The STEVAL-IME008V1 allows the user to configure special pins on the STHV749
described below:
– THSD is a thermal flag. The output stage of the THSD pin is an NMOS channel opendrain, so the external pull-up resistance (R ≥ 10 kΩ) must be connected to the
positive low-voltage supply (see Figure 18). If the internal temperature exceeds
160 °C, the THSD goes down and puts all the channels into the HZ state. Thermal
protection can be disabled by externally forcing THSD to a positive low-voltage
supply.
– EXPOSED-PAD is internally connected to the substrate. It can be floating or
connected to a 100 V capacitance toward ground, in order to reduce noise during the
receiving phase.
The fixed configuration of the THSD pin is described in Table 22.
Table 22. STHV749 special pin configuration
Special pins on the PCB demo
Name
description
THSD
(pin 23)
Thermal shutdown flag pin
Status on board
Active (J24 closed between 1 and 2 forced to 3 V through R58 = 10 kΩ).
the user can also give control to FPGA
by shorting J24 between 2 and 3.
the user can monitor the THSD status
on TP3 (test point).
Input logic & high voltage
level shifter
Figure 18. STHV749 single channel block diagram
AM14715V1
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AN4472
Hardware layout and configuration
The STHV749 output waveforms can be displayed directly for each channel Ch 1/2/3/4
using an oscilloscope by connecting the scope probe to the JCh1, JCh2, JCh3, Jch4 BNC
connectors. The user can also select whether or not to connect the on-board equivalent
load, a 270 pF 100 V capacitor paralleled with a 100 Ω, 2 W resistor (through J20, J21, J28,
J31). A coaxial cable can also be used to easily connect the user transducer, and four low
voltage outputs are available to receive the echo traduced signal arriving from the piezoelement through HVR_SW (JLch1, JLch2, JLch3, JLch4).
This PCB design features layer separation, which ensures good filtering and an effective
decoupling between the low voltage inputs and the HV switching signals (XDCR, etc.),
together with the capacitance values. The user can download the gerber reference file for
this board from www.st.com.
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44
Hardware layout and configuration
3.6
AN4472
Operating supply conditions
Table 23. DC working supply conditions
Operating supply voltages
Symbol
Note:
Parameter
Min.
Typ.
Max.
Unit
VDDP
Positive supply voltage
2.7
3.3
3.6
V
VDDM
Negative supply voltage
-2.7
-3.3
-3.6
V
VDD
Positive logic voltage
1.6
3.3
3.6
V
HVP0
TX0 high voltage positive supply
95
V
HVP1
TX1 high voltage positive supply
95
V
HVM0
TX0 high voltage negative supply
-95
V
HVM1
TX1 high voltage negative supply
-95
V
HVP_CW
CW high voltage positive supply
HVM_CW
CW high voltage negative supply
95
-95
V
V
HVM0 / HVM1 /HVM_CW and HVP0 / HVP1 /HVP_CW are fully independent on the board.
Table 24. Current consumption in CW mode, @ 5 MHz, HV_CW = ± 5 V, no-load
Current consumption
Symbol
28/44
Parameter
Value
Unit
IVDDP
Positive supply current
2
mA
IVDDM
Negative supply current
7
mA
HVP_CW
CW high voltage positive supply current
15
mA
HVM_CW
CW high voltage negative supply current
12
mA
DocID026198 Rev 1
AN4472
Connectors
4
Connectors
4.1
Power supply
The STEVAL-IME008V1 board must be powered by the J4, J1, J2 and J3 connectors shown
in the following figures.
Figure 19. Power supply connector J4
Figure 20. Power supply connector J1
Figure 21. Power supply connector J2
Figure 22. Power supply connector J3
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44
Connectors
4.2
AN4472
Power-up sequence
The device is fully power-up/power-down free, meaning that there is no recommended
sequence to follow in order to power up/down the STHV749.
4.3
MCU
Figure 23. USB mini-B connector (CN1)
Table 25. USB mini B connector pin out
Pin number
Description
1
Vbus (power)
2
DM (STM32 PA11)
3
DP (STM32 PA12)
4
N.C.
5
Ground
Figure 24. SWD (J40)
Table 26. JTAG/SWD connector pin out
30/44
Pin number
Description
1
MCU_3V3
2
JTMS
3
GND
4
JTCK
5
GND
6
JTDO
7
GND
8
JTDI
9
GND
10
RESET#
DocID026198 Rev 1
AN4472
4.4
Connectors
SPI Flash memory
Figure 25. Memory expansion connector (J10)
Table 27. Memory expansion connector pin out
Note:
Pin number
Description
1
MCU_FPGA_PROG (not used)
2
SPI MISO3
3
SPI MISO2
4
SPI CS
5
SPI MOSI
6
SPI MISO
7
SPI CLK
8
GND
9
3.3 V
10
CHECK
This memory is mutually exclusive with the on-board Flash memory, remove J38 before
connecting the expansion memory via J10; the relative LED (D29) turns on.
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44
Connectors
4.5
AN4472
FPGA
FPGA USER I/O connector (J7) connector is used for debugging purpose; it allows users to
directly interface with FPGA I/Os.
Table 28. FPGA USER I/O connector pin out
Pin number
Description
Pin number
Description
Direction
1
GND
2
CW
OUTPUT
3
GND
4
TRIGGER_OUT
OUTPUT
5
GND
6
CLKOUT
OUTPUT
7
GND
8
CYCLE_END
OUTPUT
9
GND
10
THSD_EN
OUTPUT
11
GND
12
ERROR
OUTPUT
13
GND
14
PROG<0>
IN/OUT
15
GND
16
PROG<1>
IN/OUT
17
GND
18
PROG<2>
IN/OUT
19
GND
20
PROG<3>
IN/OUT
21
GND
22
IDLE_SEL<0>
IN/OUT
23
GND
24
IDLE_SEL<1>
IN/OUT
25
GND
26
REMOTE_ENABLE
INPUT
27
GND
28
REMOTE_START
INPUT
29
GND
30
REMOTE_STOP
INPUT
31
GND
32
REMOTE_RESET
INPUT
Table 29. FPGA PMOD connectors (J8) not mounted on the board
32/44
Pin number
Description
Pin number
Description
1
Not used
2
Not used
3
Not used
4
Not used
5
GND
6
3.3 V
7
Not used
8
Not used
9
Not used
10
Not used
11
GND
12
3.3 V
DocID026198 Rev 1
AN4472
Connectors
Table 30. FPGA PMOD connectors (J9) not mounted on the board
Pin number
Description
Pin number
Description
1
Not used
2
Not used
3
Not used
4
Not used
5
GND
6
3.3 V
7
Not used
8
Not used
9
Not used
10
Not used
11
GND
12
3.3 V
Two right-angle, 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J8, J9) are
interfaced to the FPGA, with each header providing 3.3 V power, ground and eight I/O's.
These headers may be used as general-purpose I/Os or to interface with the PMODs in
order to enable additional user customizations. J8 and J9 are placed in close proximity (0'9"
- centers) on the PCB in order to support dual PMODs.
Table 31. FPGA JTAG connectors (J11) not mounted on the board
Pin number
Description
Pin number
Description
1
GND
2
3.3 V
3
GND
4
TMS
5
GND
6
TCK
7
GND
8
TDO
9
GND
10
TDI
11
GND
12
Not used
13
GND
14
Not used
The STEVAL-IME008V1 evaluation board supports the serial peripheral interface (SPI
Flash) method for configuring the FPGA. The default configuration mode (determined by
pullup/pulldown resistors R17, R18, R21, and R22) is "Master Serial / SPI" mode, which
allows the FPGA to be configured by the SPI Flash device. Spartan-6 devices have a
dedicated four-wire JTAG port (always available to the FPGA regardless of the mode pin
settings), allowing the Boundary-scan configuration method.
Configuring the FPGA via Boundary-scan requires a JTAG download cable to be attached to
the 14-pin 2 mm spaced keyed header J11 (to be mounted) with a ribbon cable. Resistors
RN1, R41 to R44 and diode D22 must also be mounted.
Jumper J13 is used to prevent FPGA programming from the configuration source. It must be
open (default) to enable FPGA programming. The DONE LED (D23) on the board lights
when the FPGA has successfully been configured.
DocID026198 Rev 1
33/44
44
34/44
DocID026198 Rev 1
HVMCW
HVM1
HVM0
USB_DM
USB_DP
USB_DISCONNECT
MCU_3V3
MCU_3V3
FLASH_3V3
FLASH_3V3
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
CW
CK
DATAOUT13
DATAOUT12
DATAOUT10
DATAOUT11
DATAOUT8
DATAOUT9
DATAOUT6
DATAOUT7
DATAOUT2
DATAOUT3
DATAOUT0
DATAOUT1
THSD_EN
DATAOUT[0:15]
DATAOUT4
DATAOUT5
DATAOUT[0:15]
VDDM
VDDM
STHV749
CK
THSD_EN
SEL
CW
IN4_1
IN4_2
IN3_2
IN4_0
IN3_0
IN3_1
IN2_1
IN2_2
IN1_2
IN2_0
IN1_0
IN1_1
DVDD VDDP HVP0 HVP1 HVPCW
VDDP
BOARD_POWER
FPGA
FPGA_SPI_CCLK
FPGA_SPI_MOSI
FPGA_SPI_MISO1
FPGA_SPI_MISO2
FPGA_SPI_MISO3
FPGA_SPI_SEL
MCU_FPGA_PROG
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE
MCU_FPGA_SUSPEND
MCU_FPGA_GPIO[0:7]
STHV749_BLK
DVDD
HVP0 HVP1 HVPCW HVM0 HVM1 HVMCW
MCU_FPGA_GPIO[0:7]
DVDD VDDP VDDM
FLASH_C
FLASH_DQ0
FLASH_DQ1
FLASH_DQ2
FLASH_DQ3
FLASH_nS
MCU_FPGA_PROG
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE
MCU_FPGA_SUSPEND
FPGA_GPIO[0:7]
FPGA_BLK
HVM0
HVM0
HVP0
HVM1
HVM1
HVP_CW
HVM_CW
HVMCW
5
BOARD_POWER_BLK
STM32_FLASH
STM32_FLASH_BLK
Schematic diagrams
AN4472
Schematic diagrams
Figure 26. STEVAL_IME008V1- Part 1
HVP1
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
HVPCW
HVP1
HVP0
VDDM
VDDP
DVDD
USB_DP
USB_DISCONNECT
USB_DM
GSPG3009141005SG
1
4
DocID026198 Rev 1
1
2
D1
SM2T3V3A
ON_1a
J41
2
1
NOT ASSEMBLY
C12
4u7
6.3V
EXT_3V3
MMS228T
nc
ON_2a
COM_1a
C8
2.2uF 6.3V
USB_3V3
J4 Details
Phoenix Contact (Mfg Code MPT 0.5/2-2.54)
RS (220-4260)
C12 and C13 Detail
TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND)
Dimension 0603 - EIA 1608
3V3
3V3 Connector
J4
SW1 Details:
SW1
RS 711-8329
KNITTER-SWITCH (MMS228T)
2
4
3
2
1
5
SOT23-5L
VOUT
LDS3985M33R
GND
EXT_3V3
BYPS
C11
33nF
ID nc
GND
SHELL
SHELL
SHELL
SHELL
VBUS
DM
DP
CN1
C3
4.7nF
RS (515-1995)
Molex (54819-0572)
4
5
6
7
8
9
INH
FLASH_3V3
VIN
U2
DM
DP
1
2
3
USB
3
USB_3V3
C7
1uF
USB_5V
R1
1M
USB_5V
USB_miniB
3
2
1
D4
SOTT323-6L
D3
USBUF02W6
D2
Grd 3.3V
D1
U1
4
5
6
USB_DISCONNECT
USB_DM
USB_DP
DM
USB_DISCONNECT
DP
ON_1b
nc
ON_2b
COM_1b
DVDD
D26
RED
USB ON
C13
4u7
6.3V
1
4
ST1S12xx
EN
Vin
U3
SW
FB/Vo
+VFPGA_IO_3V3
FLASH_3V3
5
3
L1
VDDM
DVDD
VDDP
2.2uH
C14
10u
10V
MCU_3V3
HVMCW
HVM1
HVM0
HVPCW
HVP1
HVP0
R124
56 D27
RED
C14 Detail
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
L1 Detail
TDK (VLF4012AT-2R2M1R5) - RS (614-3147)
RED
D28
FPGA
R125 56
5
6
7
8
MCU
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
3.3V Power Management
R90 56R
C8 Details:
DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA)
Package 0603
C7 Details:
Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)
Package 0402
USB_DISCONNECT
USBDM
USBDP
USBDM
USBDP
C6
100V
100V
100V
J1
100V
22000n 100V
C10
HVMCW
HVM1
HVM0
1
2
3
4
1
2
3
4
GND_POWER
0
R2
DVDD
VDDP
GND
VDDM
J3
HVMCW
HVM1
HVM0
GND
HVM
J3 Details
RS 2X(193-0564)
Phoenix Contact
(Mfg Code
MKDS 1.5/2-5.08)
C4, C5, C6 Details:
Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M)
Package 1210 - EIA 3225
+VFPGA_CORE_1V2
HVPCW
HVP1
HVP0
GND
HVP
J2 Details
RS 2X(193-0564)
22000n 16V Phoenix Contact
(Mfg Code
16V
MKDS 1.5/2-5.08)
C4
VDDM
DVDD
VDDP
0
GND_SHIELD
R123
GND_POWER
C1, C2, C9, C10, C15, C16 Details:
Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M)
Package 6.5mm x 5.5 mm
C9
C79
1
2
3
4
J1 Details
RS 2X(193-0564)
Phoenix Contact
(Mfg Code
MKDS 1.5/2-5.08)
GND_POWER
J2 LV
GND_POWER
16V
22000n 100V 22000n 100V
16V
100V
C2
22000n 100V
22000n 16V 22000n 16V
C5
100V
22000n 100V 22000n 100V
C1
C78
HVPCW
HVP1
HVP0
STHV800 Power Management
LOW POWER
GND
+ HIGH VOLTAGE
2
AN4472
Schematic diagrams
Figure 27. STEVAL_IME008V1- Part 2
GSPG3009141035SG
- HIGH VOLTAGE
35/44
44
GSPG3009141045SG
36/44
DocID026198 Rev 1
IO_0_L01N_VREF
IO_0_L01P_HSWAPEN
IO_0_L02N
IO_0_L02P
IO_0_L03N
IO_0_L03P
IO_0_L04N
IO_0_L04P
IO_0_L05N
IO_0_L05P
IO_0_L06N
IO_0_L06P
IO_0_L07N
IO_0_L07P
IO_0_L08N_VREF
IO_0_L08P
IO_0_L09N
IO_0_L09P
IO_0_L10N
IO_0_L10P
IO_0_L11N
IO_0_L11P
IO_0_L32N
IO_0_L32P
IO_0_L33N
IO_0_L33P
IO_0_L34N_GCLK18
IO_0_L34P_GCLK19
IO_0_L35N_GCLK16
IO_0_L35P_GCLK17
IO_0_L36N_GCLK14
IO_0_L36P_GCLK15
IO_0_L37N_GCLK12
IO_0_L37P_GCLK13
IO_0_L38N_VREF
IO_0_L38P
IO_0_L39N
IO_0_L39P
IO_0_L40N
IO_0_L40P
IO_0_L41N
IO_0_L41P
IO_0_L42N
IO_0_L42P
IO_0_L47N
IO_0_L47P
IO_0_L50N
IO_0_L50P
IO_0_L51N
IO_0_L51P
IO_0_L62N_VREF
IO_0_L62P
IO_0_L63N_SCP6
IO_0_L63P_SCP7
IO_0_L64N_SCP4
IO_0_L64P_SCP5
IO_0_L65N_SCP2
IO_0_L65P_SCP3
IO_0_L66N_SCP0
IO_0_L66P_SCP1
FPGA - Bank 0
XC6SLX16-2CSG324C
U4A
C4
D4
A2
B2
C6
D6
A3
B3
A4
B4
A5
C5
E6
F7
A6
B6
E8
E7
A7
C7
C8
D8
F8
G8
A8
B8
C9
D9
A9
B9
C11
D11
A10
C10
F9
G9
A11
B11
F10
G11
A12
B12
E11
F11
C12
D12
A13
C13
E12
F12
A14
B14
E13
F13
A15
C15
C14
D14
A16
B16
Diff. pair
DATAOUT8
Diff. pair
DATAOUT9
Diff. pair
DATAOUT10
Diff. pair
DATAOUT11
Diff. pair
DATAOUT12
Diff. pair
DATAOUT13
Diff. pair
DATAOUT14
Diff. pair
DATAOUT15
Diff. pair
CW
IDLE_STATE0
IDLE_STATE1
HI_Z
THSD_EN
HSWAPEN
Diff. pair
DATAOUT3
Diff. pair
DATAOUT4
Diff. pair
DATAOUT2
Diff. pair
DATAOUT1
Diff. pair
DATAOUT0
Diff. pair
DATAOUT5
Diff. pair
DATAOUT6
Diff. pair
DATAOUT7
Diff. pair
CK
R120
10K 0402
DATAOUT[0:15]
THSD_EN
R121
10K 0402
CW
DATAOUT[0:15]
CK
R122
10K 0402
NOT ASSEMBLY
JUMPER
J5
HSWAPEN
1
2
R3
10K 0402
+VFPGA_IO_3V3
+VFPGA_IO_3V3
2
2
2
FPGA DISCONNECT
NOT ASSEMBLY
THESE JUMPERS
J35 1
J36 1
J37 1
C17
10uF 10V 0805
C18
100n 0402
Open J37 (default) to connect FPGA outputs
Close J37 to disconnect outputs (High-Z)
Configure J35 and J36 to setup outputs idle state as follows:
00 - (J35 and J36 open) --> High-Z (default)
01 - (J35 closed and J36 open) --> Clamp/HVR_SW
11 - (J35 and J36 closed) --> High-Z
10 - (J35 open and J36 closed) --> Clamp
Jumpers J35, J36 and J37 are used to set dataout output state.
C16 and C17 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
C16
10uF 10V 0805
IDLE STATE
C15
100n 0402
+VFPGA_IO_3V3
Open (default) to float I/O output during FPGA conf iguration.
Set jumper 1:2 to enable I/O pullups during FPGA configuration.
Jumper J5 is used to control I/O pullups during FPG A configuration.
Schematic diagrams
AN4472
Figure 28. STEVAL_IME008V1- Part 3
FPGA - Bank 1
DocID026198 Rev 1
XC6SLX16-2CSG324C
IO_1_L01N_A24_VREF
IO_1_L01P_A25
IO_1_L29N_A22_M1A14
IO_1_L29P_A23_M1A13
IO_1_L30N_A20_M1A11
IO_1_L30P_A21_M1RESET
IO_1_L31N_A18_M1A12
IO_1_L31P_A19_M1CKE
IO_1_L32N_A16_M1A9
IO_1_L32P_A17_M1A8
IO_1_L33N_A14_M1A4
IO_1_L33P_A15_M1A10
IO_1_L34N_A12_M1BA2
IO_1_L34P_A13_M1WE
IO_1_L35N_A10_M1A2
IO_1_L35P_A11_M1A7
IO_1_L36N_A8_M1BA1
IO_1_L36P_A9_M1BA0
IO_1_L37N_A6_M1A1
IO_1_L37P_A7_M1A0
IO_1_L38N_A4_M1CLKN
IO_1_L38P_A5_M1CLK
IO_1_L39N_M1ODT
IO_1_L39P_M1A3
IO_1_L40N_GCLK10_M1A6
IO_1_L40P_GCLK11_M1A5
IO_1_L41N_GCLK8_M1CASN
IO_1_L41P_GCLK9_IRDY1_M1RASN
IO_1_L42N_GCLK6_TRDY1_M1LDM
IO_1_L42P_GCLK7_M1UDM
IO_1_L43N_GCLK4_M1DQ5
IO_1_L43P_GCLK5_M1DQ4
IO_1_L44N_A2_M1DQ7
IO_1_L44P_A3_M1DQ6
IO_1_L45N_A0_M1LDQSN
IO_1_L45P_A1_M1LDQS
IO_1_L46N_FOE_B_M1DQ3
IO_1_L46P_FCS_B_M1DQ2
IO_1_L47N_LDC_M1DQ1
IO_1_L47P_FWE_B_M1DQ0
IO_1_L48N_M1DQ9
IO_1_L48P_HDC_M1DQ8
IO_1_L49N_M1DQ11
IO_1_L49P_M1DQ10
IO_1_L50N_M1UDQSN
IO_1_L50P_M1UDQS
IO_1_L51N_M1DQ13
IO_1_L51P_M1DQ12
IO_1_L52N_M1DQ15
IO_1_L52P_M1DQ14
IO_1_L53N_VREF
IO_1_L53P
IO_1_L61N
IO_1_L61P
IO_1_L74N_DOUT_BUSY
IO_1_L74P_AWAKE
U4B
FPGA_DOUT_BUSY
FPGA_AWAKE
FPGA_USER_IO_0
FPGA_USER_IO_1
FPGA_USER_IO_2
FPGA_USER_IO_3
FPGA_USER_IO_4
FPGA_USER_IO_5
FPGA_USER_IO_6
FPGA_USER_IO_7
FPGA_USER_IO_8
FPGA_USER_IO_9
FPGA_USER_IO_10
FPGA_USER_IO_11
FPGA_USER_IO_12
FPGA_USER_IO_13
FPGA_USER_IO_14
FPGA_USER_IO_15
CTRL_LED3
CTRL_LED2
FPGA_RESET
STOP_PB
CTRL_LED1
CTRL_LED0
SEL_PROG_PB
FPGA_CLK_66MHZ
START_PB
FPGA_PMOD1_P2
FPGA_PMOD1_P1
FPGA_PMOD1_P4
FPGA_PMOD1_P3
FPGA_PMOD1_P8
FPGA_PMOD1_P7
FPGA_PMOD1_P10
FPGA_PMOD1_P9
FPGA_PMOD2_P2
FPGA_PMOD2_P1
FPGA_PMOD2_P4
FPGA_PMOD2_P3
FPGA_PMOD2_P8
FPGA_PMOD2_P7
FPGA_PMOD2_P10
FPGA_PMOD2_P9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
FPGA_MCU_AWAKE
TP1
TEST POINT
HEADER 16X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
NOT ASSEMBLY
FPGA USER I/O
J7
X1
GND
OE ST
OUT
VCC
FPGA_CLK_66MHZ
2
1
BACKUP OF U5
R126
10k
3
4
33R2
R7
1
8
7
3
2
FPGA_PMOD2_P7
FPGA_PMOD2_P9
FPGA_PMOD2_P1
FPGA_PMOD2_P3
C29
100nF
J8
2
4
6
8
10
12
C27
C20
10nF
FPGA_PMOD1_P8
FPGA_PMOD1_P10
C28
100nF
+VFPGA_IO_3V3
R6
10K NM
MCU_FPGA_OSC_EN
FPGA_PMOD1_P2
FPGA_PMOD1_P4
10uF 10V 0805
5
4
6
C19
100nF
J9
DX
2
4
6
8
10
12
NOT ASSEMBLY
HEADER 6X2
1
3
5
7
9
11
PMOD2
C30
10uF 10V 0805
FPGA_PMOD2_P8
FPGA_PMOD2_P10
FPGA_PMOD2_P2
FPGA_PMOD2_P4
C31
10uF 10V 0805
C32
100nF
+VFPGA_IO_3V3
C26, C27, C30 and C31 Detail
HEADER 6X2 TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
SX
NOT ASSEMBLY
PMOD1
C26
10uF 10V 0805
1
3
5
7
9
11
+VFPGA_IO_3V3
FPGA_PMOD1_P7
FPGA_PMOD1_P9
FPGA_PMOD1_P1
FPGA_PMOD1_P3
C25
100nF
+VFPGA_IO_3V3
GND
GND
PDN
66MHZ OSC
DS1088LU-66
OUT
n/c
n/c
VCC
VCC
U5
PERIPHERRAL MODULE (PMOD)
Place R7 (1%) close to the clock
source DS1088LU-66 device
MCU_FPGA_OSC_EN
Two right-angle, 12-pin (2 x 6 female) Peripheral
Module (PMOD) headers (J8, J9) are interfaced to the
FPGA, with each header providing 3.3 V power, ground,
and eight I/O's. These headers may be utilized as
general-purpose I/Os or may be used to interface to
PMODs. J6 and J8 are placed in close proximity (0'9 "
-centers) on the PCB in order to support dual PMODs.
F16
F15
C18
C17
G14
F14
D18
D17
G13
H12
E18
E16
K13
K12
F18
F17
H14
H13
H16
H15
G18
G16
K14
J13
L13
L12
K16
K15
L16
L15
H18
H17
J18
J16
K18
K17
L18
L17
M18
M16
N18
N17
P18
P17
N16
N15
T18
T17
U18
U17
N14
M14
M13
L14
P16
P15
1
+VFPGA_IO_3V3
66MHZ EXTERNAL OSCILLATOR
When using backup oscillator X1,
R126 have to be mounted and R6
must be unplaced.
STOP
SW PUSHBUTTON-DPST
R8
10K 0402
PROGRAM
RED LED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
CTRL LED
56R 0402
R13
56R 0402
R12
56R 0402
R11
56R 0402
R10
RED
D5
GREEN
D4
GREEN
D3
GREEN
D2
C24
100nF
FPGA_RESET
FPGA RESET
R9
10K 0402
ERROR
ERROR signal
IDLE
IDLE state signal
Near STOP button
Near START button
SW5
SW PUSHBUTTON-DPST
+VFPGA_IO_3V3
START
SW PUSHBUTTON-DPST
R5
10K 0402
+VFPGA_IO_3V3
C22
100nF SW3
START_PB
GREEN LED
Kingbright KP2012SURC
RS: 466-3778
Farnell: 8529906
LED 0805
CTRL_LED3
CTRL_LED2
CTRL_LED1
CTRL_LED0
SW2, SW3, SW4, Details RS (378-6527)
C23
100nF SW4
STOP_PB
R4
10K 0402
SW PUSHBUTTON-DPST
+VFPGA_IO_3V3
C21
100nF SW2
SEL_PROG_PB
+VFPGA_IO_3V3
PUSHBUTTONS
AN4472
Schematic diagrams
Figure 29. STEVAL_IME008V1- Part 4
GSPG3009141145SG
37/44
44
DocID026198 Rev 1
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
T15
R15
V16
U16
T13
R13
V15
U15
V14
T14
P12
N12
V13
U13
N11
M11
T11
R11
V12
T12
P11
N10
N9
M10
V11
U11
T10
R10
V10
U10
T8
R8
V9
T9
N8
M8
V8
U8
V7
U7
P8
N7
V6
T6
T7
R7
P7
N6
T5
R5
V5
U5
T3
R3
V4
T4
P6
N5
V3
U3
TP2
TEST POINT
MCU_FPGA_GPIO[0:7]
PROG_LED14
PROG_LED15
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
PROG_LED12
PROG_LED13
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
PROG_LED10
PROG_LED11
PROG_LED2
PROG_LED3
PROG_LED6
PROG_LED7
PROG_LED0
PROG_LED1
PROG_LED4
PROG_LED5
PROG_LED8
PROG_LED9
FPGA_SPI_SEL
FPGA_INIT_B
FPGA_MODE1
FPGA_SPI_MISO3
FPGA_SPI_MISO2
FPGA_SPI_MOSI
FPGA_SPI_MISO1
FPGA_MODE0
CCLK
MCU_FPGA_GPIO[0:7]
IO_2_L01N_M0_CMPMISO
IO_2_L01P_CCLK
IO_2_L02N_CMPMOSI
IO_2_L02P_CMPCLK
IO_2_L03N_MOSI_CSI_B_MISO0
IO_2_L03P_D0_DIN_MISO_MISO1
IO_2_L05N
IO_2_L05P
IO_2_L12N_D2_MISO3
IO_2_L12P_D1_MISO2
IO_2_L13N_D10
IO_2_L13P_M1
IO_2_L14N_D12
IO_2_L14P_D11
IO_2_L15N
IO_2_L15P
IO_2_L16N_VREF
IO_2_L16P
IO_2_L19N
IO_2_L19P
IO_2_L20N
IO_2_L20P
IO_2_L22N
IO_2_L22P
IO_2_L23N
IO_2_L23P
IO_2_L29N_GCLK2
IO_2_L29P_GCLK3
IO_2_L30N_GCLK0_USERCCLK
IO_2_L30P_GCLK1_D13
IO_2_L31N_GCLK30_D15
IO_2_L31P_GCLK31_D14
IO_2_L32N_GCLK28
IO_2_L32P_GCLK29
IO_2_L40N
IO_2_L40P
IO_2_L41N_VREF
IO_2_L41P
IO_2_L43N
IO_2_L43P
IO_2_L44N
IO_2_L44P
IO_2_L45N
IO_2_L45P
IO_2_L46N
IO_2_L46P
IO_2_L47N
IO_2_L47P
IO_2_L48N_RDWR_B_VREF
IO_2_L48P_D7
IO_2_L49N_D4
IO_2_L49P_D3
IO_2_L62N_D6
IO_2_L62P_D5
IO_2_L63N
IO_2_L63P
IO_2_L64N_D9
IO_2_L64P_D8
IO_2_L65N_CSO_B
IO_2_L65P_INIT_B
FPGA - Bank 2
1
38/44
XC6SLX16-2CSG324C
U4C
R21
2K43 0402 DNP
R17
2K43 0402
R22
2K43 0402
MCU_FPGA_MODE1
MCU_FPGA_INIT_B
R18
2K43 0402 DNP
1
2
3
4
5
6
7
8
9
10
Place D29
close to J10
EXT SPI
FLASH
CON10 R127
56
J10
GREEN
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
C34
100nF
R40
NA 0402
R39
NA 0402
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
+VFPGA_IO_3V3
C33
10uF 10V 0805
33R2 0402
TO CORRECT
D29
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
R38
Place R38 close to the FPGA device
SPI FLASH CTRL SIGNALS
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a configuration data
error has occurred.
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
FPGA_INIT_B
FPGA_MODE0
FPGA_MODE1
R16
10K 0402
+VFPGA_IO_3V3
FPGA CONFIGURATION
PROG_LED7
PROG_LED6
PROG_LED5
PROG_LED4
PROG_LED3
PROG_LED2
PROG_LED1
PROG_LED0
68R 0402
R33
68R 0402
R31
68R 0402
R29
68R 0402
R27
68R 0402
R25
68R 0402
R23
68R 0402
R19
68R 0402
R14
YELLOW
D20
PROG 7
YELLOW
D18
PROG 6
YELLOW
D16
PROG 5
YELLOW
D14
PROG 4
YELLOW
D12
PROG 3
YELLOW
D10
PROG 2
YELLOW
D8
PROG 1
YELLOW
D6
PROG 0
PROGRAM SELECTOR LEDS
68R 0402
R34
68R 0402
R32
68R 0402
R30
68R 0402
R28
68R 0402
R26
68R 0402
R24
68R 0402
R20
68R 0402
R15
Kingbright KP-3216SYC
RS: 466-3942
LED 0805
PROG_LED15
PROG_LED14
PROG_LED13
PROG_LED12
PROG_LED11
PROG_LED10
PROG_LED9
PROG_LED8
YELLOW
D21
PROG 15
YELLOW
D19
PROG 14
YELLOW
D17
PROG 13
YELLOW
D15
PROG 12
YELLOW
D13
PROG 11
YELLOW
D11
PROG 10
YELLOW
D9
PROG 9
YELLOW
D7
PROG 8
Schematic diagrams
AN4472
Figure 30. STEVAL_IME008V1- Part 5
GSPG3009141200SG
SPI EXTERNAL PROGRAMMING HEADER
FPGA - Bank 3
DocID026198 Rev 1
XC6SLX16-2CSG324C
IO_3_L01N_VREF
IO_3_L01P
IO_3_L02N
IO_3_L02P
IO_3_L31N_VREF
IO_3_L31P
IO_3_L32N_M3DQ15
IO_3_L32P_M3DQ14
IO_3_L33N_M3DQ13
IO_3_L33P_M3DQ12
IO_3_L34N_M3UDQSN
IO_3_L34P_M3UDQS
IO_3_L35N_M3DQ11
IO_3_L35P_M3DQ10
IO_3_L36N_M3DQ9
IO_3_L36P_M3DQ8
IO_3_L37N_M3DQ1
IO_3_L37P_M3DQ0
IO_3_L38N_M3DQ3
IO_3_L38P_M3DQ2
IO_3_L39N_M3LDQSN
IO_3_L39P_M3LDQS
IO_3_L40N_M3DQ7
IO_3_L40P_M3DQ6
IO_3_L41N_GCLK26_M3DQ5
IO_3_L41P_GCLK27_M3DQ4
IO_3_L42N_GCLK24_M3LDM
IO_3_L42P_GCLK25_TRDY2_M3UDM
IO_3_L43N_GCLK22_IRDY2_M3CASN
IO_3_L43P_GCLK23_M3RASN
IO_3_L44N_GCLK20_M3A6
IO_3_L44P_GCLK21_M3A5
IO_3_L45N_M3ODT
IO_3_L45P_M3A3
IO_3_L46N_M3CLKN
IO_3_L46P_M3CLK
IO_3_L47N_M3A1
IO_3_L47P_M3A0
IO_3_L48N_M3BA1
IO_3_L48P_M3BA0
IO_3_L49N_M3A2
IO_3_L49P_M3A7
IO_3_L50N_M3BA2
IO_3_L50P_M3WE
IO_3_L51N_M3A4
IO_3_L51P_M3A10
IO_3_L52N_M3A9
IO_3_L52P_M3A8
IO_3_L53N_M3A12
IO_3_L53P_M3CKE
IO_3_L54N_M3A11
IO_3_L54P_M3RESET
IO_3_L55N_M3A14
IO_3_L55P_M3A13
IO_3_L83N_VREF
IO_3_L83P
U4D
N3
N4
P3
P4
M5
L6
U1
U2
T1
T2
P1
P2
N1
N2
M1
M3
L1
L2
K1
K2
L3
L4
J1
J3
H1
H2
K3
K4
K5
L5
H3
H4
K6
L7
G1
G3
J6
J7
F1
F2
H5
H6
E1
E3
F3
F4
D1
D2
G6
H7
D3
E4
F5
F6
C1
C2
FPGA BANK 3 NOT USED
AN4472
Schematic diagrams
Figure 31. STEVAL_IME008V1- Part 6
GSPG3009141415SG
39/44
44
8
7
6
5
1
2
3
4
CON14A
Xilinx Parallel IV Connector
2.0mm 7x2 shrouded header
DocID026198 Rev 1
SUSPEND
SW PUSHBUTTON-DPST
RS (378-6527)
MCU_FPGA_PROG
FPGA PROG
JUMPER
J13
R49
10K 0402
4
2
1
R50
10K 0402
4
FPGA_PROG
To be placed
near U3
C73
100nF
74LX1G08CTR
U7
+VFPGA_IO_3V3
74V1G32CTR
U6
Jumper J13 used to prevent FPGA from
programming from configuration source.
Set 1:2 to disable FPGA programming.
Open (default) to enable FPGA
programming.
FPGA PROG
DISABLE
1
2
2
10K 0402
R48
1
R46
10K 0402
A17
B18
D16
D15
FPGA_CMP_CS_B P13
V2
FPGA_PROG
FPGA_SUSPEND R16
V17
FPGA_DONE
FPGA_TCK
FPGA_TMS
FPGA_TDO
FPGA_TDI
CMPCS_B_2
PROGRAM_B_2
SUSPEND
DONE_2
TCK
TMS
TDO
TDI
U4E
XC6SLX16-2CSG324C
0.22uF 6.3V 0402
C44
FPGA_MCU_DONE
DONE
FPGA_DONE
DONE
Q1
2N7002
D23
GREEN
R51
56R
0805
R47
0
FPGA BANK 3
NOT USED
E2
G4
J2
J5
M4
R2
P9
R12
R6
U14
U4
U9
E17
G15
J14
J17
M15
R17
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
C69
C72
4.7uF 6.3V 0603
C68
C71
4.7uF 6.3V 0603
C67
+VFPGA_IO_3V3
C70
100uF 6.3V 1206
0.22uF 6.3V 0402
C61
0.22uF 6.3V 0402
C65
4.7uF 6.3V 0603
C60
0.22uF 6.3V 0402
C63
0.22uF 6.3V 0402
4.7uF 6.3V 0603
C64
C59
100uF 6.3V 1206
0.22uF 6.3V 0402
+VFPGA_IO_3V3
C57
0.22uF 6.3V 0402
C58
C66
C54
0.22uF 6.3V 0402
C56
4.7uF 6.3V 0603
C53
0.22uF 6.3V 0402
4.7uF 6.3V 0603
100uF 6.3V 1206
C55
C52
C51
C35, C40, C51, C58, C66 Details
C36, C37, C38, C41, C42, C52, C53, C59, C60, C67, C68 Details
Murata (GRM31CR60J107ME39L) - Digikey (490-4539-1-ND) TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND)
Dimension 1206 - EIA 3216
Dimension 0603 - EIA 1608
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B10
B15
B5
D13
D7
E10
+VFPGA_IO_3V3
0.22uF 6.3V 0402
0.22uF 6.3V 0402
XC6SLX16-3CSG324C
C50
C49
0.22uF 6.3V 0402
0.22uF 6.3V 0402
C48
4.7uF 6.3V 0603
C47
0.22uF 6.3V 0402
0.22uF 6.3V 0402
R52
330 0402
+VFPGA_IO_3V3
C42
0.22uF 6.3V 0402
C46
C45
FPGA - Power & Configuration
C41
C43
C40
4.7uF 6.3V 0603
0.22uF 6.3V 0402
4.7uF 6.3V 0603
100uF 6.3V 1206
C39
C38
4.7uF 6.3V 0603
4.7uF 6.3V 0603
100uF 6.3V 1206
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
C37
C36
C35
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
A1
J9
K10
V18
V1
U6
U12
T16
R9
R4
R18
R14
R1
N13
M6
M2
M17
L9
L11
K8
G12
E15
J4
J15
J11
H8
H10
G5
G2
G17
C16
B7
D5
D10
C3
B13
A18
RST1
1
2
3
Header 3
J12
C62
100nF
10K 0402
R45
NOT ASSEMBLY
R43 49R 0402
NOT ASSEMBLY
R44 49R 0402
NOT ASSEMBLY
R42 49R 0402
NOT ASSEMBLY
R41 49R 0402
RESDIP4X1206
RN1
RESISTOR DIP 4
4-Resistor Array
3.2x1.6mm
Not Assembly
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PROGRAM_B
Jumper J12
1:2 to force
FPGA into
suspend mode.
2:3 (Default)
to allow MCU
to control
FPGA suspend
mode.
MCU_FPGA_SUSPEND
To be placed
near U6
+VFPGA_IO_3V3
SUSPEND & CMPCS_B
1
3
5
7
9
11
13
J11
NOT ASSEMBLY
2
4
6
8
10
12
14
FPGA JTAG
D22
STTH102A
NOT ASSEMBLY
5
+VFPGA_IO_3V3
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
3
P5
P14
P10
M9
K7
J12
G10
E9
E5
E14
B17
B1
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
5
40/44
M7
M12
L8
L10
K9
K11
J8
J10
H9
H11
G7
3
FPGA JTAG
Schematic diagrams
AN4472
Figure 32. STEVAL_IME008V1- Part 7
GSPG3009141430SG
DocID026198 Rev 1
IN3_1
17
47
48
1
IN3_0
18
IN3_2
19
13
1
2
1
2
1
B2S J16
B2S J17
LVOUT_4
Jlch4
BNC
IN3_1
270p 100V 0603
LVOUT_3
C112
270p 100V 0603
LVOUT_4
LVOUT_2
100
R62
15
LVOUT_1
C113
46
100
R53
45
1
44
1
20
Jlch3
BNC
LVOUT_3
43
CW
2
2
DGND
C75
IN2_2
IN2_1
IN2_0
IN1_2
IN1_1
IN1_0
CW
25
26
27
20p 0805
20p 0805
SEL
VDDM
28 HVP1
29
30
31
CK
J25
CON3
CX12
C97
220n
C83
220n
C87
220n
C85
C101 220n
CX11 220n
220n
220n
HVP_CW
CX7
220n
DVDD
32 HVP0
33
34
35
36
STHV749
IN4_2
IN4_1
IN4_0
IN3_2
IN3_1
IN3_0
VDDP
VDDP
AGND
VDDM
HVP1
HVP1
HVP1
HVP0
HVP0
HVP0
HVP_CW
C74
IN4_0
STHV749
IN1_2
CW
21
IN4_1
J31
B2S
22
IN1_1
J28
B2S
40
IN4_2
CK
23
THSD
IN1_0
CK
D36
DFLS1200
XDCR_4
XDCR_3
HVM_CW
39
VDDP
D38
DFLS1200
D35
DFLS1200
12
11
20p 0805
C92
DVDD
20p 0805
C76
24
CK
CW
HVM0
HVP0
DFLS1200
D37
HVM_CW 10
220n
C86
HVM1
HVM1
2
2
38
THSD_EN
1
1
9
220n
CX4
B2S J14
B2S J15
37
THSD_EN
2
SEL
BNC
Jch4
BNC
Jch3
CX1
8
220n
CX2
IN2_2
SEL
XDCR_4
XDCR_3
220n
CX5
GND_PWR
IN6_1
IN6_0
IN5_1
220n
220n
C93
HVM1
HVM0
HVM0
GND_PWR
IN4_2
IN4_1
IN4_1
IN5_0
2
IN4_0
IN3_2
7
220n HVM1
C88
6
5
220n
CX3
HVM0
GND_PWR
XDCR_2
XDCR_1
IN2_1
IN4_0
220n
CX6
4
220n HVM0
C90
3
2
1
42
IN3_0
220n
C91
D32
DFLS1200
1
1
IN2_0
IN3_1
IN3_0
1
D34
Jlch2
LVOUT_2
BNC
1
1
LVOUT_1
41
IN2_2
IN2_1
IN2_1
BNC
Jch2
1
DFLS1200
D33
1
IN2_0
IN2_0
XDCR_2
IN1_1
BNC
Jch1
2
IN1_2
IN1_1
XDCR_1
IN1_0
DFLS1200
U8
DFLS1200
D31
J21
B2S
R55
100
Jlch1
BNC
2
IN1_0
HVM1
HVM0
HVM_CW
HVM0
HVP0
1
HVM1
HVM0
HVM_CW
DVDD
VDDP
VDDM
DVDD
VDDP
VDDM
2
HVP1
HVP0
HVP_CW
C80
J20
B2S
C77
2
HVP1
HVP0
HVP_CW
R54
100
270p 100V 0603
2
3
2
1
220n
CX9
TP3
TEST POINT
1
2
3
CON3
J24
THSD
J16, J17, J22, J23, J25, J26, J29 and J30 Details
Tyco Electronics (1-1337482-0) - RS (420-5401)
R59
100k
THSD
R58
10k
THSD_EN
DVDD
C77, C80, C111, C112 Details
DigiKey (490-1462-2-ND) Murata (GRM188R72A271KA01D)
J16, J17, J22, J23, J25, J26, J29 and J30 Details
Tyco Electronics (1-1337482-0) - RS (420-5401)
D1, D2, D3 ,D4, D5, D6, D7, D8
diode DFLS1200 rs-code 708-2324
C102 220n
CX8
220n
C89
220n
CX10
220n
220n C95
CK
1
270p 100V 0603
AN4472
Schematic diagrams
Figure 33. STEVAL_IME008V1- Part 8
GND_PWR
2
16
GND_PWR
14
2
2
GSPG0110140925SG
41/44
44
FLASH_DQ0
FLASH_C
FLASH_nS
FLASH_DQ2
FLASH_DQ3
4k7
4k7
DocID026198 Rev 1
FPGA_GPIO0
FPGA_GPIO1
FPGA_GPIO2
FPGA_GPIO3
FPGA_GPIO4
FPGA_GPIO5
FPGA_GPIO6
FPGA_GPIO7
STM32_GPIO_8
STM32_GPIO_9
STM32_GPIO_10
STM32_GPIO_11
STM32_GPIO_12
STM32_GPIO_13
STM32_GPIO_14
R82
R83
R84
R85
R86
R88
R89
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
FPGA_GPIO[0:7]
C122
100nF
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
FPGA_GPIO[0:7]
C123
1uF 6.3V
R66
4K7
MCU_3V3
9
44
20
7
JNTRST
JTMS
JTCK
JTDO
JTDI
RESET#
R76
10k
R77
10k
R78
10k
MCU_3V3
STM32F103C8T6
VDDA
BOOT0
PB2-BOOT1
NRST
PC14-OSC32_IN
PC15-OSC32_OUT
PC13-Tamper-RTC
PA0-WKUP
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
JTAG/SWD
R67
4K7
VDDA
BOOT0
BOOT1
RESET#
3
4
2
10
STM32_GPIO_0
11
STM32_GPIO_1
12
STM32_GPIO_2
13
STM32_GPIO_3
14
STM32_GPIO_4
15
STM32_GPIO_5
16
STM32_GPIO_6
17
STM32_GPIO_7
29
STM32_GPIO_8
30
STM32_GPIO_9
USB_DISCONNECT31
32
DM_STM32
33
DP_STM32
MCU
R79
10k
2
R87
10k
OSCIN
OSCOUT
5
6
2
4
6
8
10
1
3
5
7
9
MCU JTAG
SWD/JTAG
J40
Male Connector 2x5
Pitch 1.27 mm
SAMTEC FTSH-105-01-F-D-K
MCU_3V3
USER_LED1
USER_LED2
STM32_GPIO_10
STM32_GPIO_11
STM32_GPIO_12
STM32_GPIO_13
STM32_GPIO_14
FLASH_DQ3
FLASH_DQ2
FLASH_nS
FLASH_C
FLASH_DQ1
FLASH_DQ0
JNTRST
JTDO
JTDI
JTCK
JTMS
C120
100nF
MCU_3V3
18
19
41
42
43
45
46
21
22
25
26
27
28
STM32F103
PD0 OSC_IN
PD1 OSC_OUT
PB0
PB1
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB4 JNTRST
PB3 JTDO
PA15 JTDI
PA14 JTCK
PA13 JTMS
U10
40
39
38
37
34
C119
100nF
Place near MCU
C118
100nF
FLASH_3V3
MCU_3V3
JP1 JUMPER
1
MCU_3V3
47
35
23
8
OPTIONAL FPGA CONFIGURATION SIGNALS
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
FLASH_DQ1
INT SPI FLASH
USB_DISCONNECT
USB_DM
USB_DP
FLASH_DQ1
2
N25Q032xSC
DQ0
DQ1
C
nS
nW/Vpp/DQ2
nHOLD/DQ3
D30
RED
56
MCU_3V3
FLASH_3V3
VSS_3
VSS_2
VSS_1
VSSA
R69
R70
R71
R72
R73
R74
R75
R80
5
6
1
3
7
U9
0R - N/A
R128
FLASH DISABLE
Use J38 to enable/disable power for SPI flash device.
J38 must be open when using external spi flash device on
connecto J10. Default value closed.
C123 Details:
Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)
Package 0402
R131
C116
100nF
4k7
R64
2
1
J38
VBAT
VDD_1
VDD_2
VDD_3
STM32_GPIO_0
STM32_GPIO_1
STM32_GPIO_2
STM32_GPIO_3
STM32_GPIO_4
STM32_GPIO_5
STM32_GPIO_6
STM32_GPIO_7
OPTIONAL FPGA I/O
FLASH_DQ0
FLASH_C
FLASH_nS
FLASH_DQ2
FLASH_DQ3
R130
R129
FLASH_3V3
8
VCC
VSS
42/44
1
24
36
48
4
SPI FLASH
C121
100nF
RST2
MCU RESET
Not Assembly
RS (505-9186)
C&K (Y78B22110FP)
SW PUSHBUTTON-DPST
OSCOUT
8MHz
Y1
R68 56R
USER_LED1
R81 56R
USER_LED2
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
D25
FLASH READY
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
D24
DOWNLOAD
Murata (CSTCE8M00G55-R0)
DigiKey (490-1195-1-ND)
RS: 283-961
Farnell: 1615352
8MHZ OSC
OSCIN
OSCILLATOR
C117
100nF
RESET#
R65
10K
MCU_3V3
Schematic diagrams
AN4472
Figure 34. STEVAL_IME008V1- Part 9
GSPG0110140950SG
AN4472
6
Revision history
Revision history
Table 32. Document revision history
Date
Revision
10-Dec-2014
1
Changes
Initial release.
DocID026198 Rev 1
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