73 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DS162 (v1.9) August 23, 2010 Advance Product Specification Spartan-6 FPGA Electrical Characteristics Spartan®-6 LX FPGAs are available in -3, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT FPGAs are available in -4, -3, and -2 speed grades, with -4 having the highest performance. Spartan-6 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -2 speed grade industrial device are the same as for a -2 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. The -3N speed grade, designated for Spartan-6 devices that do not support memory controller block (MCB) functionality, has identical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on the Xilinx website. All specifications are subject to change without notice. Spartan-6 FPGA DC Characteristics Table 1: Absolute Maximum Ratings (1) Symbol Description Units VCCINT Internal supply voltage relative to GND –0.5 to 1.32 V VCCAUX Auxiliary supply voltage relative to GND –0.5 to 3.75 V VCCO Output drivers supply voltage relative to GND –0.5 to 3.75 V VBATT Key memory battery backup supply (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) –0.5 to 4.05 V VFS External voltage supply for eFUSE programming (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only)(2) –0.5 to 3.75 V VREF Input reference voltage –0.5 to 3.75 V –0.60 to 4.10 V –0.75 to 4.25 V –0.75 to 4.40 V –0.60 to 3.95 V –0.75 to 4.15 V –0.75 to 4.40 V DC Commercial 20% overshoot duration 8% overshoot All user and dedicated I/Os DC Industrial VIN and VTS(3) duration(5) I/O input voltage or voltage applied to 3-state output, relative to GND(4) 20% overshoot duration 4% overshoot duration(5) 20% overshoot duration –0.75 to 4.35 V –0.75 to 4.40 V 10% overshoot duration –0.75 to 4.45 V 20% overshoot duration –0.75 to 4.25 V 10% overshoot duration –0.75 to 4.35 V 8% overshoot duration(5) –0.75 to 4.40 V Commercial 15% overshoot duration(5) Restricted to maximum of 100 user I/Os Industrial © 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 1 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings (1) (Cont’d) Symbol TSTG Description Units Storage temperature (ambient) –65 to 150 °C Maximum soldering (TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256) +260 °C Maximum soldering temperature(6) (Pb-free packages: FGG484, FGG676, and FGG900) +250 °C Maximum soldering temperature(6) (Pb packages: FT256, FG484, FG676, and FG900) +220 °C Maximum junction temperature(6) +125 °C temperature(6) TSOL Tj Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. When programming eFUSE, VFS ≤ VCCAUX. Requires up to 40 mA current. For read mode, VFS can be between GND and 3.45 V. 3. I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressed beyond 3.45V. 4. For I/O operation, refer to the Spartan-6 FPGA SelectIO Resources User Guide. 5. Maximum percent overshoot duration to meet 4.40V maximum. 6. For soldering guidelines and thermal considerations, see Spartan-6 FPGA Packaging and Pinout Specification. Table 2: Recommended Operating Conditions(1) Symbol Description Internal supply voltage relative to GND, Tj = 0°C to +85°C VCCINT VCCAUX(3) VCCO(4)(5)(6) VIN Internal supply voltage relative to GND, Tj = –40°C to +100°C Temperature Range Speed Grade Memory Controller Block(2) Performance Min Typ Max Units Commercial -4, -3, -2 standard 1.14 1.2 1.26 V extended 1.2 1.23 1.26 V -1L standard 0.95 1.0 1.05 V -3, -2 standard 1.14 1.2 1.26 V extended 1.2 1.23 1.26 V -1L standard 0.95 1.0 1.05 V 2.375 2.5 2.625 V 3.15 3.3 3.45 V 1.1 – 3.45 V –0.5 – 4.0 V –0.5 – –0.5 – VCCO + 0.5 V –0.5 – VCCO + 0.5 V Industrial Auxiliary supply voltage relative to GND when VCCAUX = 2.5V, Tj = 0°C to +85°C Commercial -4, -3, -2, -1L N/A Auxiliary supply voltage relative to GND when VCCAUX = 2.5V, Tj = –40°C to +100°C Industrial -3, -2, -1L N/A Auxiliary supply voltage relative to GND when VCCAUX = 3.3V, Tj = 0°C to +85°C Commercial -4, -3, -2, -1L N/A Auxiliary supply voltage relative to GND when VCCAUX = 3.3V, Tj = –40°C to +100°C Industrial -3, -2, -1L N/A Output supply voltage relative to GND, Tj = 0°C to +85°C Commercial -4, -3, -2, -1L N/A Output supply voltage relative to GND, Tj = –40°C to +100°C Industrial -3, -2, -1L N/A Input voltage relative to GND, Tj = 0°C to +85°C Commercial -4, -3, -2, -1L N/A Input voltage relative to GND, Tj = –40°C to +100°C Industrial -3, -2, -1L N/A Input voltage relative to GND, PCI I/O standard, Tj = 0°C to +85°C Commercial -4, -3, -2, -1L(7) N/A Input voltage relative to GND, PCI I/O standard, Tj = –40°C to +100°C Industrial -3, -2, -1L(7) N/A DS162 (v1.9) August 23, 2010 Advance Product Specification 3.95 V www.xilinx.com 2 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 2: Recommended Operating Conditions(1) (Cont’d) Symbol Description IIN(8) Maximum current through pin using PCI I/O standard when forward biasing the clamp diode. VBATT(9) Battery voltage relative to GND, Tj = 0°C to +85°C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) Battery voltage relative to GND, Tj = –40°C to +100°C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) Memory Controller Block(2) Performance Temperature Range Speed Grade Commercial -4, -3, -2, -1L(7) N/A Industrial -3, -2, -1L(7) N/A Commercial -4, -3, -2, -1L N/A Industrial -3, -2, -1L N/A Min Typ Max Units – – 10 mA – – 10 mA 1.0 – 3.6 V Notes: 1. All voltages are relative to ground. 2. See Interface Performances for Memory Interfaces in Table 25. The standard VCCINT voltage range applies to designs not using an MCB, or to devices that do not support MCB functionality including the LX4 device, the TQG144 and CPG196 packages, and the -3N speed grade. 3. Recommended maximum voltage droop for VCCAUX is 10 mV/ms. 4. Configuration data is retained even if VCCO drops to 0V. 5. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. 6. For PCI systems, the transmitter and receiver should have common supplies for VCCO. 7. Devices with a -1L speed grade do not support Xilinx PCI IP. 8. Do not exceed a total of 100 mA per bank. 9. VBATT is required to maintain the battery backed RAM (BBR) AES key when VCCAUX is not applied. Once VCCAUX is applied, VBATT can be unconnected. When BBR is not used, Xilinx recommends connecting to VCCAUX or GND. However, VBATT can be unconnected. Table 3: eFUSE Programming Conditions(1) Symbol VFS(2) IFS VCCAUX Description External voltage supply VFS supply current Auxiliary supply voltage relative to GND RFUSE(3) External resistor from RFUSE pin to GND VCCINT tj Internal supply voltage relative to GND Temperature range Min Typ Max Units 3.2 3.3 3.4 V – – 40 mA 3.2 3.3 3.45 V 1129 1140 1151 Ω 1.14 1.2 1.26 V 15 – 85 °C Notes: 1. These specifications apply during programming of the eFUSE AES key. Programming is only supported through JTAG.The AES key is only supported in the following devices: XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T. 2. When programming eFUSE, VFS must be less than or equal to VCCAUX. When not programming or when eFUSE is not used, Xilinx recommends connecting VFS to GND. However, VFS can be between GND and 3.45 V. 3. An RFUSE resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx recommends connecting the RFUSE pin to VCCAUX or GND. However, RFUSE can be unconnected. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 3 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 4: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.8 – – V VDRAUX Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 – – V VREF leakage current per pin –10 – 10 µA Input or output leakage current per pin (sample-tested) –10 – 10 µA –20 – 20 µA IREF IL IHS Leakage current on pins during hot socketing with FPGA unpowered CIN Die input capacitance at the pad IRPU IRPD IBATT(1) RDT (2) RIN_TERM(4) All pins except PROGRAM_B, DONE, and JTAG pins when HSWAPEN = 1 PROGRAM_B, DONE, and JTAG pins, or other pins when HSWAPEN = 0 IHS + IRPU µA – – 10 pF Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V or VCCAUX = 3.3V 200 – 500 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V or VCCAUX = 2.5V 120 – 350 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 60 – 200 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 40 – 150 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 12 – 100 µA Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 3.3V 200 – 550 µA Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 2.5V 140 – 400 µA Battery supply current – – 150 nA Resistance of optional input differential termination circuit, VCCAUX = 3.3V – 100 – Ω Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_25) 23 25 55 Ω Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_50) 39 50 72 Ω Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_75) 56 75 109 Ω Notes: 1. Maximum value specified for worst case process at 25°C. XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only. 2. Refer to IBIS models for RDT variation and for values at VCCAUX = 2.5V. 3. VCCO2 is not required for data retention. The minimum VCCO2 for power-on reset and configuration is 1.65V. 4. Termination resistance to a VCCO/2 level. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 4 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Quiescent Current Typical values for quiescent supply current are specified at nominal voltage, 25°C junction temperatures (Tj). Quiescent supply current is specified by speed grade for Spartan-6 devices. Xilinx recommends analyzing static power consumption using the XPOWER™ Estimator (XPE) tool (download at http://www.xilinx.com/power) for conditions other than those specified in Table 5. Table 5: Typical Quiescent Supply Current Symbol ICCINTQ ICCOQ Description Quiescent VCCINT supply current Quiescent VCCO supply current DS162 (v1.9) August 23, 2010 Advance Product Specification Device Speed Grade Units -4 -3 -2 -1L XC6SLX4 N/A 4.0 4.0 2.4 mA XC6SLX9 N/A 4.0 4.0 2.4 mA XC6SLX16 N/A 6.0 6.0 4.0 mA XC6SLX25 N/A 11.0 11.0 6.6 mA XC6SLX25T 11.0 11.0 11.0 N/A mA XC6SLX45 N/A 15.0 15.0 9.0 mA XC6SLX45T 15.0 15.0 15.0 N/A mA XC6SLX75 N/A 29.0 29.0 17.4 mA XC6SLX75T 29.0 29.0 29.0 N/A mA XC6SLX100 N/A 36.0 36.0 21.6 mA XC6SLX100T 36.0 36.0 36.0 N/A mA XC6SLX150 N/A 51.0 51.0 31.0 mA XC6SLX150T 51.0 51.0 51.0 N/A mA XC6SLX4 N/A 1.0 1.0 1.0 mA XC6SLX9 N/A 1.0 1.0 1.0 mA XC6SLX16 N/A 2.0 2.0 2.0 mA XC6SLX25 N/A 2.0 2.0 2.0 mA XC6SLX25T 2.0 2.0 2.0 N/A mA XC6SLX45 N/A 3.0 3.0 3.0 mA XC6SLX45T 3.0 3.0 3.0 N/A mA XC6SLX75 N/A 4.0 4.0 4.0 mA XC6SLX75T 4.0 4.0 4.0 N/A mA XC6SLX100 N/A 5.0 5.0 5.0 mA XC6SLX100T 5.0 5.0 5.0 N/A mA XC6SLX150 N/A 7.0 7.0 7.0 mA XC6SLX150T 7.0 7.0 7.0 N/A mA www.xilinx.com 5 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 5: Typical Quiescent Supply Current (Cont’d) Symbol ICCAUXQ Description Speed Grade Device Quiescent VCCAUX supply current Units -4 -3 -2 -1L XC6SLX4 N/A 2.5 2.5 2.5 mA XC6SLX9 N/A 2.5 2.5 2.5 mA XC6SLX16 N/A 3.0 3.0 3.0 mA XC6SLX25 N/A 4.0 4.0 4.0 mA XC6SLX25T 4.0 4.0 4.0 N/A mA XC6SLX45 N/A 5.0 5.0 5.0 mA XC6SLX45T 5.0 5.0 5.0 N/A mA XC6SLX75 N/A 7.0 7.0 7.0 mA XC6SLX75T 7.0 7.0 7.0 N/A mA XC6SLX100 N/A 9.0 9.0 9.0 mA XC6SLX100T 9.0 9.0 9.0 N/A mA XC6SLX150 N/A 12.0 12.0 12.0 mA XC6SLX150T 12.0 12.0 12.0 N/A mA Notes: 1. Typical values are specified at nominal voltage, 25°C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as commercial (C) grade devices at 25°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. If differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. Table 6: Power Supply Ramp Time Symbol VCCINTR Description Speed Grade Ramp Time Units -4, -3, -2 0.20 to 50.0 ms -1L 0.20 to 40.0 ms Internal supply voltage ramp time VCCO2(1) Output drivers bank 2 supply voltage ramp time All 0.20 to 50.0 ms VCCAUXR Auxiliary supply voltage ramp time All 0.20 to 50.0 ms Notes: 1. The minimum VCCO2 for power-on reset and configuration is 1.65V 2. Spartan-6 FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. Use the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools to estimate current drain on these supplies. Spartan-6 devices do not have a required power-on sequence. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 6 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SelectIO™ Interface DC Input and Output Levels Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards I/O Standard VCCO for Drivers(1) VREF for Inputs V, Min V, Nom V, Max V, Min V, Nom V, Max LVTTL 3.0 3.3 3.45 LVCMOS33 3.0 3.3 3.45 LVCMOS25 2.3 2.5 2.7 LVCMOS18 1.65 1.8 1.95 LVCMOS18_JEDEC 1.65 1.8 1.95 LVCMOS15 1.4 1.5 1.6 LVCMOS15_JEDEC 1.4 1.5 1.6 LVCMOS12 1.1 1.2 1.3 LVCMOS12_JEDEC 1.1 1.2 1.3 PCI33_3(2) 3.0 3.3 3.45 PCI66_3(2) 3.0 3.3 3.45 I2C 2.7 3.0 3.45 SMBUS 2.7 3.0 3.45 SDIO 3.0 3.3 3.45 MOBILE_DDR 1.7 1.8 1.9 HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 HSTL_II 1.4 1.5 1.6 0.68 0.75 0.9 HSTL_III 1.4 1.5 1.6 – 0.9 – HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 HSTL_II_18 1.7 1.8 1.9 – 0.9 – HSTL_III_18 1.7 1.8 1.9 – 1.1 – SSTL3_I 3.0 3.3 3.45 1.3 1.5 1.7 SSTL3_II 3.0 3.3 3.45 1.3 1.5 1.7 SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 SSTL18_I 1.7 1.8 1.9 0.833 0.9 0.969 SSTL18_II 1.7 1.8 1.9 0.833 0.9 0.969 SSTL15_II 1.425 1.5 1.575 0.69 0.75 0.81 VREF is not used for these I/O standards Notes: 1. 2. VCCO range required when using I/O standard for an output. Also required for PCI33_3, LVCMOS18_JEDEC, LVCMOS15_JEDEC, and LVCMOS12_JEDEC inputs, and for LVCMOS25 inputs when VCCAUX = 3.3V. For PCI systems, the transmitter and receiver should have common supplies for VCCO. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 7 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 8: Recommended Operating Conditions for User I/Os Using Differential Signal Standards VCCO for Drivers I/O Standard V, Min V, Nom V, Max LVDS_33 3.0 3.3 3.45 LVDS_25 2.25 2.5 2.75 BLVDS_25 2.25 2.5 2.75 MINI_LVDS_33 3.0 3.3 3.45 MINI_LVDS_25 2.25 2.5 2.75 LVPECL_33(1) N/A–Inputs Only LVPECL_25 N/A–Inputs Only RSDS_33 3.0 3.3 3.45 RSDS_25 2.25 2.5 2.75 TMDS_33(1) 3.14 3.3 3.45 PPDS_33 3.0 3.3 3.45 PPDS_25 2.25 2.5 2.75 DISPLAY_PORT 2.3 2.5 2.7 DIFF_MOBILE_DDR 1.7 1.8 1.9 DIFF_HSTL_I 1.4 1.5 1.6 DIFF_HSTL_II 1.4 1.5 1.6 DIFF_HSTL_III 1.4 1.5 1.6 DIFF_HSTL_I_18 1.7 1.8 1.9 DIFF_HSTL_II_18 1.7 1.8 1.9 DIFF_HSTL_III_18 1.7 1.8 1.9 DIFF_SSTL3_I 3.0 3.3 3.45 DIFF_SSTL3_II 3.0 3.3 3.45 DIFF_SSTL2_I 2.3 2.5 2.7 DIFF_SSTL2_II 2.3 2.5 2.7 DIFF_SSTL18_I 1.7 1.8 1.9 DIFF_SSTL18_II 1.7 1.8 1.9 DIFF_SSTL15_II 1.425 1.5 1.575 Notes: 1. LVPECL_33 and TMDS_33 inputs require VCCAUX = 3.3V nominal. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 8 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics In Table 9 and Table 10, values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 9: Single-Ended I/O Standard DC Input and Output Levels I/O Standard VIH VIL VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL –0.5 0.8 2.0 4.1 0.4 2.4 Note(2) Note(2) LVCMOS33 –0.5 0.8 2.0 4.1 0.4 VCCO – 0.4 Note(2) Note(2) LVCMOS25 –0.5 0.7 1.7 4.1 0.4 VCCO – 0.4 Note(2) Note(2) LVCMOS18 –0.5 0.38 0.8 4.1 0.45 VCCO – 0.45 Note(2) Note(2) LVCMOS18 (-1L) –0.5 0.33 0.71 4.1 0.45 VCCO – 0.45 Note(2) Note(2) LVCMOS18_JEDEC –0.5 35% VCCO 65% VCCO 4.1 0.45 VCCO – 0.45 Note(2) Note(2) LVCMOS15 –0.5 0.38 0.8 4.1 25% VCCO 75% VCCO Note(3) Note(3) LVCMOS15 (-1L) –0.5 0.33 0.71 4.1 25% VCCO 75% VCCO Note(3) Note(3) LVCMOS15_JEDEC –0.5 35% VCCO 65% VCCO 4.1 25% VCCO 75% VCCO Note(3) Note(3) LVCMOS12 –0.5 0.38 0.8 4.1 0.4 VCCO – 0.4 Note(4) Note(4) LVCMOS12 (-1L) –0.5 0.33 0.71 4.1 0.4 VCCO – 0.4 Note(4) Note(4) LVCMOS12_JEDEC –0.5 35% VCCO 65% VCCO 4.1 0.4 VCCO – 0.4 Note(4) Note(4) PCI33_3 –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO 1.5 –0.5 PCI66_3 –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO 1.5 –0.5 I2C –0.5 25% VCCO 70% VCCO 4.1 20% VCCO – 3 – SMBUS –0.5 0.8 2.1 4.1 0.4 – 4 – SDIO –0.5 12.5% VCCO 75% VCCO 4.1 12.5% VCCO 75% VCCO 0.1 –0.1 MOBILE_DDR –0.5 20% VCCO 80% VCCO 4.1 10% VCCO 90% VCCO 0.1 –0.1 HSTL_I –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 8 –8 HSTL_II –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 16 –16 HSTL_III –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 24 –8 HSTL_I_18 –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 11 –11 HSTL_II_18 –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 22 –22 HSTL_III_18 –0.5 VREF – 0.1 VREF + 0.1 4.1 0.4 VCCO – 0.4 30 –11 SSTL3_I –0.5 VREF – 0.2 VREF + 0.2 4.1 VTT – 0.6 VTT + 0.6 8 –8 SSTL3_II –0.5 VREF – 0.2 VREF + 0.2 4.1 VTT – 0.8 VTT + 0.8 16 –16 SSTL2_I –0.5 VREF – 0.15 VREF + 0.15 4.1 VTT – 0.61 VTT + 0.61 8.1 –8.1 SSTL2_II –0.5 VREF – 0.15 VREF + 0.15 4.1 VTT – 0.81 VTT + 0.81 16.2 –16.2 SSTL18_I –0.5 VREF – 0.125 VREF + 0.125 4.1 VTT – 0.47 VTT + 0.47 6.7 –6.7 SSTL18_II –0.5 VREF – 0.125 VREF + 0.125 4.1 VTT – 0.60 VTT + 0.60 13.4 –13.4 SSTL15_II –0.5 VREF – 0.1 VREF + 0.1 4.1 VTT – 0.4 VTT + 0.4 13.4 –13.4 Notes: 1. Tested according to relevant specifications. 2. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 3. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 4. Using drive strengths of 2, 4, 6, 8, or 12 mA. 5. For more information, refer to the Spartan-6 FPGA SelectIO Resources User Guide. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 9 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 10: Differential I/O Standard DC Input and Output Levels VID VICM VOD VOCM VOH VOL mV, Min mV, Max V, Min V, Max mV, Min mV, Max V, Min V, Max V, Min V, Max LVDS_33 100 600 0.3 2.35 247 454 1.125 1.375 – – LVDS_25 100 600 0.3 2.35 247 454 1.125 1.375 – – BLVDS_25 100 – 0.3 2.35 240 460 Typical 50% VCCO – – MINI_LVDS_33 200 600 0.3 1.95 300 600 1.0 1.4 – – MINI_LVDS_25 200 600 0.3 1.95 300 600 1.0 1.4 – – LVPECL_33 100 1000 0.3 2.8(1) Inputs only LVPECL_25 100 1000 0.3 1.95 Inputs only RSDS_33 100 – 0.3 1.5 100 400 1.0 1.4 – – RSDS_25 100 – 0.3 1.5 100 400 1.0 1.4 – – TMDS_33 150 1200 2.7 3.23(1) 400 800 – – PPDS_33 100 400 0.2 2.3 100 400 0.5 1.4 – – PPDS_25 100 400 0.2 2.3 100 400 0.5 1.4 – – DISPLAY_PORT 190 1260 0.3 2.35 – – Typical 50% VCCO – – DIFF_MOBILE_DDR 100 – 0.78 1.02 – – – – 90% VCCO 10% VCCO DIFF_HSTL_I 100 – 0.68 0.9 – – – – VCCO – 0.4 0.4 DIFF_HSTL_II 100 – 0.68 0.9 – – – – VCCO – 0.4 0.4 DIFF_HSTL_III 100 – 0.68 0.9 – – – – VCCO – 0.4 0.4 DIFF_HSTL_I_18 100 – 0.8 1.1 – – – – VCCO – 0.4 0.4 DIFF_HSTL_II_18 100 – 0.8 1.1 – – – – VCCO – 0.4 0.4 DIFF_HSTL_III_18 100 – 0.8 1.1 – – – – VCCO – 0.4 0.4 DIFF_SSTL3_I 100 – 1.0 1.9 – – – – VTT + 0.6 VTT – 0.6 DIFF_SSTL3_II 100 – 1.0 1.9 – – – – VTT + 0.8 VTT – 0.8 DIFF_SSTL2_I 100 – 1.0 1.5 – – – – VTT + 0.61 VTT – 0.61 DIFF_SSTL2_II 100 – 1.0 1.5 – – – – VTT + 0.81 VTT – 0.81 DIFF_SSTL18_I 100 – 0.7 1.1 – – – – VTT + 0.47 VTT – 0.47 DIFF_SSTL18_II 100 – 0.7 1.1 – – – – VTT + 0.6 VTT – 0.6 DIFF_SSTL15_II 100 – 0.55 0.95 – – – – VTT + 0.4 VTT – 0.4 I/O Standard VCCO – 0.405 VCCO – 0.190 Notes: 1. LVPECL_33 and TMDS_33 maximum VICM is the lower of V (maximum) or VCCAUX – (VID/2) eFUSE Read Endurance Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see the Spartan-6 FPGA Configuration User Guide. Table 11: eFUSE Read Endurance Symbol Description DNA_CYCLES Number of DNA_PORT READ operations or JTAG ISC_DNA read command operations. Unaffected by SHIFT operations. AES_CYCLES Number of JTAG FUSE_KEY or FUSE_CNTL read command operations. Unaffected by SHIFT operations. DS162 (v1.9) August 23, 2010 Advance Product Specification Speed Grade -4 -3 -2 30,000,000 30,000,000 -1L Units (Min) Read Cycles Read Cycles www.xilinx.com 10 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics GTP Transceiver Specifications GTP transceivers are available in the Spartan-6 LXT family of devices. See DS160: Spartan-6 Family Overview for more information. GTP Transceiver DC Characteristics Table 12: Absolute Maximum Ratings for GTP Transceivers(1) Symbol MIn Max Units Analog supply voltage for the GTP transmitter and receiver circuits relative to GND –0.5 1.32 V MGTAVTTTX Analog supply voltage for the GTP transmitter termination circuit relative to GND –0.5 1.32 V MGTAVTTRX Analog supply voltage for the GTP receiver termination circuit relative to GND –0.5 1.32 V Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to GND –0.5 1.32 V Analog supply voltage for the resistor calibration circuit of the GTP transceiver bank (top or bottom) –0.5 1.32 V Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.32 V Reference clock absolute input voltage –0.5 1.32 V MGTAVCC MGTAVCCPLL MGTAVTTRCAL VIN VMGTREFCLK Description Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Table 13: Recommended Operating Conditions for GTP Transceivers(1)(2)(3) Symbol Description Min Typ Max Units MGTAVCC Analog supply voltage for the GTP transmitter and receiver circuits relative to GND 1.14 1.20 1.26 V MGTAVTTTX Analog supply voltage for the GTP transmitter termination circuit relative to GND 1.14 1.20 1.26 V MGTAVTTRX Analog supply voltage for the GTP receiver termination circuit relative to GND 1.14 1.20 1.26 V Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to GND 1.14 1.20 1.26 V Analog supply voltage for the resistor calibration circuit of the GTP transceiver bank (top or bottom) 1.14 1.20 1.26 V MGTAVCCPLL MGTAVTTRCAL Notes: 1. Each voltage listed requires the filter circuit described in Spartan-6 FPGA GTP Transceivers User Guide. 2. Voltages are specified for the temperature range of Tj = –40°C to +100°C. 3. The voltage level of MGTAVCCPLL must not exceed the voltage level of MGTAVCC +10mV. The voltage level of MGTAVCC must not exceed the voltage level of MGTAVCCPLL. Table 14: GTP Transceiver Current Supply (per Lane) Symbol IMGTAVCC Description Typ(1) GTP transceiver internal analog supply current 40.4 IMGTAVTTTX GTP transmitter termination supply current 27.4 IMGTAVTTRX GTP receiver termination supply current 13.6 IMGTAVCCPLL GTP transmitter and receiver PLL supply current 28.7 RMGTRREF Precision reference resistor for internal calibration termination Max Units mA Note 2 50.0 ± 1% tolerance mA mA mA Ω Notes: 1. Typical values are specified at nominal voltage, 25°C, with a 2.5 Gb/s line rate, with a shared PLL use mode. 2. Values for currents of other transceiver configurations and conditions can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 11 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 15: GTP Transceiver Quiescent Supply Current (per Lane)(1)(2)(3)(4) Symbol Typ(5) Description IMGTAVCCQ Quiescent MGTAVCC supply current 1.7 IMGTAVTTTXQ Quiescent MGTAVTTTX supply current 0.1 IMGTAVTTRXQ Quiescent MGTAVTTRX supply current 1.2 IMGTAVCCPLLQ Quiescent MGTAVCCPLL supply current Max Units mA mA Note 2 mA 1.0 mA Notes: 1. Device powered and unconfigured. 2. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. 3. GTP transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP transceivers. 4. Does not include power-up MGTAVTTRCAL supply current during device configuration. 5. Typical values are specified at nominal voltage, 25°C. GTP Transceiver DC Input and Output Levels Table 16 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. Figure 1 shows the singleended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage. Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 16: GTP Transceiver DC Specifications Symbol DVPPIN VIN VCMIN DVPPOUT VSEOUT VCMOUTDC RIN ROUT TOSKEW CEXT DC Parameter Conditions Min Typ Max Units Differential peak-to-peak input voltage External AC coupled 140 – 2000 mV Absolute input voltage DC coupled MGTAVTTRX = 1.2V –400 – MGTAVTTRX mV Common mode input voltage DC coupled MGTAVTTRX = 1.2V – 3/4 MGTAVTTRX – mV Differential peak-to-peak output Transmitter output swing is set voltage(1) to maximum setting – – 1000 mV Single-ended output voltage swing(1) – – 500 mV Common mode output voltage Equation based MGTAVTTTX – VSEOUT/2 mV Differential input resistance 80 100 130 Ω Differential output resistance 80 100 130 Ω – – 15 ps 75 100 200 nF Transmitter output skew Recommended external AC coupling capacitor(2) Notes: 1. The output swing and preemphasis levels are programmable using the attributes discussed in the Spartan-6 FPGA GTP Transceivers User Guide and can result in values lower than reported in this table. 2. Other values can be used as appropriate to conform to specific protocols and standards. X-Ref Target - Figure 1 +V P Single-Ended Voltage N 0 ds162_01_112009 Figure 1: Single-Ended Peak-to-Peak Voltage DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 12 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics X-Ref Target - Figure 2 +V Differential Voltage 0 –V P–N ds162_02_112009 Figure 2: Differential Peak-to-Peak Voltage Table 17 summarizes the DC specifications of the clock input of the GTP transceiver. Consult the Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 17: GTP Transceiver Clock DC Input Level Specification Symbol VIDIFF RIN CEXT DC Parameter Min Typ Max Units Differential peak-to-peak input voltage 200 800 2000 mV Differential input resistance 80 100 120 Ω Required external AC coupling capacitor – 100 – nF GTP Transceiver Switching Characteristics Consult the Spartan-6 FPGA GTP Transceivers User Guide for further information. Table 18: GTP Transceiver Performance Symbol Description Speed Grade Units -4 -3 -2 -1L 3.2 3.2 2.7 N/A Gb/s FGTPMAX Maximum GTP transceiver data rate FGTPRANGE1 GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 1 1.88 to 3.2 1.88 to 3.2 1.88 to 2.7 N/A Gb/s FGTPRANGE2 GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 2 0.94 to 1.62 0.94 to 1.62 0.94 to 1.62 N/A Gb/s FGTPRANGE3 GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 4 0.6 to 0.81 0.6 to 0.81 0.6 to 0.81 N/A Gb/s FGPLLMAX Maximum PLL frequency 1.62 1.62 1.62 N/A GHz FGPLLMIN Minimum PLL frequency 0.94 0.94 0.94 N/A GHz Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol FGTPDRPCLK Speed Grade Description GTP transceiver DCLK (DRP clock) maximum frequency DS162 (v1.9) August 23, 2010 Advance Product Specification -4 -3 -2 -1L 160 125 100 N/A Units MHz www.xilinx.com 13 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 20: GTP Transceiver Reference Clock Switching Characteristics Symbol Description All LXT Speed Grades Conditions Units Min Typ Max 60 – 160 MHz FGCLK Reference clock frequency range TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Transceiver PLL only 45 50 55 % TLOCK Clock recovery frequency acquisition time Initial PLL lock – – 1 ms TPHASE Clock recovery phase acquisition time Lock to data after PLL has locked to the reference clock – – 200 µs X-Ref Target - Figure 3 TRCLK 80% 20% TFCLK ds162_05_042109 Figure 3: Reference Clock Timing Parameters Table 21: GTP Transceiver User Clock Switching Characteristics(1) Symbol Description Conditions Speed Grade -4 -3 -2 -1L Units FTXOUT TXOUTCLK maximum frequency 320 320 270 N/A MHz FRXREC RXRECCLK maximum frequency 320 320 270 N/A MHz TRX RXUSRCLK maximum frequency 320 320 270 N/A MHz TRX2 RXUSRCLK2 maximum frequency 1 byte interface 156.25 156.25 125 N/A MHz 2 byte interface 160 160 125 N/A MHz 4 byte interface 80 80 67.5 N/A MHz 320 320 270 N/A MHz TTX TXUSRCLK maximum frequency TTX2 TXUSRCLK2 maximum frequency 1 byte interface 156.25 156.25 125 N/A MHz 2 byte interface 160 160 125 N/A MHz 4 byte interface 80 80 67.5 N/A MHz Notes: 1. Clocking must be implemented as described in the Spartan-6 FPGA GTP Transceivers User Guide. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 14 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 22: GTP Transceiver Transmitter Switching Characteristics Symbol Condition Min Typ Max Units TRTX TX Rise time Description 20%–80% – 140 – ps TFTX TX Fall time 80%–20% – 120 – ps TLLSKEW TX lane-to-lane skew(1) – – 400 ps VTXOOBVDPP Electrical idle amplitude – – 20 mV Electrical idle transition time – – 50 ns – – 0.35 UI – – 0.15 UI – – 0.33 UI – – 0.15 UI – – 0.20 UI – – 0.10 UI – – 0.20 UI – – 0.10 UI – – 0.10 UI – – 0.05 UI TTXOOBTRANSITION Jitter(2) TJ3.125 Total DJ3.125 Deterministic Jitter(2) TJ2.5 3.125 Gb/s Total Jitter(2) DJ2.5 Deterministic Jitter(2) 2.5 Gb/s Jitter(2) TJ1.62 Total DJ1.62 Deterministic Jitter(2) 1.62 Gb/s TJ1.25 Total Jitter(2) 1.25 Gb/s Jitter(2) DJ1.25 Deterministic TJ614 Total Jitter(2) DJ614 Deterministic Jitter(2) 614 Mb/s Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations. Table 23: GTP Transceiver Receiver Switching Characteristics Symbol Description TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data RXOOBVDPP OOB detect threshold peak-to-peak Units – 75 – ns – 150 mV – 0 ppm – – 150 UI –200 – 200 ppm PLL_RXDIVSEL_OUT = 1 –2000 CDR 2nd-order PLL_RXDIVSEL_OUT = 2 –2000 loop enabled PLL_RXDIVSEL_OUT = 4 –1000 – 2000 ppm – 2000 ppm – 1000 ppm RXRL Run length (CID) Modulated @ 33 KHz Internal AC capacitor bypassed CDR SJ Jitter Max 60 Receiver spread-spectrum tracking(1) Data/REFCLK PPM offset tolerance Typ –5000 RXSST RXPPMTOL Min 2nd-order loop disabled Tolerance(2) JT_SJ3.125 Sinusoidal Jitter(3) 3.125 Gb/s 0.4 – – UI JT_SJ2.5 Sinusoidal Jitter(3) 2.5 Gb/s 0.4 – – UI JT_SJ1.62 Sinusoidal Jitter(3) 1.62 Gb/s 0.5 – – UI Sinusoidal Jitter(3) 1.25 Gb/s 0.5 – – UI Sinusoidal Jitter(3) 614 Mb/s 0.5 – – UI JT_SJ1.25 JT_SJ614 SJ Jitter Tolerance with Stressed Eye(2)(5) JT_TJSE3.125 Total Jitter with stressed eye(4) 3.125 Gb/s 0.65 – – UI JT_SJSE3.125 Sinusoidal Jitter with stressed eye 3.125 Gb/s 0.1 – – UI 2.7 Gb/s 0.65 – – UI 2.7 Gb/s 0.1 – – UI eye(4) JT_TJSE2.7 Total Jitter with stressed JT_SJSE2.7 Sinusoidal Jitter with stressed eye Notes: 1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4. 2. All jitter values are based on a Bit Error Ratio of 1e–12. 3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. 4. Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ. 5. Measured using PRBS7 data pattern. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 15 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Endpoint Block for PCI Express Designs Switching Characteristics The Endpoint block for PCI Express is available in the Spartan-6 LXT family. Consult the Spartan-6 FPGA Integrated Endpoint Block for PCI Express for further information. Table 24: Maximum Performance for PCI Express Designs Symbol FPCIEUSER Speed Grade Description User clock maximum frequency -4 -3 -2 -1L 62.5 62.5 62.5 N/A Units MHz Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 17. Table 25: Interface Performances Speed Grade Description -1L Units -4 -3 -2 SDR LVDS transmitter or receiver (using IOB SDR register) 400 400 375 Mb/s DDR LVDS transmitter or receiver (using IOB ODDR2/IDDR2 register) 800 800 750 Mb/s SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8) 1080 1050 950 Mb/s DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8) 1080 1050 950 Mb/s SDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8) 1080 1050 950 Mb/s DDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8) 1080 1050 950 Mb/s Networking Applications(1) Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Block)(2) Standard Performance (standard VCCINT) DDR DDR2 DDR3 LPDDR (Mobile_DDR) Extended Performance (Requires Extended Memory Controller Block 400 400(4) 400 Mb/s 667 667(4) 625 Mb/s 667 667(4) 625 400 400(4) 400 800 800(4) 667 — Mb/s 800 800(4) 667 — Mb/s — Mb/s Mb/s VCCINT)(3) DDR2 DDR3 Notes: 1. 2. 3. 4. Refer to XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s). Refer to the Spartan-6 FPGA Memory Controller User Guide Extended Memory Controller block performance for DDR2 and DDR3 can be achieved using the extended MCB performance VCCINT range from Table 2. The -3N speed grade does not support a Memory Controller block. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 16 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Switching Characteristics All values represented in this data sheet are based on these speed specifications: v1.11 for -4, -3, and -2; and v1.04 for -1L. Switching characteristics are specified on a per-speedgrade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. The -1L speed grade refers to the lower-power Spartan-6 devices. The -3N speed grade refers to the Spartan-6 devices that do not support MCB functionality. The -3N speed grade and -3 speed grade switching characteristics are identical. Table 26 correlates the current status of each Spartan-6 device on a per speed grade basis. Table 26: Spartan-6 Device Speed Grade Designations Device Speed Grade Designations Advance Preliminary Production XC6SLX4 -3, -2, -1L Preliminary XC6SLX9 -3, -3N,-2, -1L These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. XC6SLX16 -1L -3, -3N, -2 XC6SLX25 -1L -3, -3N, -2 Production XC6SLX75 These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. XC6SLX75T All specifications are always representative of worst-case supply voltage and junction temperature conditions. XC6SLX25T XC6SLX45 -4, -3, -3N, -2 -1L XC6SLX45T XC6SLX100 -4, -3, -3N, -2 -1L XC6SLX150T -3, -3N, -2 -4, -3, -3N, -2 -1L XC6SLX100T XC6SLX150 -3, -3N, -2 -3, -3N, -2 -4, -3, -3N, -2 -1L -3, -3N, -2 -4, -3, -3N, -2 Notes: 1. Until ISE software supports the -3N speed grade option, use the -3 speed grade option and do not use the Memory Controller block. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-6 devices. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 17 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 27 lists the production released Spartan-6 family member, speed grade, and the minimum corresponding supported speed specification version and ISE® software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 27: Spartan-6 Device Production Software and Speed Specification Release(1) Device Speed Grade Designations(2) -4 XC6SLX4 N/A XC6SLX9 N/A XC6SLX16 N/A XC6SLX25 N/A -3 XC6SLX45T XC6SLX75 ISE 12.1 v1.08 ISE 12.2 v1.11(3) ISE 11.5 v1.06 ISE 12.2 v1.11(3) N/A N/A ISE 12.1 v1.08 ISE 12.2 v1.11(3) ISE 11.5 v1.07 ISE 12.2 v1.11(3) ISE 12.1 v1.08 ISE 12.2 v1.11(3) ISE 12.1 v1.08 N/A ISE 12.2 v1.11(3) N/A ISE 12.2 v1.11(3) N/A ISE 12.2 v1.11(3) N/A ISE 12.2 v1.11(3) XC6SLX100T XC6SLX150 -1L ISE 12.2 v1.11(3) XC6SLX75T XC6SLX100 -2 N/A XC6SLX25T XC6SLX45 -3N N/A ISE 12.2 v1.11(3) N/A ISE 12.2 v1.11(3) XC6SLX150T N/A Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. 2. As marked with an N/A, LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade; LX4 devices are not available with a -3N speed grade. 3. ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the Xilinx Download Center. IOB Pad Input/Output/3-State Switching Characteristics Table 28 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. DS162 (v1.9) August 23, 2010 Advance Product Specification TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 29 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). www.xilinx.com 18 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L LVDS_33 1.17 1.29 1.42 1.50 1.55 1.69 1.89 2.42 1.55 1.69 1.89 2.42 ns LVDS_25 1.01 1.13 1.26 1.39 1.65 1.79 1.99 2.47 1.65 1.79 1.99 2.47 ns BLVDS_25 1.02 1.14 1.27 1.39 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns MINI_LVDS_33 1.17 1.29 1.42 1.50 1.57 1.71 1.91 2.41 1.57 1.71 1.91 2.41 ns MINI_LVDS_25 1.01 1.13 1.26 1.39 1.65 1.79 1.99 2.47 1.65 1.79 1.99 2.47 ns LVPECL_33 1.18 1.30 1.43 1.50 N/A N/A N/A N/A N/A N/A N/A N/A ns LVPECL_25 1.02 1.14 1.27 1.39 N/A N/A N/A N/A N/A N/A N/A N/A ns RSDS_33 (point to point) 1.17 1.29 1.42 1.50 1.57 1.71 1.91 2.42 1.57 1.71 1.91 2.42 ns RSDS_25 (point to point) 1.01 1.13 1.26 1.38 1.65 1.79 1.99 2.47 1.65 1.79 1.99 2.47 ns TMDS_33 1.21 1.33 1.46 1.53 1.54 1.68 1.88 2.50 1.54 1.68 1.88 2.50 ns PPDS_33 1.17 1.29 1.42 1.50 1.57 1.71 1.91 2.43 1.57 1.71 1.91 2.43 ns PPDS_25 1.01 1.13 1.26 1.38 1.68 1.82 2.02 2.47 1.68 1.82 2.02 2.47 ns 1.32 1.39(1) 3.85 4.38(1) 3.85 4.38(1) ns 3.53 3.67 3.87 4.39(1) 3.53 3.67 3.87 4.39(1) ns 3.29 3.49 4.08 3.15 3.29 3.49 PCI33_3 1.07 1.19 3.51 3.65 3.51 3.65 PCI66_3 1.07 1.19 1.32 1.39(1) DISPLAY_PORT 1.02 1.14 1.27 1.38 3.15 4.08 ns I2C 1.33 1.45 1.58 1.64 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 ns SMBUS 1.33 1.45 1.58 1.64 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 ns SDIO 1.36 1.48 1.61 1.66 2.64 2.78 2.98 3.60 2.64 2.78 2.98 3.60 ns MOBILE_DDR 0.94 1.06 1.19 1.25 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31 ns HSTL_I 0.90 1.02 1.15 1.21 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns HSTL_II 0.91 1.03 1.16 1.22 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns HSTL_III 0.95 1.07 1.20 1.26 1.67 1.81 2.01 2.61 1.67 1.81 2.01 2.61 ns HSTL_I _18 0.94 1.06 1.19 1.25 1.77 1.91 2.11 2.73 1.77 1.91 2.11 2.73 ns HSTL_II _18 0.94 1.06 1.19 1.25 1.85 1.99 2.19 2.81 1.85 1.99 2.19 2.81 ns HSTL_III _18 0.99 1.11 1.24 1.29 1.79 1.93 2.13 2.72 1.79 1.93 2.13 2.72 ns SSTL3_I 1.58 1.70 1.83 1.98 1.83 1.97 2.17 2.72 1.83 1.97 2.17 2.72 ns SSTL3_II 1.58 1.70 1.83 1.98 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94 ns SSTL2_I 1.30 1.42 1.55 1.69 1.77 1.91 2.11 2.69 1.77 1.91 2.11 2.69 ns SSTL2_II 1.30 1.42 1.55 1.70 1.86 2.00 2.20 2.82 1.86 2.00 2.20 2.82 ns SSTL18_I 0.92 1.04 1.17 1.23 1.63 1.77 1.97 2.59 1.63 1.77 1.97 2.59 ns SSTL18_II 0.92 1.04 1.17 1.23 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns SSTL15_II 0.92 1.04 1.17 1.23 1.67 1.81 2.01 2.63 1.67 1.81 2.01 2.63 ns DIFF_HSTL_I 0.94 1.06 1.19 1.28 1.77 1.91 2.11 2.62 1.77 1.91 2.11 2.62 ns DIFF_HSTL_II 0.93 1.05 1.18 1.27 1.72 1.86 2.06 2.54 1.72 1.86 2.06 2.54 ns DIFF_HSTL_III 0.93 1.05 1.18 1.28 1.69 1.83 2.03 2.53 1.69 1.83 2.03 2.53 ns DIFF_HSTL_I_18 0.97 1.09 1.22 1.32 1.79 1.93 2.13 2.63 1.79 1.93 2.13 2.63 ns DIFF_HSTL_II_18 0.97 1.09 1.22 1.31 1.69 1.83 2.03 2.51 1.69 1.83 2.03 2.51 ns DIFF_HSTL_III_18 0.97 1.09 1.22 1.32 1.69 1.83 2.03 2.53 1.69 1.83 2.03 2.53 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 19 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L DIFF_SSTL3_I 1.18 1.30 1.43 1.50 1.81 1.95 2.15 2.64 1.81 1.95 2.15 2.64 ns DIFF_SSTL3_II 1.19 1.31 1.44 1.50 1.80 1.94 2.14 2.63 1.80 1.94 2.14 2.63 ns DIFF_SSTL2_I 1.02 1.14 1.27 1.39 1.80 1.94 2.14 2.62 1.80 1.94 2.14 2.62 ns DIFF_SSTL2_II 1.02 1.14 1.27 1.39 1.76 1.90 2.10 2.57 1.76 1.90 2.10 2.57 ns DIFF_SSTL18_I 0.97 1.09 1.22 1.33 1.72 1.86 2.06 2.56 1.72 1.86 2.06 2.56 ns DIFF_SSTL18_II 0.98 1.10 1.23 1.32 1.68 1.82 2.02 2.52 1.68 1.82 2.02 2.52 ns DIFF_SSTL15_II 0.94 1.06 1.19 1.28 1.67 1.81 2.01 2.50 1.67 1.81 2.01 2.50 ns DIFF_MOBILE_DDR 0.97 1.09 1.22 1.33 1.75 1.89 2.09 2.57 1.75 1.89 2.09 2.57 ns LVTTL, QUIETIO, 2 mA 1.35 1.47 1.60 1.64 5.39 5.53 5.73 6.37 5.39 5.53 5.73 6.37 ns LVTTL, QUIETIO, 4 mA 1.35 1.47 1.60 1.64 4.29 4.43 4.63 5.22 4.29 4.43 4.63 5.22 ns LVTTL, QUIETIO, 6 mA 1.35 1.47 1.60 1.64 3.75 3.89 4.09 4.69 3.75 3.89 4.09 4.69 ns LVTTL, QUIETIO, 8 mA 1.35 1.47 1.60 1.64 3.23 3.37 3.57 4.20 3.23 3.37 3.57 4.20 ns LVTTL, QUIETIO, 12 mA 1.35 1.47 1.60 1.64 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22 ns LVTTL, QUIETIO, 16 mA 1.35 1.47 1.60 1.64 2.94 3.08 3.28 3.92 2.94 3.08 3.28 3.92 ns LVTTL, QUIETIO, 24 mA 1.35 1.47 1.60 1.64 2.69 2.83 3.03 3.67 2.69 2.83 3.03 3.67 ns LVTTL, Slow, 2 mA 1.35 1.47 1.60 1.64 4.36 4.50 4.70 5.30 4.36 4.50 4.70 5.30 ns LVTTL, Slow, 4 mA 1.35 1.47 1.60 1.64 3.17 3.31 3.51 4.16 3.17 3.31 3.51 4.16 ns LVTTL, Slow, 6 mA 1.35 1.47 1.60 1.64 2.76 2.90 3.10 3.75 2.76 2.90 3.10 3.75 ns LVTTL, Slow, 8 mA 1.35 1.47 1.60 1.64 2.59 2.73 2.93 3.55 2.59 2.73 2.93 3.55 ns LVTTL, Slow, 12 mA 1.35 1.47 1.60 1.64 2.58 2.72 2.92 3.54 2.58 2.72 2.92 3.54 ns LVTTL, Slow, 16 mA 1.35 1.47 1.60 1.64 2.39 2.53 2.73 3.40 2.39 2.53 2.73 3.40 ns LVTTL, Slow, 24 mA 1.35 1.47 1.60 1.64 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24 ns LVTTL, Fast, 2 mA 1.35 1.47 1.60 1.64 3.78 3.92 4.12 4.74 3.78 3.92 4.12 4.74 ns LVTTL, Fast, 4 mA 1.35 1.47 1.60 1.64 2.49 2.63 2.83 3.45 2.49 2.63 2.83 3.45 ns LVTTL, Fast, 6 mA 1.35 1.47 1.60 1.64 2.44 2.58 2.78 3.40 2.44 2.58 2.78 3.40 ns LVTTL, Fast, 8 mA 1.35 1.47 1.60 1.64 2.32 2.46 2.66 3.28 2.32 2.46 2.66 3.28 ns LVTTL, Fast, 12 mA 1.35 1.47 1.60 1.64 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns LVTTL, Fast, 16 mA 1.35 1.47 1.60 1.64 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns LVTTL, Fast, 24 mA 1.35 1.47 1.60 1.64 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns LVCMOS33, QUIETIO, 2 mA 1.34 1.46 1.59 1.64 5.40 5.54 5.74 6.37 5.40 5.54 5.74 6.37 ns LVCMOS33, QUIETIO, 4 mA 1.34 1.46 1.59 1.64 4.03 4.17 4.37 5.01 4.03 4.17 4.37 5.01 ns LVCMOS33, QUIETIO, 6 mA 1.34 1.46 1.59 1.64 3.51 3.65 3.85 4.47 3.51 3.65 3.85 4.47 ns LVCMOS33, QUIETIO, 8 mA 1.34 1.46 1.59 1.64 3.37 3.51 3.71 4.33 3.37 3.51 3.71 4.33 ns LVCMOS33, QUIETIO, 12 mA 1.34 1.46 1.59 1.64 2.94 3.08 3.28 3.93 2.94 3.08 3.28 3.93 ns LVCMOS33, QUIETIO, 16 mA 1.34 1.46 1.59 1.64 2.77 2.91 3.11 3.78 2.77 2.91 3.11 3.78 ns LVCMOS33, QUIETIO, 24 mA 1.34 1.46 1.59 1.64 2.59 2.73 2.93 3.58 2.59 2.73 2.93 3.58 ns LVCMOS33, Slow, 2 mA 1.34 1.46 1.59 1.64 4.37 4.51 4.71 5.28 4.37 4.51 4.71 5.28 ns LVCMOS33, Slow, 4 mA 1.34 1.46 1.59 1.64 2.98 3.12 3.32 3.94 2.98 3.12 3.32 3.94 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 20 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L LVCMOS33, Slow, 6 mA 1.34 1.46 1.59 1.64 2.58 2.72 2.92 3.61 2.58 2.72 2.92 3.61 ns LVCMOS33, Slow, 8 mA 1.34 1.46 1.59 1.64 2.65 2.79 2.99 3.61 2.65 2.79 2.99 3.61 ns LVCMOS33, Slow, 12 mA 1.34 1.46 1.59 1.64 2.39 2.53 2.73 3.31 2.39 2.53 2.73 3.31 ns LVCMOS33, Slow, 16 mA 1.34 1.46 1.59 1.64 2.31 2.45 2.65 3.27 2.31 2.45 2.65 3.27 ns LVCMOS33, Slow, 24 mA 1.34 1.46 1.59 1.64 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24 ns LVCMOS33, Fast, 2 mA 1.34 1.46 1.59 1.64 3.76 3.90 4.10 4.70 3.76 3.90 4.10 4.70 ns LVCMOS33, Fast, 4 mA 1.34 1.46 1.59 1.64 2.48 2.62 2.82 3.44 2.48 2.62 2.82 3.44 ns LVCMOS33, Fast, 6 mA 1.34 1.46 1.59 1.64 2.32 2.46 2.66 3.28 2.32 2.46 2.66 3.28 ns LVCMOS33, Fast, 8 mA 1.34 1.46 1.59 1.64 2.07 2.21 2.41 3.03 2.07 2.21 2.41 3.03 ns LVCMOS33, Fast, 12 mA 1.34 1.46 1.59 1.64 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns LVCMOS33, Fast, 16 mA 1.34 1.46 1.59 1.64 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns LVCMOS33, Fast, 24 mA 1.34 1.46 1.59 1.64 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns LVCMOS25, QUIETIO, 2 mA 0.82 0.94 1.07 1.13 4.81 4.95 5.15 5.79 4.81 4.95 5.15 5.79 ns LVCMOS25, QUIETIO, 4 mA 0.82 0.94 1.07 1.13 3.70 3.84 4.04 4.66 3.70 3.84 4.04 4.66 ns LVCMOS25, QUIETIO, 6 mA 0.82 0.94 1.07 1.13 3.46 3.60 3.80 4.38 3.46 3.60 3.80 4.38 ns LVCMOS25, QUIETIO, 8 mA 0.82 0.94 1.07 1.13 3.20 3.34 3.54 4.12 3.20 3.34 3.54 4.12 ns LVCMOS25, QUIETIO, 12 mA 0.82 0.94 1.07 1.13 2.83 2.97 3.17 3.75 2.83 2.97 3.17 3.75 ns LVCMOS25, QUIETIO, 16 mA 0.82 0.94 1.07 1.13 2.64 2.78 2.98 3.64 2.64 2.78 2.98 3.64 ns LVCMOS25, QUIETIO, 24 mA 0.82 0.94 1.07 1.13 2.45 2.59 2.79 3.42 2.45 2.59 2.79 3.42 ns LVCMOS25, Slow, 2 mA 0.82 0.94 1.07 1.13 3.78 3.92 4.12 4.76 3.78 3.92 4.12 4.76 ns LVCMOS25, Slow, 4 mA 0.82 0.94 1.07 1.13 2.79 2.93 3.13 3.73 2.79 2.93 3.13 3.73 ns LVCMOS25, Slow, 6 mA 0.82 0.94 1.07 1.13 2.73 2.87 3.07 3.66 2.73 2.87 3.07 3.66 ns LVCMOS25, Slow, 8 mA 0.82 0.94 1.07 1.13 2.48 2.62 2.82 3.42 2.48 2.62 2.82 3.42 ns LVCMOS25, Slow, 12 mA 0.82 0.94 1.07 1.13 2.01 2.15 2.35 2.95 2.01 2.15 2.35 2.95 ns LVCMOS25, Slow, 16 mA 0.82 0.94 1.07 1.13 2.01 2.15 2.35 2.95 2.01 2.15 2.35 2.95 ns LVCMOS25, Slow, 24 mA 0.82 0.94 1.07 1.13 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94 ns LVCMOS25, Fast, 2 mA 0.82 0.94 1.07 1.13 3.35 3.49 3.69 4.31 3.35 3.49 3.69 4.31 ns LVCMOS25, Fast, 4 mA 0.82 0.94 1.07 1.13 2.25 2.39 2.59 3.22 2.25 2.39 2.59 3.22 ns LVCMOS25, Fast, 6 mA 0.82 0.94 1.07 1.13 2.09 2.23 2.43 3.05 2.09 2.23 2.43 3.05 ns LVCMOS25, Fast, 8 mA 0.82 0.94 1.07 1.13 2.02 2.16 2.36 2.98 2.02 2.16 2.36 2.98 ns LVCMOS25, Fast, 12 mA 0.82 0.94 1.07 1.13 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns LVCMOS25, Fast, 16 mA 0.82 0.94 1.07 1.13 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns LVCMOS25, Fast, 24 mA 0.82 0.94 1.07 1.13 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns LVCMOS18, QUIETIO, 2 mA 1.18 1.30 1.43 1.86 5.92 6.06 6.26 6.80 5.92 6.06 6.26 6.80 ns LVCMOS18, QUIETIO, 4 mA 1.18 1.30 1.43 1.86 4.74 4.88 5.08 5.63 4.74 4.88 5.08 5.63 ns LVCMOS18, QUIETIO, 6 mA 1.18 1.30 1.43 1.86 4.05 4.19 4.39 4.96 4.05 4.19 4.39 4.96 ns LVCMOS18, QUIETIO, 8 mA 1.18 1.30 1.43 1.86 3.71 3.85 4.05 4.63 3.71 3.85 4.05 4.63 ns LVCMOS18, QUIETIO, 12 mA 1.18 1.30 1.43 1.86 3.35 3.49 3.69 4.27 3.35 3.49 3.69 4.27 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 21 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L LVCMOS18, QUIETIO, 16 mA 1.18 1.30 1.43 1.86 3.20 3.34 3.54 4.14 3.20 3.34 3.54 4.14 ns LVCMOS18, QUIETIO, 24 mA 1.18 1.30 1.43 1.86 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98 ns LVCMOS18, Slow, 2 mA 1.18 1.30 1.43 1.86 4.62 4.76 4.96 5.54 4.62 4.76 4.96 5.54 ns LVCMOS18, Slow, 4 mA 1.18 1.30 1.43 1.86 3.69 3.83 4.03 4.60 3.69 3.83 4.03 4.60 ns LVCMOS18, Slow, 6 mA 1.18 1.30 1.43 1.86 3.00 3.14 3.34 3.94 3.00 3.14 3.34 3.94 ns LVCMOS18, Slow, 8 mA 1.18 1.30 1.43 1.86 2.19 2.33 2.53 3.17 2.19 2.33 2.53 3.17 ns LVCMOS18, Slow, 12 mA 1.18 1.30 1.43 1.86 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18, Slow, 16 mA 1.18 1.30 1.43 1.86 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18, Slow, 24 mA 1.18 1.30 1.43 1.86 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18, Fast, 2 mA 1.18 1.30 1.43 1.86 3.59 3.73 3.93 4.53 3.59 3.73 3.93 4.53 ns LVCMOS18, Fast, 4 mA 1.18 1.30 1.43 1.86 2.39 2.53 2.73 3.35 2.39 2.53 2.73 3.35 ns LVCMOS18, Fast, 6 mA 1.18 1.30 1.43 1.86 1.88 2.02 2.22 2.84 1.88 2.02 2.22 2.84 ns LVCMOS18, Fast, 8 mA 1.18 1.30 1.43 1.86 1.81 1.95 2.15 2.77 1.81 1.95 2.15 2.77 ns LVCMOS18, Fast, 12 mA 1.18 1.30 1.43 1.86 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns LVCMOS18, Fast, 16 mA 1.18 1.30 1.43 1.86 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns LVCMOS18, Fast, 24 mA 1.18 1.30 1.43 1.86 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns LVCMOS18_JEDEC, QUIETIO, 2 mA 0.94 1.06 1.19 1.23 5.91 6.05 6.25 6.79 5.91 6.05 6.25 6.79 ns LVCMOS18_JEDEC, QUIETIO, 4 mA 0.94 1.06 1.19 1.23 4.75 4.89 5.09 5.64 4.75 4.89 5.09 5.64 ns LVCMOS18_JEDEC, QUIETIO, 6 mA 0.94 1.06 1.19 1.23 4.04 4.18 4.38 4.96 4.04 4.18 4.38 4.96 ns LVCMOS18_JEDEC, QUIETIO, 8 mA 0.94 1.06 1.19 1.23 3.71 3.85 4.05 4.62 3.71 3.85 4.05 4.62 ns LVCMOS18_JEDEC, QUIETIO, 12 mA 0.94 1.06 1.19 1.23 3.35 3.49 3.69 4.28 3.35 3.49 3.69 4.28 ns LVCMOS18_JEDEC, QUIETIO, 16 mA 0.94 1.06 1.19 1.23 3.20 3.34 3.54 4.13 3.20 3.34 3.54 4.13 ns LVCMOS18_JEDEC, QUIETIO, 24 mA 0.94 1.06 1.19 1.23 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98 ns LVCMOS18_JEDEC, Slow, 2 mA 0.94 1.06 1.19 1.23 4.59 4.73 4.93 5.54 4.59 4.73 4.93 5.54 ns LVCMOS18_JEDEC, Slow, 4 mA 0.94 1.06 1.19 1.23 3.69 3.83 4.03 4.60 3.69 3.83 4.03 4.60 ns LVCMOS18_JEDEC, Slow, 6 mA 0.94 1.06 1.19 1.23 3.00 3.14 3.34 3.94 3.00 3.14 3.34 3.94 ns LVCMOS18_JEDEC, Slow, 8 mA 0.94 1.06 1.19 1.23 2.19 2.33 2.53 3.18 2.19 2.33 2.53 3.18 ns LVCMOS18_JEDEC, Slow, 12 mA 0.94 1.06 1.19 1.23 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18_JEDEC, Slow, 16 mA 0.94 1.06 1.19 1.23 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18_JEDEC, Slow, 24 mA 0.94 1.06 1.19 1.23 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns LVCMOS18_JEDEC, Fast, 2 mA 0.94 1.06 1.19 1.23 3.57 3.71 3.91 4.52 3.57 3.71 3.91 4.52 ns LVCMOS18_JEDEC, Fast, 4 mA 0.94 1.06 1.19 1.23 2.39 2.53 2.73 3.35 2.39 2.53 2.73 3.35 ns LVCMOS18_JEDEC, Fast, 6 mA 0.94 1.06 1.19 1.23 1.88 2.02 2.22 2.84 1.88 2.02 2.22 2.84 ns LVCMOS18_JEDEC, Fast, 8 mA 0.94 1.06 1.19 1.23 1.80 1.94 2.14 2.76 1.80 1.94 2.14 2.76 ns LVCMOS18_JEDEC, Fast, 12 mA 0.94 1.06 1.19 1.23 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns LVCMOS18_JEDEC, Fast, 16 mA 0.94 1.06 1.19 1.23 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns LVCMOS18_JEDEC, Fast, 24 mA 0.94 1.06 1.19 1.23 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns LVCMOS15, QUIETIO, 2 mA 0.98 1.10 1.23 1.61 5.47 5.61 5.81 6.38 5.47 5.61 5.81 6.38 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 22 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L LVCMOS15, QUIETIO, 4 mA 0.98 1.10 1.23 1.61 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51 ns LVCMOS15, QUIETIO, 6 mA 0.98 1.10 1.23 1.61 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97 ns LVCMOS15, QUIETIO, 8 mA 0.98 1.10 1.23 1.61 3.91 4.05 4.25 4.81 3.91 4.05 4.25 4.81 ns LVCMOS15, QUIETIO, 12 mA 0.98 1.10 1.23 1.61 3.53 3.67 3.87 4.51 3.53 3.67 3.87 4.51 ns LVCMOS15, QUIETIO, 16 mA 0.98 1.10 1.23 1.61 3.32 3.46 3.66 4.31 3.32 3.46 3.66 4.31 ns LVCMOS15, Slow, 2 mA 0.98 1.10 1.23 1.61 4.18 4.32 4.52 5.11 4.18 4.32 4.52 5.11 ns LVCMOS15, Slow, 4 mA 0.98 1.10 1.23 1.61 3.42 3.56 3.76 4.34 3.42 3.56 3.76 4.34 ns LVCMOS15, Slow, 6 mA 0.98 1.10 1.23 1.61 2.29 2.43 2.63 3.24 2.29 2.43 2.63 3.24 ns LVCMOS15, Slow, 8 mA 0.98 1.10 1.23 1.61 2.30 2.44 2.64 3.25 2.30 2.44 2.64 3.25 ns LVCMOS15, Slow, 12 mA 0.98 1.10 1.23 1.61 2.03 2.17 2.37 2.99 2.03 2.17 2.37 2.99 ns LVCMOS15, Slow, 16 mA 0.98 1.10 1.23 1.61 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns LVCMOS15, Fast, 2 mA 0.98 1.10 1.23 1.61 3.29 3.43 3.63 4.24 3.29 3.43 3.63 4.24 ns LVCMOS15, Fast, 4 mA 0.98 1.10 1.23 1.61 2.27 2.41 2.61 3.22 2.27 2.41 2.61 3.22 ns LVCMOS15, Fast, 6 mA 0.98 1.10 1.23 1.61 1.78 1.92 2.12 2.74 1.78 1.92 2.12 2.74 ns LVCMOS15, Fast, 8 mA 0.98 1.10 1.23 1.61 1.73 1.87 2.07 2.69 1.73 1.87 2.07 2.69 ns LVCMOS15, Fast, 12 mA 0.98 1.10 1.23 1.61 1.73 1.87 2.07 2.64 1.73 1.87 2.07 2.64 ns LVCMOS15, Fast, 16 mA 0.98 1.10 1.23 1.61 1.73 1.87 2.07 2.64 1.73 1.87 2.07 2.64 ns LVCMOS15_JEDEC, QUIETIO, 2 mA 1.03 1.15 1.28 1.31 5.49 5.63 5.83 6.37 5.49 5.63 5.83 6.37 ns LVCMOS15_JEDEC, QUIETIO, 4 mA 1.03 1.15 1.28 1.31 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51 ns LVCMOS15_JEDEC, QUIETIO, 6 mA 1.03 1.15 1.28 1.31 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97 ns LVCMOS15_JEDEC, QUIETIO, 8 mA 1.03 1.15 1.28 1.31 3.92 4.06 4.26 4.81 3.92 4.06 4.26 4.81 ns LVCMOS15_JEDEC, QUIETIO, 12 mA 1.03 1.15 1.28 1.31 3.54 3.68 3.88 4.51 3.54 3.68 3.88 4.51 ns LVCMOS15_JEDEC, QUIETIO, 16 mA 1.03 1.15 1.28 1.31 3.33 3.47 3.67 4.31 3.33 3.47 3.67 4.31 ns LVCMOS15_JEDEC, Slow, 2 mA 1.03 1.15 1.28 1.31 4.18 4.32 4.52 5.13 4.18 4.32 4.52 5.13 ns LVCMOS15_JEDEC, Slow, 4 mA 1.03 1.15 1.28 1.31 3.42 3.56 3.76 4.35 3.42 3.56 3.76 4.35 ns LVCMOS15_JEDEC, Slow, 6 mA 1.03 1.15 1.28 1.31 2.29 2.43 2.63 3.25 2.29 2.43 2.63 3.25 ns LVCMOS15_JEDEC, Slow, 8 mA 1.03 1.15 1.28 1.31 2.30 2.44 2.64 3.26 2.30 2.44 2.64 3.26 ns LVCMOS15_JEDEC, Slow, 12 mA 1.03 1.15 1.28 1.31 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns LVCMOS15_JEDEC, Slow, 16 mA 1.03 1.15 1.28 1.31 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns LVCMOS15_JEDEC, Fast, 2 mA 1.03 1.15 1.28 1.31 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22 ns LVCMOS15_JEDEC, Fast, 4 mA 1.03 1.15 1.28 1.31 2.27 2.41 2.61 3.23 2.27 2.41 2.61 3.23 ns LVCMOS15_JEDEC, Fast, 6 mA 1.03 1.15 1.28 1.31 1.78 1.92 2.12 2.74 1.78 1.92 2.12 2.74 ns LVCMOS15_JEDEC, Fast, 8 mA 1.03 1.15 1.28 1.31 1.73 1.87 2.07 2.69 1.73 1.87 2.07 2.69 ns LVCMOS15_JEDEC, Fast, 12 mA 1.03 1.15 1.28 1.31 1.73 1.87 2.07 2.63 1.73 1.87 2.07 2.63 ns LVCMOS15_JEDEC, Fast, 16 mA 1.03 1.15 1.28 1.31 1.73 1.87 2.07 2.63 1.73 1.87 2.07 2.63 ns LVCMOS12, QUIETIO, 2 mA 0.91 1.03 1.16 1.33 6.40 6.54 6.74 7.30 6.40 6.54 6.74 7.30 ns LVCMOS12, QUIETIO, 4 mA 0.91 1.03 1.16 1.33 4.98 5.12 5.32 5.90 4.98 5.12 5.32 5.90 ns LVCMOS12, QUIETIO, 6 mA 0.91 1.03 1.16 1.33 4.65 4.79 4.99 5.55 4.65 4.79 4.99 5.55 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 23 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -4 -3 -2 -1L -4 -3 -2 -1L -4 -3 -2 -1L LVCMOS12, QUIETIO, 8 mA 0.91 1.03 1.16 1.33 4.23 4.37 4.57 5.21 4.23 4.37 4.57 5.21 ns LVCMOS12, QUIETIO, 12 mA 0.91 1.03 1.16 1.33 3.98 4.12 4.32 4.94 3.98 4.12 4.32 4.94 ns LVCMOS12, Slow, 2 mA 0.91 1.03 1.16 1.33 4.98 5.12 5.32 5.91 4.98 5.12 5.32 5.91 ns LVCMOS12, Slow, 4 mA 0.91 1.03 1.16 1.33 2.84 2.98 3.18 3.81 2.84 2.98 3.18 3.81 ns LVCMOS12, Slow, 6 mA 0.91 1.03 1.16 1.33 2.77 2.91 3.11 3.72 2.77 2.91 3.11 3.72 ns LVCMOS12, Slow, 8 mA 0.91 1.03 1.16 1.33 2.34 2.48 2.68 3.31 2.34 2.48 2.68 3.31 ns LVCMOS12, Slow, 12 mA 0.91 1.03 1.16 1.33 2.08 2.22 2.42 3.06 2.08 2.22 2.42 3.06 ns LVCMOS12, Fast, 2 mA 0.91 1.03 1.16 1.33 3.46 3.60 3.80 4.44 3.46 3.60 3.80 4.44 ns LVCMOS12, Fast, 4 mA 0.91 1.03 1.16 1.33 2.35 2.49 2.69 3.30 2.35 2.49 2.69 3.30 ns LVCMOS12, Fast, 6 mA 0.91 1.03 1.16 1.33 1.79 1.93 2.13 2.75 1.79 1.93 2.13 2.75 ns LVCMOS12, Fast, 8 mA 0.91 1.03 1.16 1.33 1.68 1.82 2.02 2.64 1.68 1.82 2.02 2.64 ns LVCMOS12, Fast, 12 mA 0.91 1.03 1.16 1.33 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns LVCMOS12_JEDEC, QUIETIO, 2 mA 1.50 1.62 1.75 1.70 6.39 6.53 6.73 7.31 6.39 6.53 6.73 7.31 ns LVCMOS12_JEDEC, QUIETIO, 4 mA 1.50 1.62 1.75 1.70 4.98 5.12 5.32 5.88 4.98 5.12 5.32 5.88 ns LVCMOS12_JEDEC, QUIETIO, 6 mA 1.50 1.62 1.75 1.70 4.67 4.81 5.01 5.54 4.67 4.81 5.01 5.54 ns LVCMOS12_JEDEC, QUIETIO, 8 mA 1.50 1.62 1.75 1.70 4.23 4.37 4.57 5.22 4.23 4.37 4.57 5.22 ns LVCMOS12_JEDEC, QUIETIO, 12 mA 1.50 1.62 1.75 1.70 3.99 4.13 4.33 4.94 3.99 4.13 4.33 4.94 ns LVCMOS12_JEDEC, Slow, 2 mA 1.50 1.62 1.75 1.70 5.00 5.14 5.34 5.90 5.00 5.14 5.34 5.90 ns LVCMOS12_JEDEC, Slow, 4 mA 1.50 1.62 1.75 1.70 2.85 2.99 3.19 3.80 2.85 2.99 3.19 3.80 ns LVCMOS12_JEDEC, Slow, 6 mA 1.50 1.62 1.75 1.70 2.76 2.90 3.10 3.72 2.76 2.90 3.10 3.72 ns LVCMOS12_JEDEC, Slow, 8 mA 1.50 1.62 1.75 1.70 2.35 2.49 2.69 3.30 2.35 2.49 2.69 3.30 ns LVCMOS12_JEDEC, Slow, 12 mA 1.50 1.62 1.75 1.70 2.09 2.23 2.43 3.05 2.09 2.23 2.43 3.05 ns LVCMOS12_JEDEC, Fast, 2 mA 1.50 1.62 1.75 1.70 3.46 3.60 3.80 4.42 3.46 3.60 3.80 4.42 ns LVCMOS12_JEDEC, Fast, 4 mA 1.50 1.62 1.75 1.70 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31 ns LVCMOS12_JEDEC, Fast, 6 mA 1.50 1.62 1.75 1.70 1.79 1.93 2.13 2.76 1.79 1.93 2.13 2.76 ns LVCMOS12_JEDEC, Fast, 8 mA 1.50 1.62 1.75 1.70 1.69 1.83 2.03 2.65 1.69 1.83 2.03 2.65 ns LVCMOS12_JEDEC, Fast, 12 mA 1.50 1.62 1.75 1.70 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns Notes: 1. Devices with a -1L speed grade do not support Xilinx PCI IP. Table 29: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Symbol TIOTPHZ Speed Grade Description T input to Pad high-impedance DS162 (v1.9) August 23, 2010 Advance Product Specification -4 -3 -2 -1L 1.39 1.59 1.59 1.91 Units ns www.xilinx.com 24 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description I/O Standard Attribute VL(1) VH(1) VMEAS(3)(4) VREF(2)(4) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL 0 3.0 1.4 – LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 0 3.3 1.65 – LVCMOS, 2.5V LVCMOS25 0 2.5 1.25 – LVCMOS, 1.8V LVCMOS18 0 1.8 0.9 – LVCMOS, 1.5V LVCMOS15 0 1.5 0.75 – LVCMOS, 1.2V LVCMOS12 0 1.2 0.6 – PCI (Peripheral Component Interface), 33 MHz and 66 MHz, 3.3V PCI33_3, PCI66_3 HSTL (High-Speed Transceiver Logic), Class I & II HSTL_I, HSTL_II VREF – 0.5 VREF + 0.5 VREF 0.75 HSTL, Class III HSTL_III VREF – 0.5 VREF + 0.5 VREF 0.90 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF – 0.5 VREF + 0.5 VREF 0.90 HSTL, Class III 1.8V HSTL_III_18 VREF – 0.5 VREF + 0.5 VREF 1.1 SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL3_I, SSTL3_II VREF – 0.75 VREF + 0.75 VREF 1.5 SSTL, Class I & II, 2.5V SSTL2_I, SSTL2_II VREF – 0.75 VREF + 0.75 VREF 1.25 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF – 0.5 VREF + 0.5 VREF 0.90 SSTL, Class II, 1.5V SSTL15_II VREF – 0.2 VREF + 0.2 VREF 0.75 1.25 – 0.125 1.25 + 0.125 0(5) – 1.2 – 0.3 1.2 – 0.3 0(5) – 1.3 – 0.125 1.3 + 0.125 0(5) – 1.2 – 0.125 1.2 + 0.125 0(5) – LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V LVDS_25, LVDS_33 LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V & 3.3V LVPECL_25, LVPECL_33 BLVDS (Bus LVDS), 2.5V BLVDS_25 Per PCI Specification – Mini-LVDS, 2.5V & 3.3V MINI_LVDS_25, MINI_LVDS_33 RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33 1.2 – 0.1 1.2 + 0.1 0(5) – TMDS (Transition Minimized Differential Signaling), 3.3V TMDS_33 3.0 – 0.1 3.0 + 0.1 0(5) – PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V PPDS_25, PPDS_33 1.25 – 0.1 1.25 + 0.1 0(5) – Notes: 1. Input waveform switches between VL and VH. 2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 3. Input voltage level from which measurement starts. 4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4. 5. The value given is the differential input voltage. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 25 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Output Delay Measurements X-Ref Target - Figure 5 FPGA Output Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 4 and Figure 5. + RREF VMEAS CREF – ds162_07_011309 X-Ref Target - Figure 4 Figure 5: Differential Test Setup VREF Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF , RREF , CREF , and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: RREF FPGA Output VMEAS (voltage level when taking delay measurement) 1. Simulate the output driver of choice into the generalized test setup, using values from Table 31. CREF (probe capacitance) 2. Record the time to VMEAS . ds162_06_011309 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. Figure 4: Single-Ended Test Setup 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. Table 31: Output Delay Measurement Methodology I/O Standard Attribute Description RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0 LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 1M 0 1.65 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.2V LVCMOS12 1M 0 0.75 0 PCI (Peripheral Component Interface) 33 MHz and 66 MHz, 3.3V PCI33_3, PCI66_3 (rising edge) 25 10 (2) 0.94 0 PCI33_3, PCI66_3 (falling edge) 25 10 (2) 2.03 3.3 HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 VREF 0.75 HSTL, Class II HSTL_II 25 0 VREF 0.75 HSTL, Class III HSTL_III 50 0 0.9 1.5 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9 HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8 SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 VREF 0.9 SSTL, Class II, 1.8V SSTL18_II 25 0 VREF 0.9 SSTL, Class I, 2.5V SSTL2_I 50 0 VREF 1.25 DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 26 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 31: Output Delay Measurement Methodology (Cont’d) I/O Standard Attribute Description RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) SSTL, Class II, 2.5V SSTL2_II 25 0 VREF 1.25 SSTL, Class II, 1.5V SSTL15_II 25 0 VREF 0.75 0 0(3) 1.2 0 0(3) 0 0 0(3) 1.2 0 0(3) 1.2 LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V BLVDS (Bus LVDS), 2.5V Mini-LVDS, 2.5V & 3.3V LVDS_25, LVDS_33 BLVDS_25 MINI_LVDS_25, MINI_LVDS_33 RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33 100 100 100 100 TMDS (Transition Minimized Differential Signaling), 3.3V TMDS_33 100 0 0(3) PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V PPDS_25, PPDS_33 100 0 0(3) – Notes: 1. CREF is the capacitance of the probe, nominally 0 pF. 2. Per PCI specifications. 3. The value given is the differential output voltage. Simultaneously Switching Outputs Due to lead inductance, a given package supports a limited number of simultaneous switching outputs (SSOs) when using fast, high-drive outputs. Table 32 and Table 33 provide guidelines for the recommended maximum allowable number of SSOs. These guidelines describe the maximum number of user I/O pins of an output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise for that particular signal standard. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of GND and power bounce. For each device/package combination, Table 32 provides the number of equivalent VCCO/GND pairs per bank. For each output signal standard and drive strength, Table 33 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines are categorized by package style, slew rate, and output drive current. The number of SSOs are also specified by I/O bank. Multiply the appropriate numbers from each table to calculate the maximum number of SSOs allowed within an I/O bank. The guidelines assume that all pins within a bank use the same I/O standard. Exceeding these SSO guidelines can result in increased power or GND bounce, degraded signal integrity, or increased system jitter. For a given I/O standard, if the SSO limit per pair in Table 33 is greater than the maximum I/O per pair in Table 32, then there is no SSO limit for the exclusive use of that I/O standard. The recommended maximum SSO values assume that the FPGA is soldered on a printed circuit board and that the board uses sound design practices. Due to the additional lead inductance introduced by the socket, the SSO values do not apply for FPGAs mounted in sockets. The SSO values assume that the VCCAUX is powered at 3.3V. Setting VCCAUX to 2.5V provides better SSO characteristics. For more detail, see the Spartan-6 FPGA SelectIO Resources User Guide. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 27 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 32: Spartan-6 FPGA VCCO/GND Pairs per Bank Package Devices TQG144 LX CPG196 LX CSG225 LX FT(G)256 LX LX CSG324 LXT LX CSG484 LXT LX FG(G)484 LXT LX45 FG(G)676 LX75, LX100, LX150 LXT LX FG(G)900 LXT DS162 (v1.9) August 23, 2010 Advance Product Specification Description Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 VCCO/GND Pairs 3 3 2 3 N/A N/A Maximum I/O per Pair 8 8 13 8 N/A N/A VCCO/GND Pairs 4 6 4 6 N/A N/A Maximum I/O per Pair 6 4 7 4 N/A N/A VCCO/GND Pairs 4 4 4 4 N/A N/A Maximum I/O per Pair 10 10 9 10 N/A N/A VCCO/GND Pairs 5 6 4 5 N/A N/A Maximum I/O per Pair 8 9 9 10 N/A N/A VCCO/GND Pairs 6 6 6 6 N/A N/A Maximum I/O per Pair 10 9 10 9 N/A N/A VCCO/GND Pairs 4 6 6 6 N/A N/A Maximum I/O per Pair 4 9 10 9 N/A N/A VCCO/GND Pairs 8 13 8 13 N/A N/A Maximum I/O per Pair 7 8 7 8 N/A N/A VCCO/GND Pairs 7 12 8 13 N/A N/A Maximum I/O per Pair 5 8 6 8 N/A N/A VCCO/GND Pairs 10 10 11 11 N/A N/A Maximum I/O per Pair 6 8 9 8 N/A N/A VCCO/GND Pairs 6 10 11 10 N/A N/A Maximum I/O per Pair 7 8 7 8 N/A N/A VCCO/GND Pairs 12 15 10 16 N/A N/A Maximum I/O per Pair 3 7 8 7 N/A N/A VCCO/GND Pairs 12 9 10 10 6 6 Maximum I/O per Pair 9 10 9 9 8 9 VCCO/GND Pairs 10 8 10 8 7 7 Maximum I/O per Pair 8 7 8 8 7 7 VCCO/GND Pairs 17 14 17 14 7 8 Maximum I/O per Pair 7 6 7 8 7 6 VCCO/GND Pairs 15 14 13 14 7 8 Maximum I/O per Pair 7 6 8 8 7 6 www.xilinx.com 28 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 1.2V LVCMOS12, LVCMOS12_JEDEC 6 8 12 DS162 (v1.9) August 23, 2010 Advance Product Specification Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 30 (1) 35 30 35 Slow 51 55 51 52 QuietIO 71 58 71 70 Fast 17 17 17 19 Slow 23 25 23 22 QuietIO 35 32 35 32 Fast 13 15 13 14 Slow 19 20 19 17 QuietIO 26 24 26 24 Fast N/A 12 N/A 12 Slow N/A 15 N/A 13 QuietIO N/A 20 N/A 19 Fast N/A 5 N/A 4 Slow N/A 8 N/A 5 QuietIO N/A 11 N/A 10 www.xilinx.com 29 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 6 LVCMOS15, LVCMOS15_JEDEC 8 1.5V 12 16 Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 33 40 33 41 Slow 57 62 57 56 QuietIO 70 67 70 66 Fast 19 21 19 21 Slow 30 30 30 24 QuietIO 38 33 38 30 Fast 14 16 14 16 Slow 18 19 18 17 QuietIO 27 24 27 21 Fast 11 13 11 12 Slow 16 16 16 14 QuietIO 23 20 23 17 Fast N/A 5 N/A 4 Slow N/A 8 N/A 5 QuietIO N/A 10 N/A 9 Fast N/A 5 N/A 4 Slow N/A 8 N/A 8 QuietIO N/A 10 N/A 9 HSTL_I 9 10 9 10 HSTL_II N/A 5 N/A 6 HSTL_III 7 9 7 9 DIFF_HSTL_I 27 30 27 30 DIFF_HSTL_II N/A 15 N/A 18 DIFF_HSTL_III 21 27 21 27 N/A 5 N/A 4 N/A 15 N/A 12 SSTL_15_II (3) DIFF_SSTL_15_II (3) DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 30 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 6 LVCMOS18, LVCMOS18_JEDEC 8 12 Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 39 46 39 47 Slow 65 75 65 74 QuietIO 80 80 80 85 Fast 22 25 22 25 Slow 38 36 38 29 QuietIO 45 40 45 35 Fast 16 18 16 17 Slow 27 25 27 19 QuietIO 30 28 30 23 Fast 13 15 13 14 Slow 16 18 16 16 QuietIO 25 22 25 18 Fast 5 7 5 5 Slow 7 8 7 6 QuietIO 11 10 11 8 Fast 4 5 4 4 Slow 7 8 7 5 QuietIO 11 10 11 8 Fast N/A 5 N/A 3 Slow N/A 8 N/A 8 QuietIO N/A 10 N/A 8 HSTL_I_18 9 10 9 9 HSTL_II_18 N/A 5 N/A 6 HSTL_III_18 9 10 9 11 DIFF_HSTL_I_18 27 30 27 27 DIFF_HSTL_II_18 N/A 15 N/A 18 DIFF_HSTL_III_18 27 30 27 33 12 14 12 14 36 42 36 42 1.8V 16 24 MOBILE_DDR (3) DIFF_MOBILE_DDR SSTL_18_I (3) (3) SSTL_18_II (3) DIFF_SSTL_18_I DIFF_SSTL_18_II (3) (3) DS162 (v1.9) August 23, 2010 Advance Product Specification 9 10 9 10 N/A 5 N/A 4 27 30 27 30 N/A 15 N/A 12 www.xilinx.com 31 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 6 LVCMOS25 8 2.5V 12 16 Slew SSTL_2_I Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 38 43 38 43 Slow 46 52 46 48 QuietIO 57 64 57 59 Fast 21 24 21 23 Slow 26 31 26 27 QuietIO 33 32 33 30 Fast 15 17 15 16 Slow 19 22 19 19 QuietIO 25 23 25 19 Fast 12 15 12 14 Slow 15 18 15 16 QuietIO 21 19 21 16 Fast 1 3 1 1 Slow 2 7 2 4 QuietIO 3 8 3 8 Fast 1 3 1 1 Slow 3 7 3 3 4 9 4 8 Fast N/A 3 N/A 1 Slow N/A 5 N/A 2 QuietIO N/A 8 N/A 6 (3) SSTL_2_II (3) DIFF_SSTL_2_I DIFF_SSTL_2_II (3) (3) DS162 (v1.9) August 23, 2010 Advance Product Specification All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 QuietIO 24 All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 10 11 10 11 N/A 7 N/A 7 30 33 30 33 N/A 21 N/A 24 www.xilinx.com 32 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 6 3.3V LVCMOS33 8 12 16 24 DS162 (v1.9) August 23, 2010 Advance Product Specification Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 42 46 42 44 Slow 50 55 50 49 QuietIO 60 68 60 60 Fast 21 27 21 25 Slow 32 37 32 32 QuietIO 39 42 39 37 Fast 14 19 14 17 Slow 19 25 19 22 QuietIO 29 30 29 25 Fast 11 15 11 14 Slow 15 20 15 18 QuietIO 25 24 25 20 Fast 1 3 1 1 Slow 2 5 2 2 QuietIO 4 9 4 7 Fast 1 2 1 1 Slow 1 5 1 1 QuietIO 3 10 3 8 Fast 1 2 1 1 Slow 2 5 2 1 QuietIO 7 9 7 7 www.xilinx.com 33 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive 2 4 6 LVTTL 8 12 Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 Fast 53 65 53 62 Slow 70 80 70 73 QuietIO 79 89 79 91 Fast 23 30 23 27 Slow 34 41 34 37 QuietIO 44 49 44 46 Fast 16 21 16 20 Slow 21 28 21 25 QuietIO 34 39 34 34 Fast 12 16 12 15 Slow 16 22 16 19 QuietIO 27 28 27 24 Fast 1 3 1 1 Slow 2 5 2 4 QuietIO 2 10 2 8 Fast 1 3 1 1 Slow 1 7 1 2 QuietIO 3 11 3 8 Fast 1 2 1 1 Slow 2 5 2 2 QuietIO 8 9 8 8 PCI33_3 18 19 18 19 PCI66_3 18 19 18 19 SSTL_3_I 5 8 5 8 SSTL_3_II 3 5 3 3 3.3V 16 24 DIFF_SSTL_3_I 15 24 15 24 DIFF_SSTL_3_II 9 15 9 9 SDIO 17 18 17 15 DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 34 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont’d) SSO Limit per VCCO/GND Pair VCCO Various I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2 Bank 1/3 Bank 0/2 Bank 1/3/4/5 LVDS_33 16 N/A 16 N/A LVDS_25 20 N/A 20 N/A BLVDS_25 20 48 20 20 MINI_LVDS_33 13 N/A 13 N/A MINI_LVDS_25 18 N/A 18 N/A RSDS_33 12 N/A 12 N/A RSDS_25 15 N/A 15 N/A TMDS_33 83 N/A 83 N/A PPDS_33 12 N/A 12 N/A PPDS_25 16 N/A 16 N/A DISPLAY_PORT 42 40 42 30 I2C 47 55 47 42 SMBUS 44 52 44 40 Notes: 1. 2. 3. SSO limits greater than the number of I/O per VCCO/GND pair (Table 32) indicate No Limit for the given I/O standard. They are provided in this table to calculate limits when using multiple I/O standards in a bank. Not available (N/A) indicates that the I/O standard is not available in the given bank. When used with the MCB, these signals are exempt from SSO analysis due to the known activity of the MCB switching patterns. SSO performance is validated for all MCB instances. MCB outputs can, in some cases, exceed the SSO limits. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 35 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 34: ILOGIC2 Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units Setup/Hold TICE0CK/TICKCE0 CE0 pin Setup/Hold with respect to CLK 0.56 –0.30 0.56 –0.25 0.79 –0.22 1.24 –0.55 ns TISRCK/TICKSR SR pin Setup/Hold with respect to CLK 0.74 –0.23 0.74 –0.22 0.98 –0.20 1.35 –0.49 ns TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay 1.19 –0.83 1.36 –0.83 1.73 –0.83 1.97 –1.09 ns TIDOCKD/TIOCKDD DDLY pin Setup/Hold with respect to CLK (using IODELAY2) 0.31 0.00 0.47 0.00 0.54 0.00 0.64 –0.16 ns TIDI D pin to O pin propagation delay, no Delay 0.95 1.28 1.53 1.97 ns TIDID DDLY pin to O pin propagation delay (using IODELAY2) 0.23 0.39 0.44 0.64 ns TIDLO D pin to Q pin using flip-flop as a latch without Delay 1.56 1.86 2.39 3.22 ns TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2) 0.68 0.97 1.20 1.89 ns TICKQ CLK to Q outputs 1.03 1.24 1.43 1.66 ns TRQ_ILOGIC2 SR pin to Q outputs 1.81 1.81 2.50 3.05 ns Combinatorial Sequential Delays Table 35: OLOGIC2 Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.60 –0.05 0.86 –0.05 1.18 0.00 1.15 –0.26 ns TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.75 –0.10 0.75 –0.10 1.01 –0.05 0.56 –0.22 ns TOSRCK/TOCKSR SR pin Setup/Hold with respect to CLK 0.68 –0.28 0.79 –0.28 1.03 –0.23 1.09 –0.46 ns TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.24 –0.08 0.56 –0.06 0.83 –0.01 0.86 –0.18 ns TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.58 –0.06 0.72 –0.06 1.18 –0.01 0.47 –0.12 ns TOCKQ CLK to OQ/TQ out 0.55 0.51 0.74 0.97 ns TRQ_OLOGIC2 SR pin to OQ/TQ out 1.81 1.81 2.50 3.05 ns Sequential Delays DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 36 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 36: ISERDES2 Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV 0.16 –0.09 0.20 –0.09 0.31 –0.09 0.34 –0.14 ns TISCCK_CE / TISCKC_CE CE pin Setup/Hold with respect to CLK 0.71 –0.47 0.71 –0.42 0.97 –0.42 1.39 –0.71 ns TISDCK_D /TISCKD_D D pin Setup/Hold with respect to CLK 0.24 –0.15 0.25 –0.05 0.29 –0.05 0.12 –0.06 ns TISDCK_DDLY /TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using IODELAY2) –0.25 0.30 –0.25 0.42 –0.25 0.56 –0.54 0.67 ns TISDCK_D_DDR /TISCKD_D_DDR D pin Setup/Hold with respect to CLK at DDR mode –0.03 0.04 –0.03 0.16 –0.03 0.18 –0.05 0.12 ns TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY2) –0.40 0.48 –0.40 0.53 –0.40 0.71 –0.71 0.86 ns CLKDIV to out at Q pin 1.30 1.44 2.02 2.22 ns Setup/Hold for Data Lines Sequential Delays TISCKO_Q Output Serializer/Deserializer Switching Characteristics Table 37: OSERDES2 Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units Setup/Hold TOSDCK_D/TOSCKD_D D input Setup/Hold with respect to CLKDIV –0.03 1.02 –0.03 1.17 –0.03 1.27 –0.02 0.23 ns TOSDCK_T/TOSCKD_T(1) T input Setup/Hold with respect to CLK –0.05 1.03 –0.05 1.13 –0.05 1.23 –0.05 0.24 ns TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.12 –0.03 0.15 –0.03 0.24 –0.03 0.28 –0.17 ns TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.14 –0.08 0.17 –0.08 0.27 –0.08 0.31 –0.16 ns TOSCKO_OQ Clock to out from CLK to OQ 0.94 1.11 1.51 1.89 ns TOSCKO_TQ Clock to out from CLK to TQ 0.94 1.11 1.51 1.91 ns Sequential Delays Notes: 1. TOSDCK_T2/TOSCKD_T2 (T input setup/hold with respect to CLKDIV) are reported as TOSDCK_T/TOSCKD_T in TRACE report. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 37 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Input/Output Delay Switching Characteristics Table 38: IODELAY2 Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units TIODCCK_CAL / TIODCKC_CAL CAL pin Setup/Hold with respect to CK 0.28 –0.13 0.33 –0.13 0.48 –0.13 0.57 –0.24 ns TIODCCK_CE / TIODCKC_CE CE pin Setup/Hold with respect to CK 0.14 –0.03 0.17 –0.03 0.25 –0.02 0.33 0.01 ns TIODCCK_INC/ TIODCKC_INC INC pin Setup/Hold with respect to CK 0.10 0.02 0.12 0.03 0.18 0.06 0.23 0.11 ns TIODCCK_RST/ TIODCKC_RST RST pin Setup/Hold with respect to CK 0.12 –0.02 0.15 –0.02 0.22 –0.01 0.28 0.02 ns TTAP1(2) Maximum tap 1 delay 8 14 16 ps TTAP2 Maximum tap 2 delay 40 66 77 ps TTAP3 Maximum tap 3 delay 95 120 140 ps TTAP4 Maximum tap 4 delay 108 141 166 ps TTAP5 Maximum tap 5 delay 171 194 231 ps TTAP6 Maximum tap 6 delay 207 249 292 ps TTAP7 Maximum tap 7 delay 212 276 343 ps TTAP8 Maximum tap 8 delay 292 341 424 ps FMINCAL Minimum allowed bit rate for calibration in variable mode: VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX, and DIFF_PHASE_DETECTOR. 188 188 188 Mb/s TIODDO_IDATAIN Propagation delay through IODELAY2 Note 1 Note 1 Note 1 Note 1 TIODDO_ODATAIN Propagation delay through IODELAY2 Note 1 Note 1 Note 1 Note 1 Notes: 1. Delay depends on IODELAY2 tap setting. See TRACE report for actual values. 2. Maximum delay = integer (number of taps/8) × TTAP8 + TTAPn (where n equals the remainder). For minimum delay consult the TRACE setup and hold report. Minimum delay is greater than 30% of the maximum delay. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 38 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics CLB Switching Characteristics (SLICEM Only) Table 39: CLB Switching Characteristics (SLICEM Only) Symbol Description Speed Grade Units -4 -3 -2 -1L An – Dn LUT inputs to A to D outputs 0.21 0.26 0.38 0.49 ns, Max An – Dn LUT inputs through F7AMUX/F7BMUX to AMUX/CMUX output 0.37 0.43 0.61 0.80 ns, Max TOPAB An – Dn LUT inputs through F7AMUX or F7BMUX and F8MUX to BMUX output 0.37 0.46 0.65 0.86 ns, Max TITO An – Dn LUT inputs through latch to AQ – DQ outputs 0.82 0.95 1.28 1.70 ns, Max TTITO_LOGIC An – Dn LUT inputs to AQ – DQ outputs (latch as logic) 0.82 0.95 1.28 1.70 ns, Max TOPCYA An LUT inputs to COUT output 0.38 0.48 0.72 0.95 ns, Max TOPCYB Bn LUT inputs to COUT output 0.38 0.49 0.71 0.92 ns, Max TOPCYC Cn LUT inputs to COUT output 0.28 0.33 0.49 0.67 ns, Max TOPCYD Dn LUT inputs to COUT output 0.28 0.35 0.48 0.63 ns, Max TAXCY AX input to COUT output 0.21 0.26 0.40 0.51 ns, Max TBXCY BX input to COUT output 0.13 0.16 0.24 0.35 ns, Max TCXCY CX input to COUT output 0.10 0.12 0.18 0.18 ns, Max TDXCY DX input to COUT output 0.09 0.11 0.14 0.18 ns, Max TBYP CIN input to COUT output 0.08 0.10 0.13 0.11 ns, Max TCINA CIN input to AMUX output 0.21 0.22 0.29 0.47 ns, Max TCINB CIN input to BMUX output 0.30 0.31 0.46 0.58 ns, Max TCINC CIN input to CMUX output 0.29 0.31 0.41 0.59 ns, Max TCIND CIN input to DMUX output 0.31 0.32 0.44 0.67 ns, Max Clock to AQ – DQ outputs 0.45 0.53 0.64 0.82 ns, Max Combinatorial Delays TILO Sequential Delays TCKO Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK/TCKDI AX – DX input to CLK on A – D flip-flops 0.42 0.28 0.47 0.39 0.74 0.54 0.99 0.58 ns, Min TCECK/TCKCE CE input to CLK on A – D flip-flops 0.31 –0.07 0.37 –0.07 0.59 –0.07 0.59 –0.27 ns, Min TSRCK/TCKSR SR input to CLK on A – D flip-flops 0.34 0.02 0.42 0.02 0.49 0.02 0.63 –0.33 ns, Min TCINCK/TCKCIN CIN input to CLK on A – D flip-flops 0.31 –0.17 0.31 –0.13 0.49 –0.12 0.79 –0.46 ns, Min TRPW SR input minimum pulse width 0.41 0.48 0.65 1.58 ns, Min TRQ Delay from SR input to AQ – DQ flip-flops 1.81 1.81 2.50 3.05 ns, Max TCEO Delay from CE input to AQ – DQ flip-flops 0.53 0.65 0.92 1.36 ns, Max FTOG Toggle frequency (for export control) 862 806 667 Set/Reset DS162 (v1.9) August 23, 2010 Advance Product Specification MHz www.xilinx.com 39 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only) Symbol Description Speed Grade -4 -3 -2 -1L Clock to A – D outputs 1.26 1.55 2.12 2.56 Clock to A – D outputs (direct output path) 0.96 1.20 1.60 Units Sequential Delays TSHCKO ns, Max ns, Max Setup and Hold Times Before/After Clock CLK TDS/TDH AX – DX or AI – DI inputs to CLK 0.59 0.17 0.73 0.22 1.04 0.37 1.17 0.33 ns, Min TAS/TAH Address An inputs to clock 0.28 0.35 0.32 0.42 0.40 0.67 0.26 0.71 ns, Min TWS/TWH WE input to clock 0.31 –0.08 0.37 –0.08 0.59 –0.08 0.59 –0.27 ns, Min TCECK/TCKCE CE input to CLK 0.31 –0.08 0.37 –0.08 0.59 –0.08 0.59 –0.27 ns, Min CLB Shift Register Switching Characteristics (SLICEM Only) Table 41: CLB Shift Register Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Clock to A – D outputs 1.35 1.78 2.14 2.89 Clock to A – D outputs (direct output path) 1.24 1.65 1.95 Units Sequential Delays TREG ns, Max ns, Max Setup and Hold Times Before/After Clock CLK TWS/TWH WE input to CLK 0.20 –0.07 0.24 –0.07 0.36 –0.07 0.59 –0.17 ns, Min TCECK/TCKCE CE input to CLK 0.27 0.36 0.29 0.38 0.52 0.40 0.59 –0.17 ns, Min TDS/TDH AX – DX or AI – DI inputs to CLK 0.07 0.11 0.09 0.14 0.18 0.28 1.16 0.28 ns, Min DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 40 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Block RAM Switching Characteristics Table 42: Block RAM Switching Characteristics Symbol Speed Grade Description Units -4 -3 -2 -1L 1.85 2.10 2.90 3.50 ns, Max 1.60 1.75 1.90 2.30 ns, Max Block RAM Clock to Out Delays TRCKO_DO TRCKO_DO_REG Clock CLK to DOUT output (without output register)(1) Clock CLK to DOUT output (with output register)(2) Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR ADDR inputs(3) 0.35 0.10 0.40 0.12 0.40 0.15 0.50 0.15 ns, Min TRDCK_DI/TRCKD_DI DIN inputs (4) 0.30 0.10 0.30 0.10 0.30 0.12 0.40 0.15 ns, Min TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.21 0.05 0.22 0.06 0.28 0.10 0.26 0.10 ns, Min TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.20 0.10 0.20 0.10 0.25 0.12 0.28 0.15 ns, Min TRCCK_WE/TRCKC_WE Write Enable (WE) input 0.25 0.10 0.33 0.10 0.46 0.12 0.28 0.15 ns, Min Block RAM in all modes 320 280 260 150 MHz Maximum Frequency FMAX Notes: 1. TRCKO_DO includes TRCKO_DOA and TRCKO_DOPA as well as the B port equivalent timing parameters. 2. TRCKO_DO_REG includes TRCKO_DOA_REG and TRCKO_DOPA_REG as well as the B port equivalent timing parameters. 3. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 4. TRDCK_DI includes both A and B inputs as well as the parity inputs of A and B. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 41 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DSP48A1 Switching Characteristics Table 43: DSP48A1 Switching Characteristics Symbol Preadder Description Multiplier Postadder Speed Grade -4 -3 -2 -1L Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_A1REG/ TDSPCKD_A_A1REG A input to A1 register CLK N/A N/A N/A 0.15 0.09 0.17 0.09 0.23 0.09 0.32 0.09 ns TDSPDCK_D_B1REG/ TDSPCKD_D_B1REG D input to B1 register CLK Yes N/A N/A 1.90 –0.07 1.95 –0.07 1.99 –0.07 2.82 –0.07 ns TDSPDCK_C_CREG/ TDSPCKD_C_CREG C input to C register CLK N/A N/A N/A 0.11 0.15 0.13 0.15 0.17 0.15 0.24 0.09 ns TDSPDCK_D_DREG/ TDSPCKD_D_DREG D input to D register CLK N/A N/A N/A 0.09 0.15 0.10 0.15 0.14 0.15 0.19 0.12 ns TDSPDCK_OPMODE_B1REG/ TDSPCKD_OPMODE_B1REG OPMODE input to B1 register CLK Yes N/A N/A 1.97 0.01 2.00 0.01 2.01 0.01 2.85 0.01 ns N/A N/A N/A 0.18 0.12 0.21 0.12 0.28 0.26 0.40 0.12 ns TDSPDCK_OPMODE_OPMODEREG/ OPMODE input to TDSPCKD_OPMODE_OPMODEREG OPMODE register CLK Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_A_MREG/ TDSPCKD_A_MREG A input to M register CLK N/A Yes N/A 3.06 –0.40 3.51 –0.40 3.71 –0.40 3.97 –0.40 ns TDSPDCK_B_MREG/ TDSPCKD_B_MREG B input to M register CLK Yes Yes N/A 3.96 –0.68 4.58 –0.68 5.28 –0.68 7.00 –0.68 ns TDSPDCK_D_MREG/ TDSPCKD_D_MREG D input to M register CLK Yes Yes N/A 4.23 –0.56 4.80 –0.56 4.82 –0.56 6.84 –0.56 ns TDSPDCK_OPMODE_MREG/ TDSPCKD_OPMODE_MREG OPMODE to M register CLK Yes Yes N/A 4.18 –0.48 4.80 –0.48 4.85 –0.48 6.88 –0.48 ns No Yes N/A 2.37 –0.48 2.70 –0.48 3.02 –0.48 4.28 –0.48 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_A_PREG/ TDSPCKD_A_PREG A input to P register CLK N/A Yes Yes 4.32 –0.76 5.06 –0.76 5.38 –0.76 7.52 –0.76 ns TDSPDCK_B_PREG/ TDSPCKD_B_PREG B input to P register CLK Yes Yes Yes 5.87 –0.59 6.87 –0.59 7.87 –0.59 10.55 –0.59 ns No Yes Yes 4.14 –0.93 4.68 –0.93 6.16 –0.93 8.12 –0.93 ns TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK N/A N/A Yes 2.20 –0.23 2.25 –0.23 2.30 –0.23 3.27 –0.23 ns TDSPDCK_D_PREG/ TDSPCKD_D_PREG D input to P register CLK Yes Yes Yes 5.90 –0.92 6.91 –0.92 7.32 –0.92 10.39 –0.92 ns TDSPDCK_OPMODE_PREG/ TDSPCKD_OPMODE_PREG OPMODE input to P register CLK Yes Yes Yes 6.21 –0.84 7.27 –0.84 7.35 –0.84 10.43 –0.84 ns No Yes Yes 1.69 –0.87 1.98 –0.87 2.55 –0.87 3.62 –0.87 ns No No Yes 2.09 –0.22 2.30 –0.22 2.67 –0.22 3.79 –0.22 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 42 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 43: DSP48A1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Preadder Multiplier Postadder -4 -3 -2 -1L N/A N/A N/A 1.20 1.34 1.34 1.90 ns N/A N/A Yes 3.38 3.95 4.19 5.83 ns Units Clock to Out from Output Register Clock to Output Pin TDSPCKO_P_PREG CLK (PREG) to P output Clock to Out from Pipeline Register Clock to Output Pins TDSPCKO_P_MREG CLK (MREG) to P output Clock to Out from Input Register Clock to Output Pins TDSPCKO_P_A1REG CLK (A1REG) to P output N/A Yes Yes 5.02 5.87 6.80 9.65 ns TDSPCKO_P_B1REG CLK (B1REG) to P output N/A Yes Yes 5.02 5.87 6.79 9.63 ns TDSPCKO_P_CREG CLK (CREG) to P output N/A N/A Yes 3.12 3.64 3.70 5.24 ns TDSPCKO_P_DREG CLK (DREG) to P output Yes Yes Yes 6.77 7.92 9.06 12.53 ns N/A No Yes 2.85 3.33 3.41 4.73 ns N/A Yes No 3.35 3.93 4.83 6.74 ns N/A Yes Yes 4.56 5.22 6.38 8.94 ns Yes No No 3.22 3.76 3.91 5.55 ns Yes Yes No 6.01 6.54 6.88 9.76 ns Yes Yes Yes 6.27 7.34 8.43 11.96 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_P TDSPDO_B_P A input to P output B input to P output TDSPDO_C_P C input to P output N/A N/A Yes 2.69 3.15 3.30 4.68 ns TDSPDO_D_P D input to P output Yes Yes Yes 6.31 7.38 8.32 11.81 ns TDSPDO_OPMODE_P OPMODE input to P output Yes Yes Yes 6.43 7.52 8.35 11.84 ns No Yes Yes 4.84 5.66 6.52 9.25 ns No No Yes 3.11 3.49 3.55 5.03 ns Yes Yes Yes 390 333 302 213 MHz Maximum Frequency FMAX All registers used Notes: 1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because no path exists. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 43 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 44: Device DNA Interface Port Switching Characteristics Symbol Speed Grade Description -4 -3 -2 Units -1L TDNASSU Setup time on SHIFT before the rising edge of CLK 7 ns, Min TDNASH Hold time on SHIFT after the rising edge of CLK 1 ns, Min TDNADSU Setup time on DIN before the rising edge of CLK 7 ns, Min TDNADH Hold time on DIN after the rising edge of CLK 1 ns, Min TDNARSU Setup time on READ before the rising edge of CLK 7 ns, Min 1,000 ns, Max TDNARH Hold time on READ after the rising edge of CLK 1 ns, Min TDNADCKO Clock-to-output delay on DOUT after rising edge of CLK 0.5 ns, Min 6 ns, Max CLK frequency 2 MHz, Max TDNACLKL CLK Low time 50 ns, Min TDNACLKH CLK High time 50 ns, Min TDNACLKF (2) Notes: 1. The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 µs. 2. Also applies to TCK when reading DNA through the boundary-scan port. Table 45: Suspend Mode Switching Characteristics Description Min Max Units TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter 2.5 14 ns TSUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled 31 430 ns TSUSPEND_GWE Rising edge of SUSPEND pin until FPGA output pins drive their defined SUSPEND constraint behavior (without glitch filter) – 15 ns TSUSPEND_GTS Rising edge of SUSPEND pin to write-protect lock on all writable clocked elements (without glitch filter) – 15 ns TSUSPEND_DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnect disabled (without glitch filter) – 1500 ns TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not include DCM or PLL lock time. 7 75 µs TSUSPEND_ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnect reenabled 7 41 µs TAWAKE_GWE1 Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1. – 80 ns TAWAKE_GWE512 Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512. – 20.5 µs TAWAKE_GTS1 Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1. – 80 ns TAWAKE_GTS512 Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512. – 20.5 µs TSCP_AWAKE Rising edge of SCP pins to rising edge of AWAKE pin 7 75 µs Symbol Entering Suspend Mode Exiting Suspend Mode DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 44 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Configuration Switching Characteristics Table 46: Configuration Switching Characteristics(1) Symbol Description Speed Grade Units -4 -3 -2 -1L 4 4 4 5 ms, Max Power-up Timing Characteristics TPL(2) PROGRAM_B Latency TPOR(2) Power-on-Reset 5/40 5/40 5/40 5/40 ms, Min/Max TPROGRAM PROGRAM_B Pulse Width 500 500 500 500 ns, Min 6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0 ns, Min Slave Serial Mode Programming Switching TDCCK/TCCKD DIN Setup/Hold, slave mode TCCO CCLK to DOUT 12 12 12 17 ns, Max FSCCK Slave mode external CCLK 80 80 80 50 MHz, Max Slave SelectMAP Mode Programming Switching TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold 6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0 ns, Min TSMCSCCK/TSMCCKCS CSI_B Setup/Hold 7.0/0.0 7.0/0.0 7.0/0.0 9.0/2.0 ns, Min TSMCCKW/TSMWCCK RDWR_B Setup/Hold 17.0/1.0 17.0/1.0 17.0/1.0 27.0/2.0 ns, Min TSMCKCSO CSO_B clock to out 16 16 16 26 ns, Min TSMCO CCLK to DATA out in readback 13 13 13 25 ns, Max TSMCKBY CCLK to BUSY out in readback 12 12 12 17 ns, Max Maximum CCLK frequency (XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T only) 50 50 50 25 MHz, Max Maximum CCLK frequency (XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) 40 40 40 20 MHz, Max Maximum Readback CCLK frequency (XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T only) 20 20 20 4 MHz, Max Maximum Readback CCLK frequency (XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) 12 12 12 4 MHz, Max FSMCCK FRBCCK Boundary-Scan Port Timing Specifications TTAPTCK TMS and TDI Setup time before TCK 10 10 10 17 ns, Min TTCKTAP TMS and TDI Hold time after TCK 5.5 5.5 5.5 5.5 ns, Min TTCKTDO TCK falling edge to TDO output valid 6.5 6.5 6.5 8 ns, Max TTCKH TCK clock minimum High time 12 12 12 21 ns, Min TTCKL TCK clock minimum Low time 12 12 12 21 ns, Min FTCK Maximum configuration TCK clock frequency 33 33 33 18 MHz, Max FTCKB Maximum boundary-scan TCK clock frequency 33 33 33 18 MHz, Max FTCKAES Maximum AES key TCK clock frequency 2 2 2 2 MHz, Max DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 45 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 46: Configuration Switching Characteristics(1) (Cont’d) Symbol Description Speed Grade Units -4 -3 -2 -1L 15 15 15 20 ns, Min BPI Master Flash Mode Programming Switching(3) TBPICCO(4) A[25:0], FCS_B, FOE_B, FWE_B, LDC outputs valid after CCLK falling edge TBPIICCK Master BPI CCLK (output) delay 10/100 10/100 10/100 10/130 µs, Min/Max TBPIDCC/TBPICCD Setup/Hold on D[15:0] data input pins 5.0/1.0 5.0/1.0 5.0/1.0 6.0/2.0 ns, Min ns, Min SPI Master Flash Mode Programming Switching TSPIDCC/TSPIDCCD DIN, MISO0, MISO1, MISO2, MISO3, Setup/Hold before/after the rising CCLK edge 5.0/1.0 5.0/1.0 5.0/1.0 7.0/1.0 TSPIICCK Master SPI CCLK (output) delay 0.4/7.0 0.4/7.0 0.4/7.0 0.4/10.0 µs, Min/Max TSPICCM MOSI clock to out 13 13 13 19 ns, Max TSPICCFC CSO_B clock to out 16 16 16 26 ns, Max CCLK Output (Master Modes) TMCCKL Master CCLK clock duty cycle Low 40/60 %, Min/Max TMCCKH Master CCLK clock duty cycle High 40/60 %, Min/Max FMCCK Maximum Frequency, master mode 40 40 40 30 MHz, Max FMCCKTOL Frequency Tolerance, master mode ±50 ±50 ±50 ±50 % CCLK Input (Slave Modes) TSCCKL Slave CCLK clock minimum Low time 5 5 5 8 ns, Min TSCCKH Slave CCLK clock minimum High time 5 5 5 8 ns, Min TUSERCCLKL USERCCLK clock minimum Low time 12 12 12 21 ns, Min TUSERCCLKH USERCCLK clock minimum High time 12 12 12 21 ns, Min FUSERCCLK Maximum USERCCLK frequency 40 40 40 30 MHz, Max USERCCLK Input Notes: 1. 2. 3. 4. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. To support longer delays in configuration, use the design solutions described in the Spartan-6 FPGA Configuration User Guide. BPI mode is not supported in: • LX4, LX25, or LX25T devices • LX9 devices in the TQG144 package • LX9 or LX16 devices in the CPG196 package. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 46 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Clock Buffers and Networks Table 47: Global Clock Switching Characteristics Symbol TGSI Description S pin Setup to I0/I1 inputs BUFGMUX delay from I0/I1 to O TGIO Devices Speed Grade Units -4 -3 -2 -1L LX Family N/A 0.31 0.48 0.60 ns LXT Family 0.25 0.31 0.48 N/A ns LX Family N/A 0.21 0.21 LXT Family 0.21 0.21 0.21 LX Family N/A 400 375 LXT Family 400 400 375 ns N/A ns Maximum Frequency Global clock tree (BUFG) FMAX MHz N/A MHz Table 48: Input/Output Clock Switching Characteristics (BUFIO2) Symbol TBUFCKO_O Description Clock to out delay from I to O Devices Speed Grade Units -4 -3 -2 -1L LX Family N/A 0.82 1.09 1.80 ns LXT Family 0.67 0.82 1.09 N/A ns LX Family N/A 525 500 LXT Family 540 525 500 Maximum Frequency FMAX I/O clock tree (BUFIO2) MHz N/A MHz Table 49: Input/Output Clock Switching Characteristics (BUFPLL) Symbol Description Devices Speed Grade -4 -3 -2 LX Family N/A 1050 950 LXT Family 1080 1050 950 -1L Units Maximum Frequency FMAX BUFPLL clock tree (BUFPLL) DS162 (v1.9) August 23, 2010 Advance Product Specification MHz N/A MHz www.xilinx.com 47 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics PLL Switching Characteristics Table 50: PLL Specification Symbol FINMAX FINMIN Speed Grade Device(1) Description -4 -3 -2 Units -1L Maximum Input Clock Frequency from I/O Clock LX Family N/A 525 450 MHz LXT Family 540 525 450 Maximum Input Clock Frequency from Global Clock LX Family N/A 400 375 LXT Family 400 400 375 Minimum Input Clock Frequency LX Family N/A 19 19 LXT Family 19 19 19 <20% of clock input period or 1 ns Max N/A MHz MHz N/A MHz MHz N/A MHz FINJITTER Maximum Input Clock Period Jitter All FINDUTY Allowable Input Duty Cycle: 19—199 MHz All 25/75 % Allowable Input Duty Cycle: 200—299 MHz All 35/65 % Allowable Input Duty Cycle: > 300 MHz All 45/55 % Minimum PLL VCO Frequency LX Family N/A 400 400 400 MHz LXT Family 400 400 400 N/A MHz LX Family N/A 1050 1000 1000 MHz LXT Family 1080 1050 1000 N/A MHz FVCOMIN FVCOMAX FBANDWIDTH TSTAPHAOFFSET TOUTJITTER Maximum PLL VCO Frequency Low PLL Bandwidth at Typical(3) All 1 1 1 1 MHz High PLL Bandwidth at Typical(3) All 4 4 4 4 MHz All 0.12 0.12 0.12 Static Phase Offset of the PLL Outputs PLL Output Jitter(3) All TOUTDUTY PLL Output Clock Duty Cycle TLOCKMAX Precision(4) ns Note 2 All 0.15 0.15 0.20 PLL Maximum Lock Time All 100 100 100 FOUTMAX PLL Maximum Output Frequency for BUFGMUX LX Family N/A 400 375 LXT Family 400 400 375 FOUTMAX PLL Maximum Output Frequency for BUFPLL LX Family N/A 1050 950 ns 100 µs MHz N/A MHz MHz LXT Family 1080 1050 950 N/A MHz FOUTMIN PLL Minimum Output Frequency(5) All 3.125 3.125 3.125 3.125 MHz TEXTFDVAR External Clock Feedback Variation All < 20% of clock input period or 1 ns Max RSTMINPULSE Minimum Reset Pulse Width All 5 5 5 FPFDMAX(5) Maximum Frequency at the Phase Frequency Detector LX Family N/A 500 400 LXT Family 500 500 400 Minimum Frequency at the Phase Frequency Detector LX Family N/A 19 19 LXT Family 19 19 19 Maximum Delay in the Feedback Path All FPFDMIN TFBDELAY 5 ns MHz N/A MHz MHz N/A MHz 3 ns Max or one CLKIN cycle Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. Values for this parameter are available in the Clocking Wizard. 3. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies. 4. Includes global clock buffer. 5. Calculated as FVCO/128 assuming output duty cycle is 50%. 6. When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector frequency. FPFDMAX = FCLKFB / CLKFBOUT_MULT DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 48 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DCM Switching Characteristics Table 51: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL)(1) Speed Grade Symbol Description -4 -3 -2 -1L Units Min Max Min Max Min Max Min Max Frequency of the CLKIN clock input. Also described as FCLKIN. 5(2) 280(3) 5(2) 280(3) 5(2) 250(3) 5(2) 175(3) MHz CLKIN pulse width as a percentage of the CLKIN period for CLKIN_FREQ_DLL < 150 MHz 40 60 40 60 40 60 40 60 % CLKIN pulse width as a percentage of the CLKIN period for CLKIN_FREQ_DLL > 150 MHz 45 55 45 55 45 55 45 55 % Cycle-to-cycle jitter at the CLKIN input for CLKIN_FREQ_DLL < 150 MHz – ±300 – ±300 – ±300 – ±300 ps Cycle-to-cycle jitter at the CLKIN input for CLKIN_FREQ_DLL > 150 MHz. – ±150 – ±150 – ±150 – ±150 ps CLKIN_PER_JITT_DLL Period jitter at the CLKIN input. – ±1 – ±1 – ±1 – ±1 ns CLKFB_DELAY_VAR_EXT Allowable variation of the off-chip feedback delay from the DCM output to the CLKFB input. – ±1 – ±1 – ±1 – ±1 ns Input Frequency Ranges CLKIN_FREQ_DLL Input Pulse Requirements CLKIN_PULSE Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF Notes: 1. DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV. 2. When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See Table 53. 3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to the FMAX for the global clock BUFG, see Table 47. When set to TRUE, the CLKIN_DIVIDE_BY_2 attribute divides the incoming clock frequency by two as it enters the DCM. 4. CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must then reset the DCM. 5. When using both DCMs in a CMT, both DCMs must be LOCKED. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 49 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)(1) Speed Grade Symbol Description -4 -3 -2 -1L Min Max Min Max Min Max Min Units Max Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs. 5 280 5 280 5 250 MHz CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs. 5 200 5 200 5 200 MHz CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs. 10 375 10 375 10 334 MHz CLKOUT_FREQ_DV Frequency for the CLKDV output. 0.3125 186 0.3125 186 0.3125 166 MHz Output Clock Jitter(2)(3)(4) CLKOUT_PER_JITT_0 Period jitter at the CLK0 output. – ±100 – ±100 – ±100 – ps CLKOUT_PER_JITT_90 Period jitter at the CLK90 output. – ±150 – ±150 – ±150 – ps CLKOUT_PER_JITT_180 Period jitter at the CLK180 output. – ±150 – ±150 – ±150 – ps CLKOUT_PER_JITT_270 Period jitter at the CLK270 output. – ±150 – ±150 – ±150 – ps CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs. CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer division. CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer division. Maximum = ±[0.5% of CLKIN period + 100] – ±150 – ±150 – ps ±150 ps Maximum = ±[0.5% of CLKIN period + 100] ps Duty Cycle(4) CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion. Typical = ±[1% of CLKIN period + 350] ps Phase Alignment(4) CLKIN_CLKFB_PHASE CLKOUT_PHASE_DLL Phase offset between the CLKIN and CLKFB inputs (CLK_FEEDBACK = 1X). – Phase offset between the CLKIN and CLKFB inputs (CLK_FEEDBACK = 2X). – ±150 – ±150 – ±150 – ±250 ps Max ±250 – ±250 – ±250 Phase offset between DLL outputs for CLK0 to CLK2X (not CLK2X180). Maximum = ±[1% of CLKIN period + 100] ps Phase offset between DLL outputs for all others. Maximum = ±[1% of CLKIN period + 150] ps DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 50 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)(1) (Cont’d) Speed Grade Symbol Description LOCK_DLL(3) -4 -3 -2 -1L Units Min Max Min Max Min Max Min Max When using the DLL alone: The time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase. 5 MHz < CLKIN_FREQ_DLL < 50 MHz. – 5 – 5 – 5 – 5 ms When using the DLL alone: The time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase. CLKIN_FREQ_DLL > 50 MHz – 0.60 – 0.60 – 0.60 – 0.60 ms Finest delay resolution, averaged over all steps. 10 40 10 40 10 40 10 40 ps Delay Lines DCM_DELAY_STEP(5) Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 51. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of ±(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns or 100 ps, the maximum jitter is ±(100 ps + 150 ps) = ±250 ps. 5. A typical delay step size is 23 ps. Table 53: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)(1) Speed Grade Symbol Description -4 -3 -2 -1L Min Units Min Max Min Max Min Max Max 0.5 375 0.5 375 0.5 333 Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency: FCLKFX < 150 MHz. – ±300 – ±300 – ±300 – ±300 ps CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency: FCLKFX > 150 MHz. – ±150 – ±150 – ±150 – ±150 ps CLKIN_PER_JITT_FX – ±1 – ±1 – ±1 – ±1 ns Input Frequency Ranges(2) CLKIN_FREQ_FX Frequency for the CLKIN input. Also described as FCLKIN. MHz Input Clock Jitter Tolerance(3) CLKIN_CYC_JITT_FX_LF Period jitter at the CLKIN input. Notes: 1. DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180). 2. When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 51. 3. CLKIN input jitter beyond these limits can cause the DCM to lose LOCK. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 51 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP(1) Speed Grade Symbol Description -4 -3 -2 -1L Min Max Min Max Min Max 5 375 5 375 5 333 Min Units Max Output Frequency Ranges CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs MHz Output Clock Jitter(2)(3) CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN < 20 MHz Use the Clocking Wizard ps Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN > 20 MHz Typical = ±(1% of CLKFX period + 100) ps Maximum = ±(1% of CLKFX period + 350) ps Duty Cycle(4)(5) Duty cycle precision for the CLKFX and CLKFX180 outputs including the CLKOUT_DUTY_CYCLE_FX BUFGMUX and clock tree duty-cycle distortion Phase Alignment(5) CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used – ±200 – ±200 – ±200 – ±250 Maximum = ±(1% of CLKFX period + 200) ps ps LOCKED Time LOCK_FX(2) When 5 MHz < FCLKIN < 50 MHz, the time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. When using both the DLL and the DFS, use the longer locking time. – 5 – 5 – 5 – 5 ms When FCLKIN > 50 MHz, the time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. When using both the DLL and the DFS, use the longer locking time. – 0.45 – 0.45 – 0.45 – 0.60 ms Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 53. 2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute. 3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on the system application. 4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%. 5. Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 52 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1) Speed Grade Symbol Description -4 -3 -2 -1L Units Min Max Min Max Min Max Min Max 5 375 5 375 5 333 5 200 MHz 100 MHz Output Frequency Ranges (DCM_CLKGEN) CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs CLKOUT_FREQ_FXDV Frequency for the CLKFXDV output 0.15625 187.5 0.15625 187.5 0.15625 166.5 0.15625 Output Clock Jitter(2)(3) CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. Typical = ±[0.2% of CLKFX period + 100] ps Typical = ±[0.2% of CLKFX period + 100] ps CLKFX period change in free running oscillator mode at the same temperature. FCLKFX > 50 MHz Maximum = ±3% of CLKFX period ps CLKFX period change in free running oscillator mode at the same temperature. FCLKFX < 50 MHz Maximum = ±5% of CLKFX period ps CLKFX period will change in free_oscillator mode over temperature. Add to CLKFX_FREEZE_VAR to determine total CLKFX period change. Percentage change for CLKFX period over 1°C. Maximum = 0.1 %/°C CLKOUT_DUTY_CYCLE_ FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion Maximum = ±[1% of CLKFX period + 350] ps CLKOUT_DUTY_CYCLE_ FXDV Duty cycle precision for the CLKFXDV outputs, including the BUFGMUX and clock tree duty-cycle distortion Maximum = ±[1% of CLKFX period + 350] ps CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV output. CLKFX_FREEZE_VAR CLKFX_FREEZE_TEMP _SLOPE Duty Cycle(4)(5) Lock Time LOCK_FX(2) The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX, CLKFX180, and CLKFXDV signals are valid. Lock time requires CLKFX_DIVIDE < FIN/(0.50 MHz) when: 5 MHz < FCLKIN < 50 MHz – 50 – 50 – 50 – 50 ms when: FCLKIN > 50 MHz – 5 – 5 – 5 – 5 ms DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 53 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1) (Cont’d) Speed Grade Symbol Description -4 -3 -2 -1L Units Min Max Min Max Min Max Min Max 30 200 30 200 30 200 30 200 Spread Spectrum FCLKIN_FIXED_SPREAD_ SPECTRUM Frequency of the CLKIN input for fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD/ CENTER_HIGH_SPREAD) TCENTER_LOW_SPREAD(6) Spread at the CLKFX output for fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD) 100 Typical = -----------------------------------------CLKFX_DIVIDE Spread at the CLKFX output for fixed spread spectrum (SPREAD_SPECTRUM= CENTER_HIGH_SPREAD) 240 Typical = -----------------------------------------CLKFX_DIVIDE TCENTER_HIGH_SPREAD(6) SPECTRUM (6) ps Maximum = 250 ps Maximum = 400 Average modulation frequency when using fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD / CENTER_HIGH_SPREAD) FMOD_FIXED_SPREAD_ MHz Typical = FIN/1024 MHz Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 53. 2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute. 3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on the system application. 4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%. 5. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps. 6. When using CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, the valid values for CLKFX_MULTIPLY are limited to 2 through 32, and the valid values for CLKFX_DIVIDE are limited to 1 through 4. Table 56: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode Speed Grade Symbol Description -4 -3 -2 -1L Units Min Max Min Max Min Max Min Max 1 167 1 167 1 167 1 100 MHz 40 60 40 60 40 60 40 60 % Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input. Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 54 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode(1) Symbol Description Amount of Phase Shift Units When CLKIN < 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. When using CLKIN_DIVIDE_BY_2 = TRUE, double the clock-effective clock period. ±(INTEGER(10 x (TCLKIN – 3 ns))) steps When CLKIN ≥ 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. When using CLKIN_DIVIDE_BY_2 = TRUE, double the clock-effective clock period. ±(INTEGER(15 x (TCLKIN – 3 ns))) steps FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting. ±(MAX_STEPS x DCM_DELAY_STEP_MIN) ns FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±(MAX_STEPS x DCM_DELAY_STEP_MAX) ns Phase Shifting Range MAX_STEPS(2) Notes: 1. The values in this table are based on the operating conditions described in Table 51 and Table 56. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the end of Table 52. Table 58: Miscellaneous DCM Timing Parameters(1) Symbol Description DCM_RST_PW_MIN Min Max Units 3 – CLKIN cycles Minimum duration of a RST pulse width Notes: 1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected. Table 59: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY (DCM_SP) 2 32 CLKFX_DIVIDE (DCM_SP) 1 32 CLKDV_DIVIDE (DCM_SP) 1.5 16 CLKFX_MULTIPLY (DCM_CLKGEN) 2 256 CLKFX_DIVIDE (DCM_CLKGEN) 1 256 CLKFXDV_DIVIDE (DCM_CLKGEN) 2 32 Table 60: DCM Switching Characteristics Symbol Description Speed Grade -4 -3 -2 -1L Units TDMCCK_PSEN/ TDMCKC_PSEN PSEN Setup/Hold 1.50 0.00 1.50 0.00 1.50 0.00 1.50 0.00 ns TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC PSINCDEC Setup/Hold 1.50 0.00 1.50 0.00 1.50 0.00 1.50 0.00 ns TDMCKO_PSDONE Clock to out of PSDONE 1.50 1.50 1.50 1.50 ns DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 55 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Spartan-6 Device Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 61 through Table 67. Values are expressed in nanoseconds unless otherwise noted. Table 61: Global Clock Input to Output Delay Without DCM or PLL Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL TICKOF Global Clock and OUTFF without DCM or PLL XC6SLX4 N/A 6.48 7.44 ns XC6SLX9 N/A 6.34 7.33 ns XC6SLX16 N/A 6.42 7.48 ns XC6SLX25 N/A 6.69 7.84 ns XC6SLX25T 6.20 6.69 7.84 XC6SLX45 N/A 6.88 8.10 XC6SLX45T 6.42 6.88 8.10 XC6SLX75 N/A 7.22 8.42 XC6SLX75T 6.60 7.22 8.42 XC6SLX100 N/A 7.18 8.41 XC6SLX100T 6.72 7.18 8.41 XC6SLX150 N/A 7.68 8.80 XC6SLX150T 7.11 7.68 8.80 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 56 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 62: Global Clock Input to Output Delay With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode. TICKOFDCM Global Clock and OUTFF with DCM XC6SLX4 N/A 4.50 5.32 ns XC6SLX9 N/A 4.50 5.31 ns XC6SLX16 N/A 4.57 5.34 ns XC6SLX25 N/A 4.18 4.59 ns XC6SLX25T 3.95 4.18 4.59 XC6SLX45 N/A 4.70 5.50 XC6SLX45T 4.37 4.70 5.50 XC6SLX75 N/A 4.23 4.77 XC6SLX75T 3.90 4.23 4.77 XC6SLX100 N/A 4.16 4.66 XC6SLX100T 3.90 4.16 4.66 XC6SLX150 N/A 4.33 4.83 XC6SLX150T 4.03 4.33 4.83 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 57 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 63: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode. TICKOFDCM_0 Global Clock and OUTFF with DCM XC6SLX4 N/A 5.44 6.42 ns XC6SLX9 N/A 5.43 6.42 ns XC6SLX16 N/A 5.51 6.44 ns XC6SLX25 N/A 5.13 5.69 ns XC6SLX25T 4.81 5.13 5.69 XC6SLX45 N/A 5.69 6.63 XC6SLX45T 5.26 5.69 6.63 XC6SLX75 N/A 5.18 5.88 XC6SLX75T 4.77 5.18 5.88 XC6SLX100 N/A 5.11 5.76 XC6SLX100T 4.76 5.11 5.76 XC6SLX150 N/A 5.30 5.93 XC6SLX150T 4.90 5.30 5.93 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. Table 64: Global Clock Input to Output Delay With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode. TICKOFPLL Global Clock and OUTFF with PLL XC6SLX4 N/A 4.69 5.48 ns XC6SLX9 N/A 4.68 5.47 ns XC6SLX16 N/A 4.64 5.39 ns XC6SLX25 N/A 4.32 4.91 ns XC6SLX25T 4.03 4.32 4.91 XC6SLX45 N/A 4.96 5.75 XC6SLX45T 4.63 4.96 5.75 XC6SLX75 N/A 4.30 4.88 XC6SLX75T 4.01 4.30 4.88 XC6SLX100 N/A 4.33 4.90 XC6SLX100T 4.06 4.33 4.90 XC6SLX150 N/A 3.98 4.58 XC6SLX150T 3.65 3.98 4.58 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 58 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 65: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode. TICKOFPLL_0 Global Clock and OUTFF with PLL XC6SLX4 N/A 5.81 6.87 ns XC6SLX9 N/A 5.80 6.86 ns XC6SLX16 N/A 5.77 6.79 ns XC6SLX25 N/A 5.35 6.10 ns XC6SLX25T 5.00 5.35 6.10 XC6SLX45 N/A 6.03 7.02 XC6SLX45T 5.59 6.03 7.02 XC6SLX75 N/A 5.41 6.22 XC6SLX75T 4.96 5.41 6.22 XC6SLX100 N/A 5.42 6.21 XC6SLX100T 5.01 5.42 6.21 XC6SLX150 N/A 5.06 5.86 XC6SLX150T 4.59 5.06 5.86 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. Table 66: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode and PLL in DCM2PLL Mode. TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XC6SLX4 N/A 5.01 5.90 ns XC6SLX9 N/A 5.01 5.89 ns XC6SLX16 N/A 5.12 5.94 ns XC6SLX25 N/A 5.09 5.92 ns XC6SLX25T 4.70 5.09 5.92 XC6SLX45 N/A 4.98 5.83 XC6SLX45T 4.63 4.98 5.83 XC6SLX75 N/A 5.04 5.88 XC6SLX75T 4.68 5.04 5.88 XC6SLX100 N/A 5.07 5.92 XC6SLX100T 4.76 5.07 5.92 XC6SLX150 N/A 4.73 5.31 XC6SLX150T 4.44 4.73 5.31 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 59 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 67: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode and PLL in DCM2PLL Mode. TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XC6SLX4 N/A 5.95 7.00 ns XC6SLX9 N/A 5.94 7.00 ns XC6SLX16 N/A 6.06 7.05 ns XC6SLX25 N/A 6.04 7.02 ns XC6SLX25T 5.57 6.04 7.02 XC6SLX45 N/A 5.97 6.96 XC6SLX45T 5.53 5.97 6.96 XC6SLX75 N/A 6.00 6.99 XC6SLX75T 5.55 6.00 6.99 XC6SLX100 N/A 6.03 7.02 XC6SLX100T 5.62 6.03 7.02 XC6SLX150 N/A 5.70 6.41 XC6SLX150T 5.32 5.70 6.41 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 60 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Spartan-6 Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 68 through Table 74. Values are expressed in nanoseconds unless otherwise noted. Table 68: Global Clock Setup and Hold Without DCM or PLL Symbol Description Device Speed Grade -4 -1L Units -3 -2 N/A 0.34/ 1.54 0.34/ 1.59 ns N/A 0.31/ 1.40 0.31/ 1.49 ns XC6SLX16 N/A 0.12/ 1.48 0.12/ 1.64 ns XC6SLX25 N/A 0.18/ 1.75 0.18/ 1.99 ns XC6SLX25T 0.18/ 1.64 0.18/ 1.75 0.18/ 1.99 XC6SLX45 N/A –0.08/ 1.95 –0.08/ 2.27 –0.08/ 1.88 –0.08/ 1.95 –0.08/ 2.27 XC6SLX75 N/A 0.13/ 2.29 0.13/ 2.57 XC6SLX75T 0.13/ 2.08 0.13/ 2.29 0.13/ 2.57 N/A ns XC6SLX100 N/A –0.14/ 2.24 –0.14/ 2.56 0 ns –0.14/ 2.15 –0.14/ 2.24 –0.14/ 2.56 N/A ns N/A –0.24/ 2.74 –0.24/ 2.95 –0.24/ 2.55 –0.24/ 2.74 –0.24/ 2.95 Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) XC6SLX4 Global Clock and IFF(2) without DCM or PLL XC6SLX9 XC6SLX45T XC6SLX100T XC6SLX150 XC6SLX150T N/A ns ns N/A ns ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 61 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 69: Global Clock Setup and Hold With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM XC6SLX4 in System-Synchronous Mode N/A 1.97/ 0.18 2.20/ 0.18 ns XC6SLX9 N/A 1.96/ 0.19 2.19/ 0.19 ns XC6SLX16 N/A 1.87/ –0.17 2.13/ –0.17 ns XC6SLX25 N/A 1.78/ 0.17 2.00/ 0.17 ns XC6SLX25T 1.79/ 0.16 1.79/ 0.17 2.00/ 0.17 XC6SLX45 N/A 1.84/ 0.08 2.02/ 0.08 XC6SLX45T 1.76/ 0.07 1.84/ 0.08 2.02/ 0.08 XC6SLX75 N/A 1.98/ 0.12 2.20/ 0.12 XC6SLX75T 1.89/ 0.11 1.98/ 0.12 2.20/ 0.12 XC6SLX100 N/A 1.72/ 0.17 1.97/ 0.17 XC6SLX100T 1.69/ 0.16 1.72/ 0.17 1.97/ 0.17 XC6SLX150 N/A 1.62/ 0.40 1.82/ 0.40 XC6SLX150T 1.51/ 0.39 1.62/ 0.40 1.82/ 0.40 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 62 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 70: Global Clock Setup and Hold With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM XC6SLX4 in Source-Synchronous Mode N/A 1.02/ 0.69 1.11/ 0.69 ns XC6SLX9 N/A 1.01/ 0.70 1.10/ 0.70 ns XC6SLX16 N/A 0.92/ 0.57 1.04/ 0.60 ns XC6SLX25 N/A 0.90/ 0.77 1.01/ 0.77 ns XC6SLX25T 0.94/ 0.76 0.94/ 0.77 1.01/ 0.77 XC6SLX45 N/A 0.90/ 0.76 0.98/ 0.79 XC6SLX45T 0.87/ 0.73 0.90/ 0.76 0.98/ 0.79 XC6SLX75 N/A 1.06/ 0.72 1.15/ 0.72 XC6SLX75T 1.03/ 0.71 1.06/ 0.72 1.15/ 0.72 XC6SLX100 N/A 0.81/ 0.76 0.94/ 0.76 XC6SLX100T 0.86/ 0.75 0.86/ 0.76 0.94/ 0.76 XC6SLX150 N/A 0.69/ 0.99 0.79/ 0.99 XC6SLX150T 0.66/ 0.98 0.69/ 0.99 0.79/ 0.99 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 63 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XC6SLX4 N/A 2.07/ 0.19 2.07/ 0.19 ns XC6SLX9 N/A 2.06/ 0.20 2.06/ 0.20 ns XC6SLX16 N/A 1.53/ 0.07 1.60/ 0.07 ns XC6SLX25 N/A 1.71/ 0.28 1.91/ 0.28 ns XC6SLX25T 1.70/ 0.28 1.71/ 0.28 1.91/ 0.28 XC6SLX45 N/A 1.64/ 0.18 1.75/ 0.18 XC6SLX45T 1.57/ 0.18 1.64/ 0.18 1.75/ 0.18 XC6SLX75 N/A 1.89/ 0.21 2.13/ 0.21 XC6SLX75T 1.80/ 0.21 1.89/ 0.21 2.13/ 0.21 XC6SLX100 N/A 1.52/ 0.32 1.70/ 0.32 XC6SLX100T 1.51/ 0.32 1.52/ 0.32 1.70/ 0.32 XC6SLX150 N/A 1.48/ 0.49 1.67/ 0.49 XC6SLX150T 1.41/ 0.49 1.48/ 0.49 1.67/ 0.49 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 64 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 72: Global Clock Setup and Hold With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XC6SLX4 N/A 0.88/ 0.92 0.91/ 1.03 ns XC6SLX9 N/A 0.87/ 0.93 0.89/ 1.02 ns XC6SLX16 N/A 0.37/ 0.82 0.51/ 0.94 ns XC6SLX25 N/A 0.76/ 1.06 0.79/ 1.06 ns XC6SLX25T 0.83/ 1.06 0.83/ 1.06 0.83/ 1.06 XC6SLX45 N/A 0.65/ 1.10 0.65/ 1.18 XC6SLX45T 0.59/ 1.06 0.65/ 1.10 0.65/ 1.18 XC6SLX75 N/A 0.87/ 1.04 0.90/ 1.04 XC6SLX75T 0.88/ 1.04 0.88/ 1.04 0.90/ 1.04 XC6SLX100 N/A 0.54/ 1.13 0.55/ 1.13 XC6SLX100T 0.61/ 1.13 0.61/ 1.13 0.61/ 1.13 XC6SLX150 N/A 0.51/ 1.31 0.52/ 1.31 XC6SLX150T 0.52/ 1.31 0.52/ 1.31 0.52/ 1.31 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 65 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 73: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode and PLL in DCM2PLL Mode. XC6SLX4 N/A 2.06/ 0.87 2.30/ 0.87 ns XC6SLX9 N/A 2.05/ 0.88 2.29/ 0.88 ns XC6SLX16 N/A 1.49/ 0.18 1.62/ 0.18 ns XC6SLX25 N/A 1.65/ 0.42 1.83/ 0.42 ns XC6SLX25T 1.69/ 0.42 1.69/ 0.42 1.83/ 0.42 XC6SLX45 N/A 1.59/ 0.39 1.75/ 0.39 XC6SLX45T 1.57/ 0.39 1.59/ 0.39 1.75/ 0.39 XC6SLX75 N/A 1.80/ 0.41 1.99/ 0.41 XC6SLX75T 1.74/ 0.41 1.80/ 0.41 1.99/ 0.41 XC6SLX100 N/A 1.46/ 0.51 1.64/ 0.51 XC6SLX100T 1.46/ 0.51 1.46/ 0.51 1.64/ 0.51 XC6SLX150 N/A 1.40/ 0.69 1.55/ 0.69 XC6SLX150T 1.35/ 0.69 1.40/ 0.69 1.55/ 0.69 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 66 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 74: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -4 -3 -2 -1L Units Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics, page 19. TPSDCMPLL_0/ TPHDCMPLL_0 No Delay Global Clock and IFF (2) with DCM XC6SLX4 in Source-Synchronous Mode and PLL in DCM2PLL Mode. XC6SLX9 N/A 1.11/ 1.38 1.21/ 1.38 ns N/A 1.10/ 1.38 1.20/ 1.39 ns XC6SLX16 N/A 0.83/ 1.12 0.83/ 1.21 ns XC6SLX25 N/A 0.76/ 1.11 0.84/ 1.18 ns XC6SLX25T 0.84/ 1.02 0.84/ 1.11 0.84/ 1.18 XC6SLX45 N/A 0.65/ 1.04 0.71/ 1.12 XC6SLX45T 0.68/ 1.00 0.68/ 1.04 0.71/ 1.12 XC6SLX75 N/A 0.88/ 1.06 0.94/ 1.14 XC6SLX75T 0.89/ 1.03 0.89/ 1.06 0.94/ 1.14 XC6SLX100 N/A 0.56/ 1.10 0.61/ 1.17 XC6SLX100T 0.63/ 1.10 0.63/ 1.10 0.63/ 1.17 XC6SLX150 N/A 0.47/ 1.28 0.53/ 1.28 XC6SLX150T 0.50/ 1.28 0.50/ 1.28 0.52/ 1.28 N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 67 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA source-synchronous transmitter and receiver data-valid windows. Table 75: Duty Cycle Distortion and Clock-Tree Skew Symbol TDCD_CLK TCKSKEW TDCD_BUFIO2 TBUFIOSKEW Description Device(1) Global Clock Tree I/O clock tree duty cycle distortion I/O clock tree skew across one clock region -1L Units -4 -3 -2 N/A 0.20 0.20 LXT Family 0.20 0.20 0.20 XC6SLX4 N/A 0.16 0.16 ns XC6SLX9 N/A 0.16 0.16 ns XC6SLX16 N/A 0.15 0.15 ns XC6SLX25 N/A 0.26 0.26 ns XC6SLX25T 0.26 0.26 0.26 XC6SLX45 N/A 0.20 0.20 XC6SLX45T 0.20 0.20 0.20 XC6SLX75 N/A 0.56 0.56 XC6SLX75T 0.56 0.56 0.56 XC6SLX100 N/A 0.22 0.22 XC6SLX100T 0.22 0.22 0.22 XC6SLX150 N/A 0.48 0.48 XC6SLX150T 0.39 0.48 0.48 LX Family N/A 0.25 0.25 LXT Family 0.25 0.25 0.25 LX Family N/A 0.06 0.06 LXT Family 0.06 0.06 0.06 Global Clock Tree Duty Cycle Distortion(2) LX Family Skew(3) Speed Grade ns N/A N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns N/A ns Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 3. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 68 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 76: Package Skew Symbol TPKGSKEW Description Package Device Skew(1)(2) Package(3) Value TQG144 XC6SLX4 ps CPG196 23 ps CSG225 58 ps TQG144 CPG196 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T DS162 (v1.9) August 23, 2010 Advance Product Specification Units ps 23 ps CSG225 58 ps FT(G)256 88 ps CSG324 64 ps CPG196 19 ps CSG225 70 ps FT(G)256 71 ps CSG324 54 ps FT(G)256 90 ps CSG324 61 ps FG(G)484 84 ps CSG324 48 ps FG(G)484 112 ps CSG324 70 ps CSG484 99 ps FG(G)484 109 ps FG(G)676 138 ps CSG324 75 ps CSG484 100 ps FG(G)484 95 ps CSG484 101 ps FG(G)484 107 ps FG(G)676 161 ps CSG484 107 ps FG(G)484 110 ps FG(G)676 134 ps CSG484 95 ps FG(G)484 155 ps FG(G)676 144 ps CSG484 88 ps FG(G)484 111 ps FG(G)676 147 ps FG(G)900 134 ps www.xilinx.com 69 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 76: Package Skew (Cont’d) Symbol TPKGSKEW Description Device Package Skew(1) XC6SLX150 XC6SLX150T Package(3) Value Units CSG484 84 ps FG(G)484 103 ps FG(G)676 115 ps FG(G)900 121 ps CSG484 83 ps FG(G)484 88 ps FG(G)676 141 ps FG(G)900 120 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. 3. Some of these devices are available in both Pb and Pb-free (additional G) packages as standard ordering options. Table 77: Sample Window Symbol Device(1) Description Speed Grade -4 -3 -2 -1L Units TSAMP Sampling Error at Receiver Pins(2) All 510 510 560 ps TSAMP_BUFIO2 Sampling Error at Receiver Pins using BUFIO2(3) All 430 430 480 ps Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 3. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO2 clock network and IODELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 70 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 78: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2 Symbol Description Device Speed Grade -4 -3 -2 -1L Units Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO2 TPSCS/TPHCS IFF setup/hold using BUFIO2 clock XC6SLX4 N/A 0.86/ 0.23 1.01/ 0.35 ns XC6SLX9 N/A 0.73/ 0.44 0.83/ 0.57 ns XC6SLX16 N/A 0.55/ 0.75 0.69/ 0.83 ns XC6SLX25 N/A 0.28/ 1.12 0.28/ 1.24 ns XC6SLX25T 0.28/ 1.08 0.28/ 1.12 0.28/ 1.24 ns XC6SLX45 N/A 0.44/ 1.29 0.50/ 1.40 ns XC6SLX45T 0.42/ 1.23 0.44/ 1.29 0.50/ 1.40 XC6SLX75 N/A 0.38/ 1.63 0.38/ 1.84 XC6SLX75T 0.38/ 1.53 0.38/ 1.63 0.38/ 1.84 XC6SLX100 N/A 0.06/ 1.63 0.06/ 1.87 XC6SLX100T 0.06/ 1.54 0.06/ 1.63 0.06/ 1.87 XC6SLX150 N/A 0.04/ 1.75 0.04/ 1.98 XC6SLX150T 0.04/ 1.73 0.04/ 1.75 0.04/ 1.98 XC6SLX4 N/A 5.16 6.15 ns XC6SLX9 N/A 5.38 6.41 ns XC6SLX16 N/A 5.70 6.67 ns XC6SLX25 N/A 6.00 7.02 ns XC6SLX25T 5.53 6.00 7.02 ns XC6SLX45 N/A 6.18 7.22 ns XC6SLX45T 5.76 6.18 7.22 XC6SLX75 N/A 6.46 7.57 XC6SLX75T 5.94 6.46 7.57 XC6SLX100 N/A 6.53 7.60 XC6SLX100T 6.09 6.53 7.60 XC6SLX150 N/A 6.69 7.81 XC6SLX150T 6.29 6.69 7.81 N/A ns ns N/A ns ns N/A ns ns N/A ns Pin-to-Pin Clock-to-Out Using BUFIO2 TICKOFCS OFF clock-to-out using BUFIO2 clock DS162 (v1.9) August 23, 2010 Advance Product Specification N/A ns ns N/A ns ns N/A ns ns N/A ns www.xilinx.com 71 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version 06/24/09 1.0 Initial Xilinx release. 08/26/09 1.1 Added VFS to Table 1and Table 2. Added RFUSE to Table 2. Added XC6SLX75 and XC6SLX75T to VBATT and IBATT in Table 1, Table 2, and Table 4. Corrected the quiescent supply current for the XC6SLX4 in Table 5. Updated Table 11. Removed DVPPIN from Figure 2. Removed FPCIECORE from Table 24 and added values to FPCIEUSER. Added more networking applications to Table 25. Updated values for TSUSPENDLOW_AWAKE, TSUSPEND_ENABLE, and TSCP_AWAKE in Table 45. Numerous changes to Table 46, page 45 including the addition of new values to various specifications, revising the TSMCKCSO description, and changing the units of TPOR. Also, removed Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK section from Table 46 and updated all the notes. In Table 50, added to FINMAX, revised FOUTMAX, and removed PLL Maximum Output Frequency for BUFIO2. Revised values for DCM_DELAY_STEP in Table 52. Updated CLKIN_FREQ_FX values in Table 53. 01/04/10 1.2 Added -4 speed grade to entire document. Updated speed specification of -4, -3, -2 speed grades to version 1.03. Added -1L speed grade numbers per speed specification 1.00. Updated TSOL in Table 1. Added -1L rows for LVCMOS12, LVCMOS15, and LVCMOS18 in Table 9. Revised much of the detail in GTP Transceiver Specifications in Table 12 through Table 23. Added -2 data to Table 25. Updated FMAX in Table 43. Updated descriptions for TDNACLKL and TDNACLKH in Table 44 and revised values for all parameters. Removed TINITADDR from Table 46 and added new data. Updated values in Table 47 through Table 60. Added Table 49 (BUFPLL) and Table 55 (DCM_CLKGEN). Removed TLOCKMAX note from Table 50. Updated note 3 in Table 51. In Table 76: removed XC6SLX75CSG324 and XC6SLX75TCSG324; added XC6SLX75FG(G)484 and XC6SLX75FG(G)484. 02/22/10 1.3 Production release of XC6SLX16 -2 speed grade devices. The changes to Table 26 and Table 27 includes updating this data sheet to the data in ISE v11.5 software with speed specification v1.06. Updated maximum of VIN and VTS and note 2 in Table 1. In Table 2, changed VIN, added IIN and note 5, revised notes 1, 6, and 7, and added note 8 to RFUSE. In Table 4, removed previous note 1 and added data to IRPU, IRPD, and IBATT, changed CIN, added RDT and RIN_TERM, and added note 2 and 3. Updated VCCO2 in Table 6. Added Table 7 and Table 8. Removed PCI66_3 from Table 9. Updated PCI33_3 and I2C in Table 9. Updated the description of Table 11. Completely updated Table 25. Updated Table 28 including adding values for PCI33_3. Updated VREF value for HSTL_III_18 in Table 30. Updates missing VREF values in Table 31. Added Simultaneously Switching Outputs, page 27. Removed TGSRQ and TRPW from Table 34 and Table 35. Also removed TDOQ from Table 35. Removed TISDO_DO and note 1 from Table 36. Removed TOSCCK_S and combinatorial section from Table 37. In Table 38, removed TIODDO_T and added new tap parameters and note 2. In Table 39, Table 40, and Table 41, made typographical edits and removed notes. Removed clock CLK section in Table 40. Removed clock CLK section and TREG_MUX and TREG_M31 in Table 41. Added block RAM FMAX values to Table 42. Updated values and added note 2 to Table 44. Added values to Table 45 and removed note 1. Numerous changes to Table 46. Completely updated Table 55. Revised data in Table 60. Removed note 3 from Table 68. Added values to Table 76. Added data to Table 77 and Table 78. 03/10/10 1.4 Production release of XC6SLX45 -2 speed grade devices, which includes changes to Table 26 and Table 27 updating this data sheet to the data in ISE v11.5 software with speed specification v1.07. Fixed RIN_TERM description in Table 4. Added PCI66_3 to Table 7 and replaced note 1. Corrected note 1 and the V, Max for TMDS_33 in Table 8. In Table 10, added note 1 to LVPECL_33 and TMDS_33. Also updated specifications for TMDS_33. Updated the GTP Transceiver Specifications section including adding values to Table 16, Table 17, and Table 20 through Table 23. Added PCI66_3 back into Table 9, Table 28, Table 30, Table 31, and Table 33. Updated note 3 on Table 31. In Table 33, corrected some typographical errors and fixed SSO limits for bank1/3 in FG(G)484 package. Corrected TOSCKC_OCE in Table 37. In Table 55, updated CLKFX_FREEZE_VAR and CLKFX_FREEZE_TEMP_SLOPE and added typical values to TCENTER_LOW_SPREAD and TCENTER_HIGH_SPREAD. Updated and added values to Table 61 through Table 75, and Table 78. In Table 76, revised the XC6SLX16-CSG324 and the XC6SLX45-CSG484 and FG(G)484 values. DS162 (v1.9) August 23, 2010 Advance Product Specification Description of Revisions www.xilinx.com 72 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Date Version Description of Revisions 06/14/10 1.5 In Table 2, added note 5 and added temperature range to VFS and RFUSE. Removed speed grade delineation, revised IRPD description, and updated note 2 in Table 4. Added note 2 to Table 7. Added DIFF_MOBILE_DDR to Table 8 and Table 10. Added note 4 to Table 15. Changed minimum DVPPIN in Table 16. Updated FGTPDRPCLK in Table 19. Increased maximum TLLSKEW in Table 22. Updated descriptions and added data to Table 23. Removed note 1 and added new data to the Networking Applications section in Table 25. Updated Table 26 and Table 27 to the data in ISE v12.1 software with speed specification v1.08. In Table 28, added DIFF_MOBILE_DDR and updated -4 speed grade data. Updated the maximum I/O pairs per bank in Table 32. Updated note 2 on Table 38. Revised the FMAX in Table 43. In Table 46, updated description for TSMCKCSO, revised values for TPOR and added Min value, added TBPIICCK and TSPIICCK. Also in Table 46, added device dependencies to FSMCCK and FRBCCK. Updated and added data to Table 61 through Table 75, and Table 78. In Table 76, added data on the XC6SLX45-FG(G)676 and revised the XC6SLX45T and XC6SLX150T values. The following changes to this specification are addressed in the product change notice XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs. In Table 2, revised the VCCINT to add the memory controller block extended performance specifications. In Table 25, changed the standard specifications and added extended performance specifications for the memory controller block and note 2. Added Note 4 and updated values in Table 33. 06/24/10 1.6 Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed grade) devices which includes changes to Table 26 and Table 27 (ISE v12.1 software with speed specification v1.08). Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB functionality (specifications are identical to the -3 speed grade). This includes changes to Table 2 (note 2), Table 25 (note 4), and Switching Characteristics (Table 26). Updated Simultaneously Switching Outputs discussion. Added -3 speed grade values for TTAP and FMINCAL values in Table 38. In Table 39, updated TRPW (-2 and -3 speed grade) values and FTOG (-3 speed grade) values. In Table 47, updated TGIO (-2 and -3 speed grade) values. Updated -3 values in spread spectrum section of Table 55. 07/16/10 1.7 Production release of specific devices listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added Note 3 advising designers of the patch which contains v1.11. Also updated the -1L speed specification to v1.04. Updated numerous -4 and -1L values. Added -4 TTAP values and FMINCAL to Table 38. Revised TCINCK/TCKCIN in Table 39. In Table 40, revised TSHCKO. In Table 41, revised TREG. Added new -1L values to Table 46. Added and updated values in Table 76. 07/26/10 1.8 Production release of XC6SLX25, XC6SLX25T, XC6SLX100 and XC6SLX100T in the specific speed grades listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added note 7 to Table 2 and moved VFS and RFUSE to a new Table 3. Added IHS and Note 4 to Table 4. Added note 1 to Table 28. Added and updated SSO limits per VCCO/GND pairs in Table 33. Added note 3 to Table 46. In Table 52, removed -1L specifications for CLKOUT_PER_JITT_DV1/2 and revised CLKIN_CLKFB_PHASE and CLKOUT_PHASE_DLL values. Updated note 3 in both Table 54 and Table 55. 08/23/10 1.9 Updated values for FGTPRANGE1, FGTPRANGE2, and FGPLLMIN in Table 18. Revised -3 and -4 values in Table 21. Removed the -1L speed grade readback support restriction and Note 3 in Table 46. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS162 (v1.9) August 23, 2010 Advance Product Specification www.xilinx.com 73