PSMN012-100YL N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 16 October 2015 Preliminary data sheet 1. General description Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS technology. This product is designed and qualified for use in a wide range of power supply & motor control equipment. 2. Features and benefits • • • • Advanced TrenchMOS provides low RDSon and low gate charge Logic level gate operation Avalanche rated, 100 % tested LFPAK provides maximum power density in a Power SO8 package 3. Applications • • • • • Synchronous rectification in power supply equipment Chargers & adaptors with Vout < 10 V Fast charge & USB-PD applications Battery powered motor control LED lighting & TV backlight 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 85 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 238 W Tj junction temperature -55 - 175 °C - 9.1 11.9 mΩ - 118 - nC - 24 - nC Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 11 Dynamic characteristics QG(tot) total gate charge VGS = 10 V; ID = 25 A; VDS = 80 V; Tj = 25 °C; Fig. 13; Fig. 14 QGD gate-drain charge VGS = 5 V; ID = 25 A; VDS = 80 V; Tj = 25 °C; Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit - - 139 mJ Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy [1] [2] ID = 85 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN012-100YL Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 238 W ID drain current Tmb = 25 °C; VGS = 5 V; Fig. 2 - 85 A Tmb = 100 °C; VGS = 5 V; Fig. 2 - 60 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 - 339 A IDM peak drain current PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Tstg Tj Conditions Min Max Unit storage temperature -55 175 °C junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 85 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 339 A - 139 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 85 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 Pder (%) 003aai835 100 ID (A) 80 80 60 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature PSMN012-100YL Preliminary data sheet 0 200 Fig. 2. 0 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 16 October 2015 50 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 003aai837 103 ID (A) Limit RDSon = VDS / ID 102 tp =10 µ s 100 µ s 10 10 ms 100 ms 10-1 10-1 Fig. 3. 1 ms DC 1 1 102 10 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aai836 103 IAL (A) 102 10 (1) (2) 1 (3) 10 Fig. 4. -1 10-3 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.63 K/W PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 4 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 1 Zth(j-mb) (K/W) 10-1 003aai463 δ = 0.5 0.2 0.1 0.05 0.02 single shot 10-2 P δ= tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V - - 2.45 V 0.5 - - V VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.08 10 µA VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 9.5 12 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; - 9.1 11.9 mΩ - - 33.1 mΩ - 118 - nC Static characteristics V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11 VGS = 5 V; ID = 25 A; Tj = 175 °C; Fig. 11; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 80 V; VGS = 10 V; Tj = 25 °C; Fig. 13; Fig. 14 PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit ID = 25 A; VDS = 80 V; VGS = 5 V; - 64 - nC Tj = 25 °C; Fig. 13; Fig. 14 - 13 - nC - 24 - nC QGS gate-source charge QGD gate-drain charge Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 5980 7973 pF Coss output capacitance Tj = 25 °C; Fig. 15 - 349 419 pF Crss reverse transfer capacitance - 214 293 pF td(on) turn-on delay time VDS = 80 V; RL = 3.2 Ω; VGS = 5 V; - 22 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C - 39 - ns td(off) turn-off delay time - 117 - ns tf fall time - 74 - ns Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.81 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 39 - ns Qr recovered charge VDS = 25 V; Tj = 25 °C - 65 - nC 003aai839 240 ID (A) VGS (V) = 10 4 RDSon (mΩ) 3.5 180 003aai840 30 20 3 120 2.8 10 60 0 2.6 2.4 2.2 0 1 2 3 V DS(V) 0 4 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values PSMN012-100YL Preliminary data sheet 0 2 6 8 VGS (V) 10 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 16 October 2015 4 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 003aai842 180 003aah025 3 VGS(th) (V) 2.5 ID (A) max 2 120 typ 1.5 Tj = 175 °C 0 Fig. 8. min 1 60 0 1 0.5 Tj = 25 °C 2 3 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 9. 003aah026 10-1 0 60 120 003aai845 2.6 2.8 RDSon (mΩ) 10-2 min 10-3 typ 20 max 3 10 3.5 -4 10 10 180 Gate-source threshold voltage as a function of junction temperature 30 ID (A) Tj (° C) VGS (V) = 10 -5 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage PSMN012-100YL Preliminary data sheet 0 20 40 60 80 4.5 ID (A) 100 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 003aaj820 3 003aai847 10 VGS (V) a 2.4 8 1.8 6 1.2 4 0.6 2 0 -60 0 60 120 Tj ( °C) 0 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature VDS = 14V 0 VDS = 80V 40 80 ID 120 Fig. 13. Gate-source voltage as a function of gate charge; typical values 003aai848 104 VDS QG (nC) Ciss C (pF) VGS(pl) 103 VGS(th) VGS C oss QGS2 QGS1 QGS QGD QG(tot) Crss 003aaa508 Fig. 14. Gate charge waveform definitions 102 10-1 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 003aai849 80 IS (A) 60 40 20 Tj = 175°C 0 0 0.4 Tj = 25 °C 0.8 VSD(V) 1.2 Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 10. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 mm c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 11. Legal information 11.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 11.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. PSMN012-100YL Preliminary data sheet Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 11 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 12 / 13 PSMN012-100YL NXP Semiconductors N-channel 100 V, 12 mΩ logic level MOSFET in LFPAK56 12. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Limiting values .......................................................2 8 Thermal characteristics .........................................4 9 Characteristics ....................................................... 5 10 Package outline ................................................... 10 11 11.1 11.2 11.3 11.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 October 2015 PSMN012-100YL Preliminary data sheet All information provided in this document is subject to legal disclaimers. 16 October 2015 © NXP Semiconductors N.V. 2015. All rights reserved 13 / 13