PSMN019-100YL N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 2 June 2016 Product data sheet 1. General description Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS technology. This product is designed and qualified for use in a wide range of power supply & motor control equipment. 2. Features and benefits • • • • Advanced TrenchMOS provides low RDSon and low gate charge Logic level gate operation Avalanche rated, 100 % tested LFPAK provides maximum power density in a Power SO8 package 3. Applications • • • • • Synchronous rectification in power supply equipment Chargers & adaptors with Vout < 10 V Fast charge & USB-PD applications Battery powered motor control LED lighting & TV backlight 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 56 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 167 W VGS = 5 V; ID = 15 A; Tj = 25 °C; Fig. 11 - 14.6 19 mΩ ID = 15 A; VDS = 80 V; VGS = 5 V; - 14.1 - nC Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Tj = 25 °C; Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN019-100YL Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN019-100YL 19L100 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 167 W ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - 56 A VGS = 5 V; Tmb = 100 °C; Fig. 2 - 40 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 226 A -55 175 °C IDM peak drain current Tstg storage temperature PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Tj junction temperature Min Max Unit -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 56 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 226 A - 94.1 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 56 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 ID (A) Pder (%) 003aai925 60 50 40 80 30 20 40 10 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature PSMN019-100YL Product data sheet 0 200 Fig. 2. 0 40 120 160 Tmb (°C) 200 Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 2 June 2016 80 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 ID (A) 003aai927 103 Limit RDSon = VDS / ID 102 tp = 10 us 100 us 10 DC 1 1 ms 10 ms 100 ms 10-1 Fig. 3. 1 102 10 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage IAL (A) 003aai926 102 10 (1) (2) 1 (3) 10-1 10-3 Fig. 4. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.9 K/W PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 1 Zth(j-mb) (K/W) 003aai928 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P 10-2 δ= tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; 1.4 1.7 2.1 V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9 - - 2.45 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9 0.5 - - V VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.04 10 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 15 A; Tj = 25 °C; Fig. 11 - 14.6 19 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; - 14 18 mΩ - - 52.4 mΩ - 72.4 - nC ID = 15 A; VDS = 80 V; VGS = 5 V; - 39 - nC Tj = 25 °C; Fig. 13; Fig. 14 - 8.5 - nC Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 10 Fig. 11 VGS = 5 V; ID = 15 A; Tj = 175 °C; Fig. 11; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 15 A; VDS = 80 V; VGS = 10 V; Tj = 25 °C; Fig. 13; Fig. 14 QGS gate-source charge PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 14.1 - nC Ciss input capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; - 3814 5085 pF Tj = 25 °C; Fig. 15 Coss output capacitance - 222 266 pF Crss reverse transfer capacitance - 133 182 pF td(on) turn-on delay time VDS = 80 V; RL = 5 Ω; VGS = 5 V; - 18.5 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C - 36.8 - ns td(off) turn-off delay time - 59.6 - ns tf fall time - 34.3 - ns Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.8 1.2 V trr reverse recovery time IS = 15 A; dIS/dt = -100 A/µs; VGS = 0 V; - 38.7 - ns Qr recovered charge VDS = 25 V; Tj = 25 °C - 67.7 - nC 003aai929 150 ID (A) 003aai930 40 VGS (V) = 10 RDSon (mΩ) 4.5 3 30 2.8 20 2.6 10 100 50 0 2.4 2.2 0 1 2 3 VDS(V) 0 4 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values PSMN019-100YL Product data sheet 0 2 6 8 10 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 2 June 2016 4 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 003aai932 120 ID (A) 100 003aah025 3 VGS(th) (V) 2.5 max 80 2 typ 60 1.5 40 1 20 0 Fig. 8. 0.5 175°C 0 0.5 1 1.5 2 min Tj = 25°C 2.5 3 3.5 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 9. 003aah026 10-1 0 60 120 003aai935 RDSon 10-2 180 Gate-source threshold voltage as a function of junction temperature 40 ID (A) Tj (° C) VGS = 2.6 V 30 min 10-3 typ 2.8 V max 20 3V 10 3.5 V 4.5 V 10 V 10-4 10-5 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage PSMN019-100YL Product data sheet 0 10 20 30 40 50 ID (A) 60 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 003aaj820 3 003aai937 10 VGS (V) a 2.4 8 1.8 6 1.2 4 0.6 2 0 -60 0 60 120 Tj ( °C) 0 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature VDS = 14V 0 VDS = 80V 20 40 60 003aai938 Ciss C (pF) ID 80 Fig. 13. Gate-source voltage as a function of gate charge; typical values 104 VDS QG (nC) 103 VGS(pl) VGS(th) Coss VGS QGS2 QGS1 QGS 102 Crss QGD QG(tot) 003aaa508 10 10-1 Fig. 14. Gate charge waveform definitions 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 003aai939 100 IS (A) 80 60 40 20 0 Tj = 175 °C 0 0.2 0.4 Tj = 25 °C 0.6 0.8 1 VSD (V) Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 9 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 mm c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 10 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. 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The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 12 / 13 PSMN019-100YL NXP Semiconductors N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 June 2016 PSMN019-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 2 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 13 / 13