ESDAXLC6-1BT2Y Automotive single-line extra low capacitance Transil™, transient surge voltage suppressor (TVS) for ESD protection Datasheet − production data Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: • Automotive applications • Computers • Printers • Communication systems • Cellular phone handsets and accessories 62'7 • Video equipment Description Features The ESDAXLC6-1BT2Y is bidirectional single-line TVS diode designed to protect data lines or other I/O ports against ESD transients. • Single-line bidirectional protection • Breakdown voltage = 6 V min. This device is ideal for applications where both reduced line capacitance and power absorption capability are required. • Extra low diode capacitance = 0.4 pF • Lead-free package • ECOPACK®2 compliant Figure 1. Functional diagram • AEC-Q101 qualified Benefits 3LQ • Low capacitance for optimized data integrity • Low leakage current < 50 nA • Low PCB space consumption: 0.6 mm2 3LQ Complies with the following standards: • IEC 61000-4-2 (exceeds level 4) – 30 kV (air discharge) – 16 kV (contact discharge) • ISO10605: C = 330 pF, R = 330 Ω – 30 kV (air discharge) – 12 kV (contact discharge) • ISO 7637-3: – Pulse 3a: VS = -150 V – Pulse 3b: VS = +100 V TM: Transil is a trademark of STMicroelectronics November 2014 This is information on a product in full production. DocID026845 Rev 1 1/12 www.st.com Characteristics 1 ESDAXLC6-1BT2Y Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value IEC 61000-4-2: Contact discharge Air discharge VPP 16 30 Electrostatic ISO 10605 - C = 330 pF, R = 330 Ω : discharge capability Contact discharge Air discharge kV 12 30 MIL STD 883G - method 3015-7: Class3 PPP Peak pulse power dissipation (8/20 µs) IPP Peak pulse current (8/20 µs) Tj Unit 25 Tj initial = Tamb 40 W 1.3 A Operating junction temperature range - 55 to + 150 °C Tstg Storage temperature range - 65 to + 150 °C TL Maximum lead temperature for soldering during 10 s 260 °C Figure 2. Electrical characteristics (definitions) Symbol VBR VRM IRM IPP = = = = Parameter Breakdown voltage Stand-off voltage Leakage current @ VRM Peak pulse current Rd αT C = = = Dynamic impedance Voltage temperature coefficient Parasite capacitance Table 2. Electrical characteristics (values, Tamb = 25 °C) Symbol 2/12 Test condition VBR IR = 1 mA IRM VRM = 3 V Rd Dynamic resistance, pulse width 100 ns VCL Cline Min. Typ. Max. Unit 6 9 11 V 50 nA 0.25 Ω 8 kV contact discharge after 30 ns IEC 61000-4-2 37 V F = (200 MHz - 3000 MHz), VR = 0 V 0.4 DocID026845 Rev 1 0.5 pF ESDAXLC6-1BT2Y Characteristics Figure 3. Junction capacitance versus reverse voltage applied (typical values) $Q' Figure 4. Leakage current versus junction temperature (typical values) ,5Q$ 959 Figure 5. S21 attenuation measurement 7M& Figure 6. TLP measurements 6G% ,33$ )+] 0 0 * * * 9&/9 * DocID026845 Rev 1 3/12 12 Characteristics ESDAXLC6-1BT2Y Figure 7. ESD response to ISO 10605, C = 150 pF, R = 330 Ω (+8 kV contact) Figure 8. ESD response to ISO 10605, C = 150 pF, R = 330 Ω (-8 kV contact) 7EJW 7EJW OTEJW Figure 9. Response to ISO 7637-3 (pulse 3a) US = -150 V OTEJW Figure 10. Response to ISO 7637-3 (pulse 3b) US = +100 V 9GLY 9GLY P$GLY QVGLY P$GLY QVGLY 4/12 DocID026845 Rev 1 ESDAXLC6-1BT2Y 2 Package information Package information • Epoxy meets UL94, V0 • Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. SOD882T dimension definitions L1 L2 b1 b2 PIN # 1 ID e A A1 E D DocID026845 Rev 1 5/12 12 Package information ESDAXLC6-1BT2Y Table 3. SOD882T dimension values Dimensions Ref. Millimeters Min. Typ. Inches Max. Min. Typ. Max. A 0.30 0.40 0.012 0.016 A1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 Figure 12. SOD882T footprint in mm (inches) 0.55 (0.022) Figure 13. SOD882T marking 0.55 (0.022) 0.50 (0.020) 3LQ 8 3LQ 0.40 (0.016) Note: 6/12 Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. DocID026845 Rev 1 ESDAXLC6-1BT2Y Package information %DULQGLFDWHV3LQ 8 8 8 8 $OOGLPHQVLRQVDUHLQPP 8 8 Figure 14. SOD882T tape and reel specifications 8VH UGLUHF WLRQ RIXQ UHH OLQJ DocID026845 Rev 1 7/12 12 Recommendation on PCB assembly ESDAXLC6-1BT2Y 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 15. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 16. Recommended stencil window position in mm (inches) 0.55 (0.022) 0.50 (0.020) 0.474 (0.019) 0.013 0.013 (0.00051) (0.00051) 0.40 (0.016) 0.014 0.014 (0.00055) (0.00055) 0.522 (0.021) 8/12 DocID026845 Rev 1 Lead footprint on PCB Stencil window opening ESDAXLC6-1BT2Y 3.2 3.3 3.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. DocID026845 Rev 1 9/12 12 Recommendation on PCB assembly 3.5 ESDAXLC6-1BT2Y Reflow profile Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. 10/12 DocID026845 Rev 1 ESDAXLC6-1BT2Y 4 Ordering information Ordering information Figure 18. Ordering information scheme (6'$;/& %7< (6'DUUD\ ([WUDORZFDSDFLWDQFH %UHDNGRZQYROWDJH 9ROWVPLQ 1XPEHURIOLQHV 'LUHFWLRQDO % %LGLUHFWLRQDO 3DFNDJH 7 7KLQ62' $XWRPRWLYH Table 4. Ordering information Order code Marking(1) Package Weight Base qty Delivery mode ESDAXLC6-1BT2Y U SOD882T 0.80 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 5 Revision history Table 5. Document revision history Date Revision 03-Nov-2014 1 Changes Initial release. DocID026845 Rev 1 11/12 12 ESDAXLC6-1BT2Y IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 12/12 DocID026845 Rev 1