PSMN023-40YLC N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology 22 August 2012 Product data sheet 1. Product profile 1.1 General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits • High reliability Power SO8 package, qualified to 175°C • Low parasitic inductance • Optimised for 4.5V Gate drive utilising NextPower Superjunction technology • Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads 1.3 Applications • DC-to-DC converters • Load switching • Server power supplies • Synchronous buck regulator 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 1 - - 24 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 25 W Tj junction temperature -55 - 175 °C - 22 26 mΩ VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 19 23 mΩ VGS = 4.5 V; ID = 5 A; VDS = 20 V; - 0.9 - nC Static characteristics RDSon drain-source on-state resistance VGS = 4.5 V; ID = 5 A; Tj = 25 °C; Fig. 12 Dynamic characteristics QGD gate-drain charge Fig. 14; Fig. 15 Scan or click this QR code to view the latest information for this product PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit QG(tot) total gate charge VGS = 4.5 V; ID = 5 A; VDS = 20 V; - 4.3 - nC Fig. 14; Fig. 15 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 4 LFPAK; PowerSO8 (SOT669) 3. Ordering information Table 3. Ordering information Type number Package PSMN023-40YLC Name Description Version LFPAK; Power-SO8 plastic single-ended surface-mounted package; 4 leads SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 40 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 1 - 24 A VGS = 10 V; Tmb = 100 °C; Fig. 1 - 17 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4 - 97 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 25 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 100 - V PSMN023-40YLC Product data sheet MM (JEDEC JESD22-A115) All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 2 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Max Unit Source-drain diode IS source current Tmb = 25 °C - 23 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 97 A VGS = 10 V; Tj(init) = 25 °C; ID = 24 A; - 6.9 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Vsup ≤ 40 V; RGS = 50 Ω; unclamped; Fig. 3 003aaj904 30 ID (A) 03na19 120 Pder (%) 25 20 80 15 10 40 5 0 Fig. 1. 0 30 60 90 120 150 Tj (°C) Continuous drain current as a function of mounting base temperature IAL (A) 0 180 Fig. 2. 0 50 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature 003aaj905 102 10 (1) 1 (2) 10-1 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Single pulse avalanche rating; avalanche current as a function of avalanche time PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 3 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology ID (A) 003aaj906 102 Limit RDSon = VDS / ID tp = 10 us 10 100 us DC 1 1 ms 10 ms 100 ms 10-1 10-1 Fig. 4. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - 5.66 5.83 K/W 003aaj907 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 0.02 10-1 single shot P δ= tp 10-2 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 4 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.05 1.67 1.95 V 0.5 - - V - - 2.25 V VDS = 40 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 40 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 5 A; Tj = 25 °C; - 22 26 mΩ - - 44.5 mΩ VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 19 23 mΩ VGS = 10 V; ID = 5 A; Tj = 150 °C; - - 39.5 mΩ f = 1 MHz 0.85 1.7 3.4 Ω ID = 5 A; VDS = 20 V; VGS = 10 V; - 8.4 - nC - 4.3 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 8 - nC gate-source charge ID = 5 A; VDS = 20 V; VGS = 4.5 V; - 1.3 - nC QGS(th) pre-threshold gatesource charge Fig. 14; Fig. 15 - 0.7 - nC QGS(th-pl) post-threshold gatesource charge - 0.6 - nC QGD gate-drain charge - 0.9 - nC VGS(pl) gate-source plateau voltage - 2.5 - V Static characteristics V(BR)DSS VGS(th) Fig. 10 ID = 10 mA; VDS = VGS; Tj = 150 °C; Fig. 11 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 11 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 12 VGS = 4.5 V; ID = 5 A; Tj = 150 °C; Fig. 12; Fig. 13 Fig. 12; Fig. 13 RG gate resistance Dynamic characteristics QG(tot) total gate charge Fig. 14; Fig. 15 ID = 5 A; VDS = 20 V; VGS = 4.5 V; Fig. 14; Fig. 15 QGS PSMN023-40YLC Product data sheet ID = 5 A; VDS = 20 V; Fig. 14; Fig. 15 All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 5 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit Ciss input capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; - 520 - pF Coss output capacitance Tj = 25 °C; Fig. 16 - 110 - pF Crss reverse transfer capacitance - 40 - pF td(on) turn-on delay time VDS = 20 V; RL = 4 Ω; VGS = 4.5 V; - 6.2 - ns tr rise time RG(ext) = 5 Ω - 3.8 - ns td(off) turn-off delay time - 9.9 - ns tf fall time - 3.1 - ns Qoss output charge - 3.4 - nC VGS = 0 V; VDS = 20 V; f = 1 MHz; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.83 1.1 V trr reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V; - 12.9 - ns Qr recovered charge VDS = 20 V - 6.9 - nC ta reverse recovery rise time VGS = 0 V; IS = 5 A; dIS/dt = -100 A/µs; - 8.7 - ns - 4.2 - ns tb VDS = 20 V; Fig. 18 reverse recovery fall time ID (A) 003aaj908 25 4.5 V 10 V 3.5 V VGS = 3 V 20 15 003aaj909 100 RDSon (mΩ) 80 60 2.8 V 10 40 2.6 V 5 0 Fig. 6. 20 2.4 V 2.2 V 0 0.5 1 1.5 VDS (V) 0 2 Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values PSMN023-40YLC Product data sheet 0 2 6 8 10 12 14 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 22 August 2012 4 © NXP B.V. 2012. All rights reserved 6 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology gfs (S) 003aaj910 50 ID (A) 003aaj911 25 40 20 30 15 20 10 10 5 Tj = 25°C 150°C 0 Fig. 8. 0 5 10 15 20 ID (A) Forward transconductance as a function of drain current; typical values 003aaj912 10-1 ID (A) 0 25 Fig. 9. 0 0.5 1 1.5 2 2.5 3 3.5 VGS (V) Transfer characteristics; drain current as a function of gate-source voltage; typical values 003aaj913 3 VGS(th) (V) 2.5 10-2 4 Max(1mA) ID = 5mA 2 10-3 Min Typ Max 1.5 10-4 1mA 1 10-5 10-6 Min(5mA) 0.5 0 0.6 1.2 1.8 2.4 VGS (V) 0 -60 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage PSMN023-40YLC Product data sheet -30 0 30 60 90 120 150 Tj (°C) 180 Fig. 11. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 7 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology 003aaj914 50 RDSon 2.8 V 3V 003aaj915 2 a 10 V 1.6 40 VGS = 4.5 V 1.2 3.5 V 30 0.8 4.5 V 20 0.4 VGS = 10 V 10 0 5 10 15 20 ID (A) Fig. 12. Drain-source on-state resistance as a function of drain current; typical values VDS 0 -60 25 -30 0 30 60 90 120 150 Tj (°C) 180 Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature VGS (V) ID 003aaj916 10 8 VGS(pl) 6 VGS(th) 32V VGS 20 V 4 QGS1 QGS2 QGS VGS = 8 V QGD 2 QG(tot) 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 2 4 6 8 QG (nC) 10 Fig. 15. Gate-source voltage as a function of gate charge; typical values PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 8 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology 003aaj917 103 C (pF) IS (A) Ciss 003aaj918 25 20 15 Coss 102 10 Crss 5 150°C 10 10-1 1 10 VDS (V) 0 102 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) 1.2 Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values 003a a f 444 ID (A) trr ta tb 0 0.25 IR M IRM t (s ) Fig. 18. Reverse recovery timing definition PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 9 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology 7. Package outline Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b X c 1/2 e A (A 3) A1 C θ L detail X 0 2.5 y C 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-03-16 11-03-25 MO-235 Fig. 19. Package outline LFPAK; Power-SO8 (SOT669) PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 10 / 13 PSMN023-40YLC NXP Semiconductors N-channel 40 V 23mΩ logic level MOSFET in LFPAK using NextPower technology In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 8. Legal information 8.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. 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Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Limiting values .......................................................2 5 Thermal characteristics .........................................4 6 Characteristics ....................................................... 5 7 Package outline ................................................... 10 8 8.1 8.2 8.3 8.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP B.V. 2012. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 August 2012 PSMN023-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © NXP B.V. 2012. All rights reserved 13 / 13