1EDI EiceDRIVER™ Compact 1EDI20N12AF Single Channel MOSFET and GaN HEMT Gate Driver IC 1EDI20N12AF Data Sheet Rev. 2.0, 2015-06-01 Industrial Power Control Edition 2015-06-01 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 1EDI EiceDRIVER™ Compact 1EDI20N12AF Revision History Page or Item Subjects (major changes since previous revision) Rev. 2.0, 2015-06-01 p17 dynamic parameter update Rev. 1.03, 2014-10-14 all pages parameter completion Rev. 1.02, 2014-02-14 p8 application diagram Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. 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MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 Data Sheet 3 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 3.1 3.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 13 13 13 13 5 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 15 15 16 16 17 17 18 6 Timing Diagramms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 8.1 8.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Sheet 4 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Data Sheet Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram 1EDI20N12AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PG-DSO-8-51 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application Example Bipolar Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application Example Unipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Propagation Delay, Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical Switching Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UVLO Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PG-DSO-8-51 (Plastic (Green) Dual Small Outline Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference Layout for Thermal Data (Copper thickness 35 μm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Data Sheet Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 14 15 15 16 16 17 17 18 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact Single Channel MOSFET and GaN HEMT Gate Driver IC 1 1EDI20N12AF Overview Main Features • • • • • Single channel isolated Gate Driver Input to output isolation voltage up to 1200 V For high voltage power FETs 4 A typical peak current at rail-to-rail outputs Separate source and sink outputs Product Highlights • • • • • Galvanically isolated Coreless Transformer Driver Low input to output capacitive coupling Suitable for operation at high ambient temperature Wide input voltage operating range ideally suited for driving cascoded or normally-off Gallium Nitride HEMTs ED- Compact Typical Application • • • • • • AC and Brushless DC Motor Drives High Voltage PFC, DC/DC-Converter and DC/AC-Inverter Induction Heating Resonant Application UPS-Systems Welding Solar MPPT boost converter Description The 1EDI20N12AF is a galvanically isolated single channel FET driver in a PG-DSO-8-51 package that provides output currents of at least 2 A at separated output pins. The input logic pins operate on a wide input voltage range from 3 V to 15 V using CMOS threshold levels to support even 3.3 V microcontroller. Data transfer across the isolation barrier is realized by the Coreless Transformer Technology. The undervoltage lockout (UVLO) functions for both input and output chip and an active shutdown feature are included to always guarantee safe operation. Product Name Gate Drive Current (min) Package 1EDI20N12AF ±2.0 A MOSFET level optimized PG-DSO-8-51 Data Sheet 7 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Overview VCC1 VCC2,H OUT+ IN+ EiceDRIVERTM IN- 1EDI20N12AF OUTDC GND1 GND2,H VCC1 VCC2,L Control OUT+ IN+ EiceDRIVERTM IN- 1EDI20N12AF OUTDC GND1 Figure 1 Data Sheet GND2,L Typical Application 8 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Block Diagram 2 Block Diagram VCC1 1 UVLO UVLO 5 VCC2 6 OUT+ 7 OUT- 8 GND2 VCC2 IN+ 2 input filter GND1 & active filter & TX RX VCC1 IN- 3 GND1 4 Figure 2 Data Sheet Shoot through protection input filter Block Diagram 1EDI20N12AF 9 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Pin Configuration and Functionality 3 Pin Configuration and Functionality 3.1 Pin Configuration Table 1 Pin Configuration Pin No. Name Function 1 VCC1 Positive Logic Supply 2 IN+ Non-Inverting Driver Input (active high) 3 IN- Inverting Driver Input (active low) 4 GND1 Logic Ground 5 VCC2 Positive Power Supply Output Side 6 OUT+ Driver Source Output 7 OUT- Driver Sink Output 8 GND2 Power Ground 1 VCC1 GND2 8 2 IN+ OUT- 7 3 IN- OUT+ 6 4 GND1 VCC2 5 Figure 3 PG-DSO-8-51 (top view) 3.2 Pin Functionality VCC1 Logic input supply voltage with wide operating range (3.3 V o 15 V). IN+ Non Inverting Driver Input IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN- = low) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal pull-down-resistor favors off-state. Data Sheet 10 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Pin Configuration and Functionality IN- Inverting Driver Input IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN+ = high) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN-. An internal pull-up-resistor favors off-state. GND1 Ground connection of input circuit. VCC2 Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this supply pin. OUT+ Driver Source Output Driver output pin sourcing current to turn on external switch transistor. During on-state the driving output is switched to VCC2. Switching of this output is controlled by IN+ and IN-, resp.. This output will also be turned off at an UVLO event. During turn off the OUT+ terminal is able to sink approx. 100 mA. OUT- Driver Sink Output) Driver output pin sinking current to turn off external switch transistor. During off-state the driving output is switched to GND2. Switching of this output is controlled by IN+ and IN-, resp.. In case of UVLO an active shut down keeps the output low. GND2 Reference Ground Reference ground of the output driving circuit. In case of a bipolar supply (positive and negative voltage with respect to switch source potential) this pin is connected to the negative supply voltage. Data Sheet 11 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Functional Description 4 Functional Description 4.1 Introduction The 1EDI EiceDRIVER™ Compact is a general purpose gate driver. Basic control and protection features support fast and easy design of highly reliable systems. The galvanic isolation between input logic and driver output is achieved by utilizing on-chip Coreless Transformer Technology. The wide input range supports the direct connection of various signal sources like DSPs and microcontrollers. The separated rail-to-rail driver outputs simplify gate resistor selection, save an external high current bypass diode and improve dV/dt control. +5V VCC1 +12V VCC2 1µ 100n 10R SGND OUT+ GND1 IN 3R3 OUT- IN+ IN- Figure 4 Application Example Bipolar Supply 4.2 Supply GND2 0V 1µ -8V The driver can operate over a wide supply voltage range, either unipolar or bipolar. With bipolar supply the driver is typically operated with a positive voltage of 12 V at VCC2 and a negative voltage of -8V at GND2 relative to the source potential as seen in Figure 4. Negative supply can help to prevent a dynamic turn on. For unipolar supply configuration the driver is typically supplied with a positive voltage of 12 V at VCC2. In this case, careful evaluation for turn off gate resistor selection is recommended to avoid dynamic turn on (see Figure 5). +5V VCC1 VCC2 1µ 10R 100n SGND IN Figure 5 Data Sheet +12V OUT+ GND1 3R3 IN+ OUT- IN- GND2 Application Example Unipolar Supply 12 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Functional Description 4.3 Protection Features 4.3.1 Undervoltage Lockout (UVLO) To ensure correct switching the device is equipped with an undervoltage lockout for input and output independently. Operation starts only after both VCC levels have increased beyond the respective VUVLOH levels (see also Figure 8). If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The switch is turned off and the signals at IN+ and IN- are ignored until VVCC1 reaches the power-up voltage VUVLOH1 again. If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the switch is again turned off and signals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again. Note: VVCC2 is always referred to GND2; the output UVLO function thus depends on the total supply voltage. 4.3.2 Active Shut-Down The Active Shut-Down feature ensures a safe off-state if the output chip is not connected to the power supply, The gate is clamped at OUT- to GND2. 4.3.3 Short Circuit Clamping During short circuit the gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT+ limits this voltage to a value slightly higher than the supply voltage. A maximum current of 500 mA may be fed back to the supply through this path for 10 μs. If higher currents are expected or tighter clamping is desired external Schottky diodes may be added. 4.4 Non-Inverting and Inverting Inputs There are two possible input modes to control the switch. In the non-inverting mode IN+ controls the driver output while IN- is set to low. In the inverting mode IN- controls the driver output while IN+ is set to high, see Figure 7. A minimum input pulse width is required to filter occasional glitches. 4.5 Driver Outputs The output driver section uses MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the driver’s supply is stable. Due to the low internal voltage drop, switching behaviour is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated in the driver. Data Sheet 13 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters 5 Electrical Parameters 5.1 Absolute Maximum Ratings Note: Absolute maximum ratings are defined as absolute limits, i.e. exceeding them may lead to destruction of the integrated circuit. Table 2 Absolute Maximum Ratings Parameter Symbol Values Min. Max. 40 Unit Note / Test Condition Power supply output side VVCC2 -0.3 V 1) Gate driver output VOUT VGND2-0.3 VVCC2+0.3 V – Positive power supply input side VVCC1 -0.3 18.0 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 18.0 V – Input to output isolation voltage VISO -1200 1200 V Junction temperature TJ -40 150 °C – Storage temperature TS -55 150 °C – Power dissipation (Input side) PD, IN – 25 mW 2) @TA = 25°C mW 2) @TA = 25°C K/W 2) @TA = 85°C @TA = 85°C Power dissipation (Output side) Thermal resistance (Input side) PD, OUT RTHJA,IN – – 400 145 Thermal resistance (Output side) RTHJA,OUT – 165 K/W 2) ESD capability VESD,HBM – 2 kV Human Body Model3) 1) With respect to GND2. 2) See Figure 10 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. 3) According to EIA/JESD22-A114-C (discharging a 100 pF capacitor through a 1.5 kΩ series resistor). Data Sheet 14 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters 5.2 Operating Parameters Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. Table 3 Operating Parameters Parameter Symbol Values Min. Max. Unit Note / Test Condition Power supply output side VVCC2 10 35 V 1) Power supply input side VVCC1 3.1 17 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 17 V – Switching frequency fsw – 4.0 MHz 2) 3) Ambient temperature TA -40 125 °C – Thermal coefficient, junction-top Ψth,jt – 4.8 K/W 3) @TA = 85°C kV/μs 3) @ 1000 V Common mode transient immunity (CMTI) |dVISO/dt| – 100 1) With respect to GND2. 2) do not exceed max. power dissipation 3) Parameter is not subject to production test - verified by design/characterization 5.3 Electrical Characteristics Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 5 to 7). 5.3.1 Voltage Supply Table 4 Voltage Supply Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition UVLO threshold input chip VUVLOH1 – 2.85 3.1 V – VUVLOL1 2.55 2.75 – V – UVLO hysteresis input chip (VUVLOH1 - VUVLOL1) VHYS1 90 100 – mV – UVLO threshold output chip (MOSFET Supply) VUVLOH2 – 9.1 10.0 V – VUVLOL2 8.0 8.5 – V – UVLO hysteresis output chip (VUVLOH2 - VUVLOL2) VHYS2 550 600 – mV – Data Sheet 15 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Table 4 Voltage Supply (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IQ1 – 0.65 1.0 mA VVCC1 = 5 V IN+ = High, IN- = Low =>OUT = High Quiescent current output IQ2 chip – 1.2 2.0 mA VVCC2 = 15 V IN+ = High, IN- = Low =>OUT = High Unit Note / Test Condition Quiescent current input chip 5.3.2 Logic Input Note: Unless stated otherwise VCC1 = 5.0V Table 5 Logic Input Parameter Symbol Values Min. Typ. Max. IN+,IN- low input voltage VIN+L,VIN-L – – 30 % of VCC1 IN+,IN- high input voltage VIN+H,VIN-H 70 – – % of VCC1 IN+,IN- low input voltage VIN+L,VIN-L – – 1.5 V – IN+,IN- high input voltage VIN+H,VIN-H 3.5 – – V – IN- input current IIN- – 70 200 μA VIN- = GND1 IN+ input current IIN+ – 70 200 μA VIN+ = VCC1 Unit Note / Test Condition A 1) 5.3.3 Gate Driver Table 6 Gate Driver Parameter Symbol Values Min. High level output peak current (source) 1EDI20N12AF IOUT+,PEAK Low level output peak current (sink) 1EDI20N12AF IOUT-,PEAK Typ. Max. – 2.0 IN+ = High, IN- = Low, VVCC2 = 15 V 4.0 – 2.0 3.5 A 1) IN+ = Low, IN- = Low, VVCC2 = 15 V 1) voltage across the device V(VCC2 - OUT+) or V(OUT- - GND2) < VVCC2. Data Sheet 16 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters 5.3.4 Short Circuit Clamping Table 7 Short Circuit Clamping Parameter Symbol Clamping voltage (OUT+) VCLPout (VOUT - VVCC2) 5.3.5 Values Min. Typ. Max. – 0.9 1.3 Unit Note / Test Condition V IN+ = High, IN- = Low, OUT = High IOUT = 500 mA pulse test, tCLPmax = 10 μs) Unit Note / Test Condition CLOAD = 100 pF VIN+ = 50%, VOUT=50% @ 25°C Dynamic Characteristics Dynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V. Table 8 Dynamic Characteristics Parameter Symbol Values Min. Typ. Max. Input IN to output propagation delay ON TPDON 90 115 137 ns Input IN to output propagation delay OFF TPDOFF 100 120 143 ns Input IN to output propagation delay distortion (TPDOFF - TPDON) TPDISTO -15 5 25 ns Input pulse suppression IN+, IN- TMININ+, TMININ- 30 40 – ns – IN input to output propagation delay ON variation due to temp TPDONt – – 10 ns 1) IN input to output propagation delay OFF variation due to temp TPDOFFt – – 10 ns 1) IN input to output TPDISTOt propagation delay distortion variation due to temp (TPDOFF-TPDON) – – 4 ns 1) CLOAD = 100 pF VIN+ = 50%, VOUT=50% CLOAD = 100 pF VIN+ = 50%, VOUT=50% CLOAD = 100 pF VIN+ = 50%, VOUT=50% Rise time TRISE 5 10 20 ns CLOAD = 1 nF VL 20%, VH 80% Fall time TFALL 4 9 19 ns CLOAD = 1 nF VL 20%, VH 80% 1) The parameter is not subject to production test - verified by design/characterization Data Sheet 17 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters 5.3.6 Active Shut Down Table 9 Active Shut Down Parameter Active shut down voltage Symbol V 1) ACTSD Values Min. Typ. Max. – 2.2 2.5 Unit Note / Test Condition V IOUT-/IOUT-,PEAK=0.1, VCC2 open 1) Referred to GND2 Data Sheet 18 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Timing Diagramms 6 Timing Diagramms 50 % IN+ 80 % 50 % 20 % OUT TPDON Figure 6 TRISE TPDOFF TFALL Propagation Delay, Rise and Fall Time IN+ IN‐ OUT Figure 7 Typical Switching Behavior IN+ VUVLOH 1 VUVLOL 1 VCC1 V UVLOH 2 V UVLOL 2 VCC2 OUT Figure 8 Data Sheet UVLO Behavior 19 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Package Outlines 7 Package Outlines Figure 9 PG-DSO-8-51 (Plastic (Green) Dual Small Outline Package) Data Sheet 20 Rev. 2.0, 2015-06-01 1EDI EiceDRIVER™ Compact 1EDI20N12AF Application Notes 8 Application Notes 8.1 Reference Layout for Thermal Data The PCB layout shown in Figure 10 represents the reference layout used for the thermal characterisation. Pin 4 (GND1) and pin 8 (GND2) require each a ground plane of 100 mm² for achieving maximum power dissipation. The 1EDI20N12AF is conceived to dissipate most of the heat generated through these pins. The thermal coefficient junction-top (Ψth,jt) can be used to calculate the junction temperature at a given top case temperature and driver power dissipation: T j = Ψ th ,jt ⋅ P D + T top Figure 10 Reference Layout for Thermal Data (Copper thickness 35 μm) 8.2 Printed Circuit Board Guidelines The following factors should be taken into account for an optimum PCB layout. • • • Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits. The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and to reduce parasitic coupling. In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible. Data Sheet 21 Rev. 2.0, 2015-06-01 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG