KL26P36M48SF5

Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL26P36M48SF5
Rev 2 08/2014
Kinetis KL26 Sub-Family
MKL26Z128CAL4R
48 MHz Cortex-M0+ Based Microcontroller
Supports ultra low power ARM based microcontroller with USB
feature and ultra small Wafer Level Chip Scale Package. Ideal
solution for smart phone accessories, gaming accessories,
sensor hub applications, etc.
This product offers:
• Ultra small scale package 2.37mm x 2.46mm with 0.35mm
pitch
• USB OTG FS 2.0
• Ultra low dynamic and static power consumption with smart
peripherals for low power applications
• Highly integrated peripherals, including high speed and
mixed signal interfaces, etc
Performance
• 48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
• Up to 128 KB program flash memory
• Up to 16 KB SRAM
36-pin WLCSP (AL)
2.37 x 2.46 x 0.53 Pitch 0.35 mm
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• 27 general-purpose input/output (GPIO)
Communication interfaces
• USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator
System peripherals
• Two 16-bit SPI modules
• Nine low-power modes to provide power optimization
• I2S (SAI) module
based on application requirements
• One low power UART module
• COP Software watchdog
• Two UART modules
• 4-channel DMA controller, supporting up to 63 request
• Two I2C module
sources
Analog Modules
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• 16-bit SAR ADC
• Bit Manipulation Engine
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
Clocks
and programmable reference input
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
Timers
• Six channel Timer/PWM (TPM)
Operating Characteristics
• Two 2-channel Timer/PWM modules
• Voltage range: 1.71 to 3.6 V
• Periodic interrupt timers
• Flash write voltage range: 1.71 to 3.6 V
• 16-bit low-power timer (LPTMR)
• Temperature range (ambient): -40 to 85°C
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information
Part Number
MKL26Z128CAL4R
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
128
16
27
Related Resources
Type
Description
Resource
Selector Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL26P36M48SF5RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL26P36M48SF51
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_L_xN15J 2
Package
drawing
Package dimensions are provided in package drawings.
WLCSP 36-pin: 98ASA00604D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x”
replaced by the revision of the device you are using.
2
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Table of Contents
1 Ratings.................................................................................. 4
1.1 Thermal handling ratings............................................... 4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings..................................................... 4
1.4 Voltage and current operating ratings............................4
2 General................................................................................. 5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................6
2.2.1 Voltage and current operating requirements......6
2.2.2 LVD and POR operating requirements.............. 6
2.2.3 Voltage and current operating behaviors........... 7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC radiated emissions operating behaviors... 14
2.2.7 Designing with radiated emissions in mind........ 15
2.2.8 Capacitance attributes....................................... 15
2.3 Switching specifications................................................. 15
2.3.1 Device clock specifications................................ 15
2.3.2 General switching specifications........................16
2.4 Thermal specifications................................................... 16
2.4.1 Thermal operating requirements........................16
2.4.2 Thermal attributes.............................................. 17
3 Peripheral operating requirements and behaviors................ 17
3.1 Core modules................................................................ 17
3.1.1 SWD electricals .................................................17
3.2 System modules............................................................ 19
3.3 Clock modules............................................................... 19
3.3.1 MCG specifications............................................ 19
3.3.2 Oscillator electrical specifications...................... 21
3.4 Memories and memory interfaces................................. 23
3.4.1 Flash electrical specifications............................ 23
3.5 Security and integrity modules.......................................24
3.6 Analog............................................................................24
3.6.1
3.6.2
ADC electrical specifications..............................24
CMP and 6-bit DAC electrical specifications......29
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4
5
6
7
8
3.6.3 12-bit DAC electrical characteristics.................. 31
3.7 Timers............................................................................ 34
3.8 Communication interfaces............................................. 34
3.8.1 USB electrical specifications..............................34
3.8.2 USB VREG electrical specifications...................35
3.8.3 SPI switching specifications...............................35
3.8.4 Inter-Integrated Circuit Interface (I2C) timing.....40
3.8.5 UART................................................................. 41
3.8.6 I2S/SAI switching specifications........................ 41
3.9 Human-machine interfaces (HMI).................................. 45
3.9.1 TSI electrical specifications................................45
Dimensions........................................................................... 46
4.1 Obtaining package dimensions......................................46
Pinout.................................................................................... 46
5.1 KL26 Signal Multiplexing and Pin Assignments.............46
5.2 KL26 pinouts.................................................................. 48
Ordering parts....................................................................... 48
6.1 Determining valid orderable parts.................................. 49
Part identification...................................................................49
7.1 Description..................................................................... 49
7.2 Format........................................................................... 49
7.3 Fields............................................................................. 49
7.4 Example......................................................................... 50
Terminology and guidelines.................................................. 50
8.1 Definition: Operating requirement.................................. 50
8.2 Definition: Operating behavior....................................... 50
8.3 Definition: Attribute........................................................ 51
8.4 Definition: Rating........................................................... 51
8.5 Result of exceeding a rating.......................................... 51
8.6 Relationship between ratings and operating
requirements.................................................................. 52
8.7 Guidelines for ratings and operating requirements........ 52
8.8 Definition: Typical value................................................. 53
8.9 Typical value conditions.................................................54
9 Revision history.....................................................................54
3
Freescale Semiconductor, Inc.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
1
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
2
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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Kinetis KL26 Sub-Family, Rev2 08/2014.
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VIO
IO pin input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
ID
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
VREGIN
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Low
VIH
Input Signal
High
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
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General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-3
—
mA
-25
—
mA
VIH
VIL
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
IO pin negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol
VPOR
Description
Min.
Typ.
Max.
Unit
Notes
Falling VDD POR detect voltage
0.8
1.1
1.5
V
—
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol
VLVDH
Description
Min.
Typ.
Max.
Unit
Notes
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
VLVW1H
• Level 1 falling (LVWV = 00)
VLVW2H
• Level 2 falling (LVWV = 01)
VLVW3H
• Level 3 falling (LVWV = 10)
VLVW4H
• Level 4 falling (LVWV = 11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
1
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
2.92
3.00
3.08
V
—
±60
—
mV
—
1.54
1.60
1.66
V
—
Low-voltage warning thresholds — low range
VLVW1L
• Level 1 falling (LVWV = 00)
VLVW2L
• Level 2 falling (LVWV = 01)
VLVW3L
• Level 3 falling (LVWV = 10)
VLVW4L
• Level 4 falling (LVWV = 11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
1
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±40
—
mV
—
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
—
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
—
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Output high voltage — Normal drive pad (except
RESET_b)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VOH
Output high voltage — High drive pad (except
RESET_b)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
IOHT
Output high current total for all ports
Max.
Unit
Notes
1, 2
VDD – 0.5
—
V
VDD – 0.5
—
V
1, 2
VDD – 0.5
—
V
VDD – 0.5
—
V
—
100
mA
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
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Freescale Semiconductor, Inc.
General
Table 7. Voltage and current operating behaviors (continued)
Symbol
VOL
VOL
Description
Min.
Max.
Unit
Notes
Output low voltage — Normal drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
0.5
V
Output low voltage — High drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
3
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
3
IIN
Input leakage current (total all pins) for full
temperature range
—
65
μA
3
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
IOLT
4
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
General
Table 8. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
106
120
μs
—
105
117
μs
—
47
54
μs
—
4.5
5.0
μs
—
4.5
5.0
μs
—
4.5
5.0
μs
Notes
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol
Temp.
Typ.
Max
Unit
Note
Analog supply current
—
—
See note
mA
1
Run mode current in compute
operation - 48 MHz core / 24 MHz
flash/ bus disabled, LPTMR running
using 4 MHz internal reference clock,
CoreMark® benchmark code executing
from flash, at 3.0 V
—
6.1
—
mA
2
IDD_RUNCO
Run mode current in compute
operation - 48 MHz core / 24 MHz
flash / bus clock disabled, code of
while(1) loop executing from flash, at
3.0 V
—
3.8
4.4
mA
3
IDD_RUN
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral
clocks disabled, code executing from
flash, at 3.0 V
—
4.6
5.2
mA
3
IDDA
IDD_RUNCO_ CM
Description
Table continues on the next page...
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Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Temp.
Typ.
Max
Unit
Note
IDD_RUN
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral
clocks enabled, code executing from
flash, at 3.0 V
at 25 °C
6.0
6.2
mA
3, 4
at 70 °C
6.2
6.4
mA
at 95 °C
6.2
6.5
mA
IDD_WAIT
Wait mode current - core disabled / 48
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
—
2.7
3.2
mA
3
IDD_WAIT
Wait mode current - core disabled / 24
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
—
2.1
2.6
mA
3
Stop mode current with partial stop 2
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
—
1.5
2.0
mA
3
Very-low-power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, LPTMR
running with 4 MHz internal reference
clock, CoreMark benchmark code
executing from flash, at 3.0 V
—
732
—
µA
5
IDD_VLPRCO
Very low power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, code
executing from flash, at 3.0 V
—
161
329
µA
6
IDD_VLPR
Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks disabled, code
executing from flash, at 3.0 V
—
185
352
µA
6
IDD_VLPR
Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks enabled, code
executing from flash, at 3.0 V
—
255
421
µA
4, 6
IDD_VLPW
Very low power wait mode current core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks
disabled, at 3.0 V
—
110
281
µA
6
IDD_STOP
Stop mode current at 3.0 V
at 25 °C
305
326
µA
—
at 50 °C
317
344
µA
at 70 °C
337
380
µA
at 85 °C
364
428
µA
at 25 °C
2.69
4.14
µA
at 50 °C
5.54
9.80
µA
at 70 °C
11.80
21.94
µA
at 85 °C
21.13
39.13
µA
IDD_PSTOP2
IDD_VLPRCO _CM
IDD_VLPS
Very-low-power stop mode current at
3.0 V
—
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
IDD_LLS
Low leakage stop mode current at 3.0
V
IDD_VLLS3
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
Very low-leakage stop mode 3 current
at 3.0 V
Very low-leakage stop mode 1 current
at 3.0 V
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0
V
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0
V
Temp.
Typ.
Max
Unit
Note
at 25 °C
1.98
2.65
µA
—
at 50 °C
3.13
4.35
µA
at 70 °C
5.65
8.34
µA
at 85 °C
9.58
14.29
µA
at 25 °C
1.46
2.06
µA
at 50 °C
2.29
3.22
µA
at 70 °C
4.10
5.90
µA
at 85 °C
6.93
10.02
µA
at 25 °C
0.71
1.20
µA
at 50 °C
1.10
1.71
µA
at 70 °C
2.09
3.03
µA
at 85 °C
3.80
5.42
µA
at 25 °C
0.40
0.88
µA
at 50 °C
0.80
1.40
µA
at 70 °C
1.79
2.72
µA
at 85 °C
3.50
5.10
µA
at 25 °C
0.23
0.69
µA
at 50 °C
0.61
1.19
µA
at 70 °C
1.59
2.50
µA
at 85 °C
3.30
4.89
µA
—
—
—
7
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
IIREFSTEN4MHz
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the 32
kHz IRC enabled.
52
52
52
52
52
µA
Table continues on the next page...
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Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
IEREFSTEN4MHz
External 4 MHz crystal clock adder. Measured
by entering STOP or VLPS mode with the
crystal enabled.
206
228
237
245
251
uA
IEREFSTEN32KHz
External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by
entering all modes with the
crystal enabled.
VLLS1
440
490
540
560
570
nA
VLLS3
440
490
540
560
570
LLS
490
490
540
560
570
VLPS
510
560
560
560
610
STOP
510
560
560
560
610
ICMP
CMP peripheral adder measured by placing the
device in VLLS1 mode with CMP enabled using
the 6-bit DAC and a single external input for
compare. Includes 6-bit DAC power
consumption.
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by placing the
device in VLLS1 mode with external 32 kHz
crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432
357
388
475
532
nA
IUART
UART peripheral adder
MCGIRCLK (4
measured by placing the
MHz internal
device in STOP or VLPS mode
reference
with selected clock source
clock)
waiting for RX data at 115200 OSCERCLK (4
baud rate. Includes selected
MHz external
clock source power
crystal)
consumption.
66
66
66
66
66
µA
214
237
246
254
260
86
86
86
86
86
235
256
265
274
280
ITPM
TPM peripheral adder
MCGIRCLK (4
measured by placing the
MHz internal
device in STOP or VLPS mode
reference
with selected clock source
clock)
configured for output compare OSCERCLK (4
generating 100 Hz clock signal. MHz external
No load is placed on the I/O
crystal)
generating the clock signal.
Includes selected clock source
and I/O switching currents.
µA
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx mode.
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the measured
values at VDD and VDDA by placing the device
in STOP or VLPS mode. ADC is configured for
low-power mode using the internal clock and
continuous conversions.
366
366
366
366
366
µA
12
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
General
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG in FBE for run mode, and BLPE for VLPR mode
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Run Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
7.00E-03
6.00E-03
Current Consumption on VDD (A)
5.00E-03
4.00E-03
All Peripheral CLK Gates
All Off
All On
3.00E-03
2.00E-03
1.00E-03
000.00E+00
'1-1
1
'1-1
2
'1-1
'1-1
'1-1
'1-1
'1-1
'1-2
3
4
6
12
24
48
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 2. Run mode supply current vs. core frequency
Kinetis KL26 Sub-Family, Rev2 08/2014.
13
Freescale Semiconductor, Inc.
General
VLPR Mode Current Vs Core Frequency
Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
400.00E-06
Current Consumption on VDD (A)
350.00E-06
300.00E-06
250.00E-06
All Peripheral CLK Gates
200.00E-06
All Off
All On
150.00E-06
100.00E-06
50.00E-06
000.00E+00
'1-1
'1-2
1
'1-2
'1-4
2
4
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
16
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
18
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
11
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
13
dBμV
IEC level
0.15–1000
M
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
14
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
CIN
Description
Input capacitance
Min.
Max.
Unit
—
7
pF
Min.
Max.
Unit
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Normal run mode
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
24
MHz
Flash clock
—
24
MHz
System and core clock when Full Speed USB in operation
20
—
MHz
LPTMR clock
—
24
MHz
fFLASH
fSYS_USB
fLPTMR
VLPR and VLPS modes1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
Flash clock
—
1
MHz
—
24
MHz
fFLASH
fLPTMR
LPTMR
clock2
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
15
Freescale Semiconductor, Inc.
General
Table 13. Device clock specifications (continued)
Symbol
fERCLK
Description
Min.
Max.
Unit
—
16
MHz
—
16
MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
UART0 asynchronous clock
—
8
MHz
External reference clock
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
fTPM
fUART0
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
—
36
ns
3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
95
°C
TA
Ambient temperature
–40
85
°C
16
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type
Symbol
Description
36 WLCSP
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to ambient
(natural convection)
59.3
°C/W
1
Four-layer (2s2p)
RθJA
Thermal resistance, junction to ambient
(natural convection)
42.9
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction to ambient
(200 ft./min. air speed)
51.6
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to ambient
(200 ft./min. air speed)
38.9
°C/W
—
RθJB
Thermal resistance, junction to board
37.7
°C/W
2
—
RθJC
Thermal resistance, junction to case
0.48
°C/W
3
—
ΨJT
Thermal characterization parameter,
junction to package top outside center
(natural convection)
0.2
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
SWD_CLK frequency of operation
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
17
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
Min.
Max.
Unit
0
25
MHz
1/J1
—
ns
20
—
ns
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 4. Serial wire clock input timing
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 5. Serial wire data timing
18
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±3
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
—
± 0.4
± 1.5
%fdco
1, 2
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
4
—
MHz
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±3
%fintf_ft
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
Δfintf_ft
fintf_t
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
48
MHz
—
23.99
—
MHz
2
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS = 00)
3, 4
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS = 00)
5, 6
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
—
47.97
—
MHz
—
180
—
ps
7
—
—
1
ms
8
48.0
—
100
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
732 × ffll_ref
Mid range (DRS = 01)
1464 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
tfll_acquire
FLL target frequency acquisition time
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
50
—
ps
PLL accumulated jitter over 1µs (RMS)
10
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
Lock detector detection time
9
10
Dlock
tpll_lock
9
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
20
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
Description
Min.
Typ.
Max.
Unit
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
22
Freescale Semiconductor, Inc.
Notes
1, 2
3, 4
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
—
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
88
650
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
Kinetis KL26 Sub-Family, Rev2 08/2014.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3
Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 24. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the
differential pins ADC0_DPx, ADC0_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
24
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
Absolute
VDDA
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
Absolute
VSSA
VSSA
VSSA
V
4
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
Analog source
resistance
(external)
VREFH
13-bit / 12-bit modes
5
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
18.0
MHz
6
fADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
6
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
7
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
No ADC hardware averaging
7
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH is internally tied to VDDA.
4. VREFL is internally tied to VSSA.
5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
Kinetis KL26 Sub-Family, Rev2 08/2014.
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Peripheral operating requirements and behaviors
7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 6. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
ADC
asynchronous
clock source
fADACK
Conditions1
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
1.2
2.4
3.9
MHz
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
3.0
5.2
7.3
MHz
4.4
6.2
9.5
MHz
LSB4
• ADLPC = 0, ADHSC =
1
Sample Time
TUE
Total unadjusted
error
See Reference Manual chapter for sample times
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
5
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
DNL
INL
EFS
EQ
ENOB
Description
Differential nonlinearity
Integral nonlinearity
Full-scale error
Quantization
error
Conditions1
Min.
Typ.2
Max.
Unit
Notes
–1.1 to
+1.9
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA5
• 12-bit modes
—
±0.7
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
12.8
14.5
—
bits
11.9
13.8
—
bits
12.2
13.9
—
bits
11.4
13.1
—
bits
Effective number 16-bit differential mode
of bits
• Avg = 32
–0.3 to 0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB4
6
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
6.02 × ENOB + 1.76
dB
—
-94
—
dB
—
-85
—
dB
82
95
—
dB
78
90
—
dB
7
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
7
• Avg = 32
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
VTEMP25
Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
Temp sensor
slope
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
Temp sensor
voltage
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1,
PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VDD – 0.5
—
—
V
VH
Analog comparator
VCMPOh
Output high
VCMPOl
hysteresis1
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
IDAC6b
Min.
Typ.
Max.
Unit
—
7
—
μA
6-bit DAC current adder (enabled)
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
250
μA
—
—
900
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
—
0.7
1
μs
1
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
BW
6
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
3dB bandwidth
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
1.
2.
3.
4.
5.
6.
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
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Peripheral operating requirements and behaviors
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 11. Typical INL error vs. digital code
Kinetis KL26 Sub-Family, Rev2 08/2014.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 12. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
34
Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
NOTE
The MCGPLLCLK meets the USB jitter specifications for
certification with the use of an external clock/crystal for
both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter
specifications for certification.
3.8.2 USB VREG electrical specifications
Table 30. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
125
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and
temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
3
3.3
3.6
V
2.1
2.8
3.6
V
2.1
—
3.6
V
1.76
2.2
8.16
μF
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
• Standby mode
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
COUT
External output capacitor
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
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Peripheral operating requirements and behaviors
3.8.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats used
for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 31. SPI master mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
18
—
ns
—
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
15
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 32. SPI master mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
tHI
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
96
—
ns
—
Data hold time (inputs)
0
—
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
36
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Table 32. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol
8
tv
9
Description
Min.
Max.
Unit
Note
Data valid (after SPSCK edge)
—
52
ns
—
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
SS1
(OUTPUT)
3
2
SPSCK
(CPOL=0)
(OUTPUT)
11
10
11
4
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
10
5
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 0)
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SS1
(OUTPUT)
2
3
SPSCK
(CPOL=0)
(OUTPUT)
5
SPSCK
(CPOL=1)
(OUTPUT)
5
6
MISO
(INPUT)
11
4
10
11
7
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
10
PORT DATA MASTER MSB OUT2
BIT 6 . . . 1
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 1)
Table 33. SPI slave mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
Enable lead time
1
—
tperiph
—
Enable lag time
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2.5
—
ns
—
tHI
Data hold time (inputs)
3.5
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
31
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
Description
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
38
38
Freescale Semiconductor, Inc.
<<CLASSIFICATION>>
<<NDA MESSAGE>>
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Table 34. SPI slave mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Frequency of operation
SPSCK period
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
1
—
tperiph
—
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2
—
ns
—
tHI
Data hold time (inputs)
7
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
122
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
Description
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
SS
(INPUT)
2
12
13
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
3
SPSCK
(CPOL=1)
(INPUT)
5
9
8
MISO
(OUTPUT)
see
note
SLAVE MSB
6
MOSI
(INPUT)
10
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 15. SPI slave mode timing (CPHA = 0)
Kinetis KL26 Sub-Family, Rev2 08/2014.
39
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SS
(INPUT)
4
2
3
SPSCK
(CPOL=0)
(INPUT)
5
SPSCK
(CPOL=1)
(INPUT)
5
see
note
SLAVE
8
MSB OUT
6
MOSI
(INPUT)
13
12
13
11
10
MISO
(OUTPUT)
12
9
BIT 6 . . . 1
SLAVE LSB OUT
BIT 6 . . . 1
LSB IN
7
MSB IN
NOTE: Not defined
Figure 16. SPI slave mode timing (CPHA = 1)
3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 35. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.3
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003, 6
Data set-up time
—
ns
7
Rise time of SDA and SCL signals
tr
—
1000
20 +0.1Cb
300
ns
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb6
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
40
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 17. Timing definition for fast and standard mode devices on the I2C bus
3.8.5 UART
See General switching specifications.
3.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks
are driven) and slave mode (clocks are input). All timing is given for noninverted
serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame
sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
Kinetis KL26 Sub-Family, Rev2 08/2014.
41
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.6.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 36. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15.5
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
19
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 18. I2S/SAI timing — master modes
42
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Table 37. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
33
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
28
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 19. I2S/SAI timing — slave modes
3.8.6.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Kinetis KL26 Sub-Family, Rev2 08/2014.
43
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 38. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
—
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 20. I2S/SAI timing — master modes
Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
S11
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
Table continues on the next page...
44
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Peripheral operating requirements and behaviors
Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
—
ns
72
ns
S19
—
ns
30
I2S_TX_FS input assertion to I2S_TXD output
valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 21. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 40. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNF
Fixed power consumption in run mode
—
100
—
µA
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
45
Freescale Semiconductor, Inc.
Dimensions
Table 40. TSI electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNV
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
—
128
µA
TSI_EN
Power consumption in enable mode
—
100
—
µA
TSI_DIS
Power consumption in disable mode
—
1.2
—
µA
TSI_TEN
TSI analog enable time
—
66
—
µs
TSI_CREF
TSI reference capacitor
—
1.0
—
pF
TSI_DVOLT
Voltage variation of VP & VM around nominal
values
0.19
—
1.03
V
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
36-pin WLCSP
Then use this document number
98ASA00604D
5 Pinout
5.1 KL26 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
VREFH is internally tied to VDDA and VREFL is internally
tied to VSSA.
46
Freescale Semiconductor, Inc.
Kinetis KL26 Sub-Family, Rev2 08/2014.
Pinout
36
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
PTE0
SPI1_MISO
UART1_TX
RTC_CLKOUT CMP0_OUT
A6
PTE0
DISABLED
C3
VSS
VSS
C4
USB0_DP
USB0_DP
C5
USB0_DM
USB0_DM
C6
VOUT33
VOUT33
D4
VREGIN
VREGIN
D5
PTE16
ADC0_DP1/
ADC0_SE1
ADC0_DP1/
ADC0_SE1
PTE16
SPI0_PCS0
UART2_TX
TPM_CLKIN0
D6
PTE17
ADC0_DM1/
ADC0_SE5a
ADC0_DM1/
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
TPM_CLKIN1
D3
PTE18
ADC0_DP2/
ADC0_SE2
ADC0_DP2/
ADC0_SE2
PTE18
SPI0_MOSI
I2C0_SDA
SPI0_MISO
D2
PTE19
ADC0_DM2/
ADC0_SE6a
ADC0_DM2/
ADC0_SE6a
PTE19
SPI0_MISO
I2C0_SCL
SPI0_MOSI
E6
VDDA/
VREFH
VDDA/
VREFH
VDDA/
VREFH
F6
VSSA/
VREFL
VSSA/
VREFL
VSSA/
VREFL
E5
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30
TPM0_CH3
F5
PTA0
SWD_CLK
TSI0_CH1
PTA0
TPM0_CH5
E4
PTA1
DISABLED
TSI0_CH2
PTA1
UART0_RX
TPM2_CH0
ALT6
ALT7
I2C1_SDA
VSS
LPTMR0_ALT3
TPM_CLKIN1
SWD_CLK
F4
PTA2
DISABLED
TSI0_CH3
PTA2
UART0_TX
TPM2_CH1
E3
PTA3
SWD_DIO
TSI0_CH4
PTA3
I2C1_SCL
TPM0_CH0
SWD_DIO
F3
PTA4
NMI_b
TSI0_CH5
PTA4
I2C1_SDA
TPM0_CH1
NMI_b
F2
VDD
VDD
VDD
E2
VSS
VSS
VSS
F1
PTA18
EXTAL0
EXTAL0
PTA18
UART1_RX
TPM_CLKIN0
E1
PTA19
XTAL0
XTAL0
PTA19
UART1_TX
TPM_CLKIN1
D1
PTA20
RESET_b
C2
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0
C1
PTB1
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
I2C0_SDA
TPM1_CH1
B1
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
TPM0_CH0
I2S0_TXD0
B2
PTC2
ADC0_SE11/
TSI0_CH15
ADC0_SE11/
TSI0_CH15
PTC2
I2C1_SDA
TPM0_CH1
I2S0_TX_FS
B3
PTC3/
LLWU_P7
DISABLED
LPTMR0_ALT1
PTA20
Kinetis KL26 Sub-Family, Rev2 08/2014.
PTC3/
LLWU_P7
RESET_b
UART1_RX
TPM0_CH2
CLKOUT
I2S0_TX_BCLK
47
Freescale Semiconductor, Inc.
Ordering parts
36
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
TPM0_CH3
A1
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
B4
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_ALT2 I2S0_RXD0
A2
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI
EXTRG_IN
I2S0_RX_
BCLK
SPI0_MISO
A3
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_MISO
audioUSB_
SOF_OUT
I2S0_RX_FS
SPI0_MOSI
A4
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI1_PCS0
UART2_RX
TPM0_CH4
A5
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
B5
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI1_MOSI
UART0_RX
SPI1_MISO
B6
PTD7
DISABLED
PTD7
SPI1_MISO
UART0_TX
SPI1_MOSI
ALT6
ALT7
I2S0_MCLK
CMP0_OUT
I2S0_MCLK
5.2 KL26 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL26 Signal Multiplexing and Pin Assignments.
1
A
2
PTC4/
PTC6/
LLWU_P8 LLWU_P10
3
4
5
6
PTC7
PTD4/
LLWU_P14
PTD5
PTE0
A
PTD7
B
B
PTC1/
LLWU_P6/
RTC_CLKIN
PTC2
PTC3/
LLWU_P7
C
PTB1
PTB0/
LLWU_P5
VSS
USB0_DP
USB0_DM
VOUT33
C
D
PTA20
PTE19
PTE18
VREGIN
PTE16
PTE17
D
E
PTA19
VSS
PTA3
PTA1
PTE30
VDDA/
VREFH
E
F
PTA18
VDD
PTA4
PTA2
PTA0
VSSA/
VREFL
F
1
2
3
4
5
6
PTC5/
PTD6/
LLWU_P9 LLWU_P15
Figure 22. KL26 36-pin WLCSP pinout diagram
6 Ordering parts
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Kinetis KL26 Sub-Family, Rev2 08/2014.
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search
for the following device numbers: PKL26 and MKL26
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reels
KL##
Kinetis family
• KL26
A
Key attribute
• Z = Cortex-M0+
FFF
Program flash memory size
• 128 = 128 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• C = –40 to 85
Table continues on the next page...
Kinetis KL26 Sub-Family, Rev2 08/2014.
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Terminology and guidelines
Field
Description
Values
PP
Package identifier
• AL = 36 WLCSP (2.374 mm x 2.459 mm x
0.528 mm)
CC
Maximum CPU frequency (MHz)
• 4 = 48 MHz
N
Packaging type
• R = Tape and reel
7.4 Example
This is an example part number:
MKL26Z128CAL4R
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
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Terminology and guidelines
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Kinetis KL26 Sub-Family, Rev2 08/2014.
Min.
–0.3
Max.
1.2
Unit
V
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Freescale Semiconductor, Inc.
Terminology and guidelines
8.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
g(
g
tin
era
Op
in
rat
i
(m
nt
me
n.)
mi
g
tin
era
Op
n.)
e
uir
req
g
tin
era
Op
t
en
em
uir
q
re
ax
(m
.)
x
ma
g(
g
tin
era
in
rat
.)
Op
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
dli
n
Ha
ng
x.)
n.)
mi
g(
in
rat
li
nd
Ha
ng
a
(m
ing
rat
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Terminology and guidelines
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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Freescale Semiconductor, Inc.
Revision history
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Table 41. Typical value conditions
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
9 Revision history
The following table provides a revision history for this document.
Table 42. Revision history
Rev. No.
Date
2
08/2014
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Substantial Changes
Initial public release.
Kinetis KL26 Sub-Family, Rev2 08/2014.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
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© 2012-2014 Freescale Semiconductor, Inc.
Document Number KL26P36M48SF5
Revision 2 08/2014