IDT ICS844008I

ICS844008I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844008I-01 is an 8 output LVDS Synthesizer
ICS
optimized to generate GbE/10GbE reference clock
HiPerClockS™ frequencies and is a member of the HiPerClocksTM
family of high performance clock solutions from IDT.
Using a 25MHz parallel resonant crystal, the following
frequencies can be generated based on the F_SEL pin: 125MHz
or 156.25MHz. The ICS844008I-01 uses IDT’s 3rd generation low
phase noise VCO technology and can achieve <1ps typical rms
phase jitter, easily meeting GbE/10GbE jitter requirements. The
ICS844008I-01 is packaged in a 32-pin TQFP or 32 VFQFN
packages.
• Eight LVDS outputs
• Crystal oscillator interface
• Supports the following output frequencies:
125MHz or 156.25MHz
• VCO: 625MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.38ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
FREQUENCY SELECT FUNCTION TABLE
Input
Input Frequency (MHz)
25MHz
F_SEL
0
M Divider Value
25
N Divider Value
4
Output Frequency (MHz)
156.25
25MHz
1
25
5
125 (default)
BLOCK DIAGRAM
XTAL_OUT
Phase
Detector
625MHz
(w/25MHz
Reference)
0
÷4
÷5
QA0
1
24
QB3
nQA1
nQA0
2
23
nQB3
VDD
3
22
VDD
QA1
4
21
QB2
nQA2
nQA1
5
20
nQB2
QA3
GND
6
19
GND
QA2
7
18
QB1
nQA2
8
17
nQB1
nQA3
M = ÷25 (fixed)
QB0
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
9 10 11 12 13 14 15 16
MR
nQB0
QB0
GND
VDD
nQA3
QA3
QB1
ICS844008I-01
F_SEL
nQB0
nQB1
ICS844008I-01
QB2
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
nQB2
QB3
nQB3
MR Pulldown
ICS844008I-01
F_SEL Pullup
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
OEB Pullup
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
VDDA
OSC
32 31 30 29 28 27 26 25
QA1
QA2
VCO
nPLL_SEL
25MHz
XTAL_IN
VDD
1
OEB
nQA0
GND
OEA
QA0
nPLL_SEL Pulldown
XTAL_IN
OEA Pullup
XTAL_OUT
PIN ASSIGNMENT
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
3, 12,
22, 27
4, 5
6, 13,
19, 29
7, 8
QA0, nQA0
Output
Type
Differential output pair. LVDS interface levels.
VDD
Power
Core supply pins.
QA1, nQA1
Ouput
Differential output pair. LVDS interface levels.
GND
Power
Power supply ground.
QA2, nQA2
Output
9
F_SEL
Input
10, 11
QA3, nQA3
Output
14, 15
QB0, nQB0
Output
16
MR
Input
17, 18
nQB1, QB1
Output
20, 21
nQB2, QB2
Output
Differential output pair. LVDS interface levels.
23, 24
nQB3, QB3
Output
Differential output pair. LVDS interface levels.
25
VDDA
Power
26
nPLL_SEL
Input
28
OEB
Input
30, 31
XTAL_OUT,
XTAL_IN
Input
32
OEA
Input
NOTE: Pullup and Pulldown refer
Description
Differential output pair. LVDS interface levels.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs to go low and the inver ted output to go high.
Pulldown
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
Selects between the PLL and XTAL as input to the dividers. When LOW,
Pulldown selects PLL (PLL enabled). When HIGH, selects the XTAL (PLL bypassed).
LVCMOS/LVTTL interface levels.
Output enable for QB[0:3]/nQB[0:3] outputs. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Output enable for QA[0:3]/nQA[0:3] outputs. See Table 3A.
Pullup
LVCMOS/LVTTL interface levels.
to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
TABLE 3A. OEA FUNCTION TABLE
Input
OEA
TABLE 3B. OEB FUNCTION TABLE
Outputs
Input
QA[0:3], nQA[0:3]
OEB
Outputs
QB[0:3], nQB[0:3]
0
High Impedance state
0
High Impedance state
1
Normal operation
1
Normal operation
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA
32 TQFP, E-Pad
32.2°C/W (0 mps)
32 VFQFN
37°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.20
3.3
VDDA
Analog Supply Voltage
VDD
V
IDD
Power Supply Current
275
mA
IDDA
Analog Supply Current
20
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
Test Conditions
VDD = 3.3V
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
VIL
Input Low Voltage
VDD = 3.3V
0.8
V
IIH
Input
High Current
MR, nPLL_SEL
OEA, OEB, F_SEL
VDD = VIN = 3.465V
15 0
µA
VDD = VIN = 3.465V
5
µA
IIL
Input
Low Current
MR, nPLL_SEL
VDD = 3.465V, VIN = 0V
-5
µA
OEA, OEB, F_SEL
VDD = 3.465V, VIN = 0V
-150
µA
-0.3
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
Test Conditions
Minimum
Typical
325
1.2
3
1.3
Maximum
Units
550
mV
50
mV
1.5
V
50
mV
ICS844008AYI-01 REV. B NOVEMBER 21, 2008
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
5
pF
Maximum
Units
NOTE: Characterized using an18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
tjit(cc)
Output Skew; NOTE 1, 2
Test Conditions
Minimum
Typical
FSEL = 0
156.25
FSEL = 1
125
RMS Phase Jitter (Random);
NOTE 3
t R / tF
Output Rise/Fall Time
MHz
110
Cycle-to-Cycle Jitter
tjit(Ø)
MHz
25
ps
ps
125MHz, (1.875MHz - 20MHz)
0.38
ps
156.25MHz, (1.875MHz - 20MHz)
0.42
ps
20% to 80%
300
700
ps
odc
Output Duty Cycle
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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➤
TYPICAL PHASE NOISE AT 125MHZ
125MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.38ps (typical)
NOISE POWER dBc
Hz
Gigabit Ethernet Filter
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding a
Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
➤
TYPICAL PHASE NOISE AT 156.25MHZ
156.25MHz
Gigabit Ethernet Filter
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.42ps (typical)
Phase Noise Result by adding a
Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Noise Power
Phase Noise Plot
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
Qx
VDD
VDDA
LVDS
Phase Noise Mask
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQA0:nQA3,
nQB0:nQB3
nQx
Qx
QA0:QA3,
QB0:QB3
➤
tcycle n
➤
nQy
➤
➤
tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Qy
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQA0:nQA3,
nQB0:nQB3
nQA0:nQA3,
nQB0:nQB3
80%
QA0:QA3,
QB0:QB3
80%
VOD
t PW
t
QA0:QA3,
QB0:QB3
PERIOD
20%
20%
tF
tR
odc =
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
VDD
VDD
out
LVDS
➤
out
➤
out
DC Input
➤
LVDS
100
➤
VOD/Δ VOD
VOS/Δ VOS
out
➤
DC Input
➤
OFFSET VOLTAGE SETUP
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844008I-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
pin. Figure 1 illustrates this for a generic VDD pin and also shows
that VDDA requires that an additional10Ω resistor along with a
10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
LVDS OUTPUTS
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS844008I-01 has been characterized with an 18pF
parallel resonant crystals. The capacitor values shown in
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
VDD
VCC
VDD
VCC
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
8
TO
XTAL INPUT INTERFACE
ICS844008AYI-01 REV. B NOVEMBER 21, 2008
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical perfor mance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
VFQFN EPAD THERMAL RELEASE PATH
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
In order to maximize both the removal of heat from the package
and the electrical perfor mance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 6. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
SOLDER
LAND PATTERN
THERMAL VIA
PIN
PIN PAD
(GROUND PAD)
FIGURE 6. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
SCHEMATIC LAYOUT
Figure 7 shows an example of ICS844008I-01 application
schematic. In this example, the device is operated at VDD= 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. Two examples of
LVDS for receiver without built-in termination are shown in this
schematic.
VDD
C5
0.1uF
VDD
OEB
VDDA
X1
C3
0.01u
25MHz
F
p
8
1
C1
27pF
C4
10uF
R1
10
nPLL_SEL
Zo = 50 Ohm
Q7
OEA
32
31
30
29
28
27
26
25
U1
VDD
QA0
nQA0
1
2
3
4
5
6
7
8
QA1
nQA1
QA2
nQA2
QA0
nQA0
VDD
QA1
nQA1
GND
QA2
nQA2
Zo = 50 Ohm
QB3
nQB3
VDD
QB2
nQB2
GND
QB1
nQB1
QB3
nQB3
24
23
22
21
20
19
18
17
QB2
nQB2
QB0
nQB0
F_SEL
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
-
VDD
C6
0.1uF
QB1
nQB1
VDD=3.3V
9
10
11
12
13
14
15
16
QA3
nQA3
ICS844008I-01
MR
Zo = 50 Ohm
Q5
VDD
R3
50
C8
0.1uF
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
R2
100
nQ7
F_SEL
QA3
nQA3
VDD
GND
QB0
nQB0
MR
C7
0.1uF
+
OEA
XTAL_IN
XTAL_OUT
GND
OEB
VDD
nPLL_SEL
VDDA
C2
27pF
To Logic
Input
pins
Zo = 50 Ohm
C9
0.1uF
R4
50
+
-
nQ5
RD2
1K
Alternate
LVDS
Termination
FIGURE 7. ICS844008I-01 SCHEMATIC LAYOUT
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844008I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (275mA + 20mA) = 1022.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.022W * 37°C/W = 122.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (multi-layer).
TABLE 7A. THERMAL RESISTANCE θJA FOR 32-LEAD TQFP, E-PAD FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.2°C/W
26.3°C/W
24.7°C/W
TABLE 7B. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
12
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RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOW TABLE
FOR
32 LEAD TQFP, E-PAD
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
TABLE 8B. θJAVS. AIR FLOW TABLE
FOR
0
1
2.5
32.2°C/W
26.3°C/W
24.7°C/W
32 LEAD VFQFN
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS844008I-01 is: 2652
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION
EXPOSED PAD DOWN
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABA-HD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.20
A1
0.05
0.10
0.15
A2
0.95
1.0
1.05
b
0.30
0.35
0.40
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
D3 & D3
3.0
3.5
4. 0
Reference Document: JEDEC Publication 95, MS-026
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 9 below.
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
32
N
A
0.80
1.0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
5.0 BASIC
D, E
D2, E2
3.0
3.3
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
844008AYI-01LF
ICS4008AI01L
32 Lead "Lead-Free" TQFP, E-Pad
Tube
-40°C to 85°C
844008AYI-01LFT
ICS4008AI01L
32 Lead "Lead-Free" TQFP, E-Pad
1000 Tape & Reel
-40°C to 85°C
844008AKI-01LF
ICS008AI01L
32 Lead "Lead-Free" VFQFN
Tray
-40°C to 85°C
844008AKI-01LF
ICS008AI01L
32 Lead "Lead-Free" VFQFN
1000 Tape & Reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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REVISION HISTORY SHEET
Rev
B
B
Table
T6
Page
4
10
Description of Change
AC Characteristics Table - corrected cycle-to-cycle jitter limit from 75ps maxmimum to
25ps maximum.
Added Schematic Layout.
Added 32 VFQFN package throughout the datasheet.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
17
Date
5/13/08
11/21/08
ICS844008AYI-01 REV. B NOVEMBER 21, 2008
ICS844008I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
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+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
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