MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66010FP/GP M66010FP/GP 24-BIT I/O EXPANDER 24-BIT I/O EXPANDER DESCRIPTION M66010 Semiconductor Integrated Circuit inputs 24-bit data in series and outputs it in parallel and vice versa, using shift register function. Equipped with 2 independent shift registers, one for serial-toparallel, the other for parallel-to-serial, this IC is able to read serial input data into a shift register while converting data from parallel to serial. Parallel input/output pins are set to input or output according to the bit. The M66010 is useful in a wide range of applications, such as MCU (micro controller unit) input/output port extension and serial bus system data communication. FEATURES • Two-way serial data communication with MCU • Serial data intake possible during parallel-to-serial conversion • Parallel input/output switchable according to the bit • Low power dissipation: 100µW maximum per package (VCC =5V, Ta = 25˚C, quiescent) • Schmidt input (DI, CLK, S, CS) • Open drain output (DO, D1 thru D24) • Parallel data input and output (D1 thru D24) • Wide operating supply voltage range (VCC = 2V ~ 6V) APPLICATION MCU-related serial-parallel data conversion, serial bus control by MCU, etc. FUNCTION The M66010 is produced by using the silicon gate CMOS (complementary metal-oxide semiconductor) technology. It is distinguished for low power dissipation and high noise resistance. Because two independent shift registers are built in, one for serial-to-parallel, the other for parallel-to-serial, this IC is able to read serial input data into a shift register while converting parallel data into serial data. One cycle of latching 24-bit parallel data and outputing it in series while taking in serial data from MCU is initiated by CS’s shift from “H” to “L”. At CS fall edges, 24-bit parallel data is latched, and output in series from pin DO synchronously with shift clock fall edges. At shift clock rise edges, serial data is taken in from MCU via pin DI. The data is read into shift register. The 25th and following shift clock pulses are ignored and read-in operation is masked. The pin D0 status shifts to high-impedance. As CS is then shifted from “L” to “H”, 24-bit serial data taken in via pin DI is output in parallel to pins D1 thru D24. Because parallel output pins are the n-channel open drain output type, write data “H” for pins which should be set to input. PIN CONFIGURATION (TOP VIEW) SERIAL DATA OUTPUT SERIAL DATA INPUT CLOCK INPUT CHIP SELECT INPUT SET INPUT PARALLEL DATA I/O D0 D1 CLK CS VCC S GND D24 D23 D22 D21 D20 D19 D18 D17 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DO DI CLK CS S D24 D23 D22 D21 D20 D19 D18 D17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 D1 D2 D3 D4 D5 D6 D7 PARALLEL D8 DATA D9 I/O D10 D11 D12 D13 D14 D15 D16 Outline 32P2W-A 32P2U-B OPERATION (1) When power is turned on, the status of pins D0 and D1 thru D24 is unstable. Their status turns high-impedance when S is shifted to “L”. (2) At CS fall edges, the status of pins D1 thru D24 is loaded on shift register 1. (3) At CLK fall edges, 24-bit data loaded as described above is output in series from pin D0. (4) At CLK rise edges, 24-bit serial data is taken in from pin DI and written on shift register 2. (5) The 25th and following CLK pulses are ignored, and serial data write is discontinued. Pin D0 status turns high-impedance. (6) At CS rise edges, data written as described in (4) is output to pins D1 thru D24. (7) Shift register 1 loads data added from outside as well as AND tie data which has the same contents as data latched by serial output latch. (8) If the CS rises before CLK reaches the 24th bit, parallel output latch latches data which has been written on shift register, and output it to pins D1 thru D24. (9) Pins D1 thru D24 are switched between input and output according to serial data input to pin DI. Pins for which “H” is written are set to input. 1 MITSUBISHI 〈DIGITAL ASSP〉 M66010FP/GP 24-BIT I/O EXPANDER BLOCK DIAGRAM VCC 5 Shift register 1 3 SET INPUT S 6 CHIP SELECT INPUT CS 4 D24 D23 D22 Control circuit CLOCK INPUT CLK 1 DO D3 D2 D1 31 D2 30 D3 Q24 Q23 Q22 Q3 Q2 Q1 Parallel output latch D24 D23 D22 D3 D2 D1 PARALLEL DATA I/O 10 D22 Q3 Q2 Q1 9 D23 Shift register 2 8 D24 DI DI SERIAL DATA OUTPUT 32 D1 Q24 Q23 Q22 SERIAL DATA INPUT DO 2 7 16 GND GND VCC VCC VCC CLK S CS DI DO Input type D1~D24 Output type OPERATION TIMING CHART S H (1) L (2) CS (5) 1 CLK 2 3 4 5 6 DO3 DO4 DO5 DO6 7 8 9 DO7 DO8 DO9 10 23 24 25 (4) DO1 DI DO2 (3) DI1 DO DO23 DO24 High impedance DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI23 DI24 (6) D1 DI1 D01 D2 DI2 D02 D24 DI24 D024 One cycle 2 MITSUBISHI 〈DIGITAL ASSP〉 M66010FP/GP 24-BIT I/O EXPANDER ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 75°C unless otherwise noted) Symbol Parameter Conditions VCC VI VO Supply voltage Input voltage Output voltage IIK Input protection diode current IOK Output parasitic diode current IGND Tstg GND current Storage temperature Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 –20 20 –20 20 –150 –65 ~ 150 VI<0V VI>VCC VO<0V VO>VCC GND Unit V V V mA mA mA ˚C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Topr Parameter Min. 2 0 0 –20 Supply voltage Input voltage Output voltage Operating temperature Limits Typ. Max. 6 VCC VCC 75 Unit V V V °C ELECTRICAL CHARACTERISTICS (VCC = 2 ~ 6V unless otherwise noted) Symbol VT+ Test conditions Parameter Upper threshold voltage VT– Lower threshold voltage VIH High-level input voltage VIL Low-level input voltage VOL Open drain low-level output voltage IO Output leakage current IIH IIL ICC High-level Input leakage current Low-level output leakage current Static power dissipation VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VI=VT+, VT– VCC=4.5V VI=VT+, VT– VCC=6V VI=VCC VI=GND VI=VCC, GND CLK, CS, S, DI D1 ~ D24 Limits Ta=25˚C Min. Typ. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC Ta= –20~75˚C Min. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC Unit V V V V IOL=5mA 0.4 0.5 V VO=VCC VO=GND VCC=6.0V VCC=6.0V VCC=6.0V 1.0 –1.0 0.1 –0.1 20.0 10.0 –10.0 1.0 –1.0 200.0 µA Ta= –20~75˚C Min. Max. 1.9 400 400 400 400 400 Unit µA µA µA SWITCHING CHARACTERISTICS (VCC = 5V) Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Input clock maximum repetitive frequency “L–Z” and “Z–L” outputs propagation time CLK-DO “L–Z” and “Z–L” outputs propagation time CS-D1 to D24 “L–Z” outputs propagation time S=DO, D1 to D24 Test conditions CL=50pF RL=1kΩ (Note) Limits Ta=25˚C Min. Typ. Max. 2.5 300 300 300 300 300 MHz ns ns ns ns ns 3 MITSUBISHI 〈DIGITAL ASSP〉 M66010FP/GP 24-BIT I/O EXPANDER TIMING CONDITIONS (VCC = 5V) Limits Symbol Parameter tw Test conditions CLK, CS and S pulse width DI setup time (in response to CLK) CS setup time (in response to CLK) DI thru D24 setup time (in response to CS) DI hold time (in response to CLK) CS hold time (in response to CLK) D1 thru D24 hold time (in response to CS) CS recovery time (in response to S) tsu th trec Ta=25˚C Min. Typ. Max. 200 100 100 100 100 100 100 100 Ta= –20~75˚C Min. Max. 260 130 130 130 130 130 130 130 Unit ns ns ns ns NOTE: TEST CIRCUIT Input VCC VCC RL P.G. CL 50Ω GND 4 DO, D1~D24 DUT (1) Pulse generator (PG) characteristics: tr=tf=6ns (10% ~ 90%) (2) Capacitance CL includes connection floating capacitance and probe input capacitance. MITSUBISHI 〈DIGITAL ASSP〉 M66010FP/GP 24-BIT I/O EXPANDER TIMING CHARTS tw CLK tw 50% 50% 50% GND S 50% 10% VOL tw 50% GND trec tPZL tPLZ DO VCC VCC CS 50% VCC GND tw VCC CS 50% 50% 50% tPLZ D1~D24 50% GND tPZL 50% 10% VOL tw VCC 50% S 50% GND tPLZ DO D1~D24 10% DI 50% tsu VOL VCC 50% GND th VCC 50% CLK 50% D1~D24 tsu GND VCC 50% GND th VCC 50% CS GND CS 50% 50% GND tsu CLK VCC th 50% 50% VCC GND 5