MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66008P/FP M66008P/FP 16-BIT I/O EXPANDER 16-BIT I/O EXPANDER DESCRIPTION The M66008 is a semiconductor integrated circuit providing the 16-bit serial input-parallel output and parallel input-serial output shift register function. Independent built-in registers for serial input-parallel output and parallel input-serial output enable serial input data to be read into a shift register during output of serial data converted from parallel data. In addition, parallel data input/output pin can be placed in input or output mode in bits. The M66008 is widely applicable to I/O port extension for MCU, data communication of serial bus system, etc. FEATURES • Two-way serial data communication with MCU • Reading of serial data during parallel-serial data conversion • Division of I/O bit in parallel data input/output • Low power consumption of 50 µW/package maximum (Vcc=5V, Ta=25°C at time of standstill) • Schmitt triggered input (DI, CLK, S, CS) • Open drain output (DO, D1~D16) • With parallel data input/output (D1~D16) • Wide operating supply voltage range (Vcc=2~6V) • Wide operating temperature range (Ta=–20~75°C) PIN CONFIGURATION (TOP VIEW) SERIAL DATA OUTPUT DO ← 1 DO D1 24 ↔ D1 SERIAL DATA INPUT DI → 2 DI D2 23 ↔ D2 CLK D3 22 ↔ D3 CS D4 21 ↔ D4 D5 20 D6 19 D7 18 17 CLOCK INPUT CLK → 3 CHIP SELECT INPUT CS → 4 VCC SET INPUT 5 S→ 6 S GND 7 D16 PARALLEL DATA D15 INPUT/OUTPUT D14 D13 ↔ 8 D16 D8 ↔ 9 D15 D9 16 ↔ 10 D14 D10 15 ↔ 11 D13 D11 14 D12 13 GND 12 ↔ D5 ↔ D6 PARALLEL DATA ↔ D7 INPUT/OUTPUT ↔ D8 ↔ D9 ↔ D10 ↔ D11 ↔ D12 Outline 24P4D 24P2N-B APPLICATION Parallel/serial data conversion for MCU periphery, serial bus control by parallel/serial data conversion MCU, etc. BLOCK DIAGRAM VCC SET INPUT S 6 CHIP SELECT INPUT CS 4 SHIFT REGISTER ! D16 D15 D14 SERIAL 1 DODATA OUTPUT DO VCC D3 D2 D1 24 D1 23 D2 22 D3 Q16 Q15 Q14 Q3 Q2 Q1 PARALLEL OUTPUT LATCH D16 D15 D14 D3 D2 D1 Q16 D15 D14 Q3 Q2 Q1 10 9 SHIFT REGISTER @ SERIAL DI 2 DATA INPUT D1 8 7 12 GND GND D14 D15 D16 PARALLE DATA INPUT/OUTPUT CLOCK INPUT CLK 3 CONTROL CIRCUIT 5 CLK S CS DI INPUT FORMAT VCC VCC DO D1~ D16 OUTPUT FORMAT 1 MITSUBISHI 〈DIGITAL ASSP〉 M66008P/FP 16-BIT I/O EXPANDER FUNCTION The M66008 uses a silicon gate CMOS process to achieve low power consumption and high noise margin. The M66008 independently forms a 16-bit serial input-parallel output shift register and a parallel input-serial output shift register to read serial input data during output of serial data converted from parallel data. The operation for serial output of 16-bit parallel data and operation for reading serial data from MCU by changing CS from “H” to “L”. That is, at a falling edge of CS, 16-bit parallel data is latched and serial data is output from the DO pin in synchronization with 16-bit parallel data at a falling edge of shift clock. In addition, serial data from MCU is read into an internal shift register via the DI pin at a rising edge of shift clock. The 17th bit shift clock and later clocks are ignored. When the reading operation is masked, the DO pin is placed in high impedance status. When CS changes from “L” to “H”, 16-bit serial data read from the DI pin is output to pins D1 to D16 in parallel. Since the output format of the parallel output pin is set to Nchannel open drain output, write “H” data into a terminal placed in input mode. OPERATION DESCRIPTION (1) When power is turned on, DO and D1~D16 are indeterminate. However, they are placed in high impedance status by setting S to “L”. (2) The status of D1 to D16 is loaded to shift register ! at a falling edge of CS. (3) At a falling edge of CLK, 16-bit serial output of the data loaded in step (2) is sequentially performed from DO. (4) At a rising edge of CLK, 16-bit serial data is written into shift register @ from DI. (5) CLK of 17th bit and later is ignored and serial data cannot be written. DO is placed in high impedance status. (6) At a rising edge of CS, data written in step (4) is output to D1 to D16. (7) Shift register ! loads data to be applied externally and AND data having the latched content to parallel output latch. (8) When CS is activated before arrival of CLK at the 16th bit, parallel output latch outputs to D1 to D16 by latching the data that has been written into shift register @. Shift registers ! and @ continues the shift operation until it arrives at the 16th bit of CLK and DO output serial data. (9) Serial data is used to control the operation for switching input/output mode of D1 to D16. The pin set to “H” operates as an input pin. OPERATION TIMING DIAGRAM H S CS (1) L (2) (5) 2 CLK 1 DI DO1 DO DI1 3 4 5 6 7 8 9 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 10 15 16 17 (4) DO15 DO16 High impedance (3) DI15 DI16 (6) D1 DI1 DO1 D2 DI2 DO2 ~ DI6 DO16 DI16 1 cycle 2 MITSUBISHI 〈DIGITAL ASSP〉 M66008P/FP 16-BIT I/O EXPANDER ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 75°C unless otherwise noted) Symbol Parameter Conditions VCC VI VO Supply voltage Input voltage Output voltage IIK Input protection diode current IOK Output incidental diode current IGND Tstg Current/GND Storage temperature Ratings –0.5 ~ +7 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 –20 20 –20 20 –64 –65 ~ 150 VI<0V VI>VCC VO<0V VO>VCC GND Unit V V V mA mA mA °C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Topr Parameter Min. 2 0 0 –20 Supply voltage Input voltage Output voltage Operating temperature Limits Typ. Max. 6 VCC VCC 75 Unit V V V °C ELECTRICAL CHARACTERISTICS (VCC = 2 ~ 6V unless otherwise noted) Symbol Parameter Threshold voltage in positive direction Threshold voltage in negative direction VT+ VT– VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage IO Maximum output leak current High-level input current Low level input current Static consumption current IIH IIL ICC Conditions VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VI=VT+, VT– VCC=4.5V VI=VT+, VT– VCC=6V VI=VCC VI=GND VI=VCC, GND CLK, CS S, DI D1~D16 Limits Ta=25˚C Min. Typ. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC Ta= –20~75˚C Min. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC IOL=3mA 0.4 0.5 VO=VCC 1.0 –1.0 0.1 –0.1 10.0 10.0 –10.0 1.0 –1.0 100.0 VO=GND VCC=6V VCC=6V VCC=6V Unit V V V V V µA µA µA µA SWITCHING CHARACTERISTICS (VCC = 5V) Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Maximum repetition frequency Output “L-Z”, “Z-L” propagation time CLK-DO Output “L-Z”, “Z-L” propagation time CS-D1 to D16 Output “L-Z” propagation time S-DO, D1 ~ D16 Conditions CL=50pF RL=1kΩ (Note 2) Limits Ta=25˚C Min. Typ. Max. 2.5 300 300 300 300 300 Ta= –20~75˚C Min. Max. 1.9 400 400 400 400 400 Unit MHz ns ns ns ns ns 3 MITSUBISHI 〈DIGITAL ASSP〉 M66008P/FP 16-BIT I/O EXPANDER TIMING REQUIREMENTS (VCC = 5V) Limits Symbol tw Parameter Conditions CLK, CS, S pulse width DI set up time for CLK CS set up time for CLK D1~D16 set up time for CS DI hold time for CLK CS hold time for CLK D1~D16 hold time for CS CS recovery time for S tsu th trec Ta=25˚C Min. Typ. Max. 200 100 100 100 100 100 100 100 Ta= –20~75˚C Min. Max. 260 130 130 130 130 130 130 130 Unit ns ns ns ns Note 2: Test Circuit Input VCC VCC RL PG CL 50Ω GND 4 Output DUT (1) Characteristics (10%~90%) of pulse generator (PG) tr=6ns, tf=6ns (2) Electrostatic capacitance CL includes the floating capacitance of connection and probe input capacitance. MITSUBISHI 〈DIGITAL ASSP〉 M66008P/FP 16-BIT I/O EXPANDER TIMING DIAGRAM tw tw VCC CLK 50% 50% 50% 50% VCC S GND GND tPLZ tPZL trec ≈ VCC DO 50% 10% VCC CS VOL GND tw tw VCC CS 50% 50% 50% 50% GND tPLZ tPZL ≈ VCC D1 ~ D16 50% 10% VOL tw VCC S 50% 50% GND tPLZ ≈ VCC DO D1 ~ D16 10% VOL VCC DI 50% 50% GND tsu th VCC CLK 50% GND VCC D1 ~ D16 50% 50% GND tsu th VCC CS 50% GND VCC CS 50% 50% GND th tsu VCC CLK 50% 50% GND 5