AP65550 5A, 18V, 650kHz ADAPTIVE COT STEP-DOWN CONVERTER Description Pin Assignments The AP65550 is an adaptive, constant, on-time mode synchronous buck converter providing high efficiency, excellent transient response and high DC output accuracy for low-voltage regulation in digital TV and monitor. The constant-on-time control scheme handles wide input/output voltage ratios and provides low, external component count. The internal proprietary circuit enables the device to adopt both low equivalent series resistance (ESR) output capacitors, such as SP-CAP or POSCAP and ultra-low ESR ceramic capacitors. The adaptive on-time control supports a seamless transition between continuous conduction mode (CCM) at higher load conditions and discontinuous conduction mode (DCM) at lighter load conditions. DCM allows AP65550 to maintain high efficiency at light-load conditions. The AP65550 also features programmable soft-start, UVLO, OTP and OCP to protect the circuit. This IC is available in SO-8EP and U-DFN3030-10 packages. Applications Features • Gaming Consoles • Fixed-Frequency Emulated Constant On-Time Control • Flat Screen TV Sets and Monitors • Good Stability Independent of the Output Capacitor ESR • Set-Top Boxes • Fast Load Transient Response • Distributed Power Systems • • Home Audio • Consumer Electronics • Wide Input Voltage Range: 4.5V to 18V • Network Systems • Output Voltage Range: 0.76V to 6V • • FPGA, DSP and ASIC Supplies Green Electronics • 5A Continuous Output Current • 650kHz Switching Frequency • Built-in Over Current Limit • Built-in Thermal Shutdown Protection • Programmable Soft-Start Notes: Synchronous Rectification: 65mΩ Internal High-Side Switch and 36mΩ Internal Low-Side Switch • Pre-Biased Start-Up • • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. AP65550 Document number: DS36336 Rev. 4 - 2 1 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Typical Applications Circuit INPUT VIN 12V ON OFF C1 20μF BST IN EN L1 C5 0.1µF 1.5μH SW AP65550 R1 8.25kΩ R2 22.1kΩ FB C4 8.2nF VREG5 SS OUTPUT VOUT 1.05V C2 44μF C3 1µF GND Figure 1. Typical Application Circuit Pin Descriptions Pin Name Pin Number Function SO-8EP U-DFN3030-10 EN 1 1 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn off. Pull up with 100kΩ resistor for automatic startup. FB 2 2 Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider connected to it from the output voltage. VREG5 3 3 Internal power supply output pin to connect an additional capacitor. Connect a 1µF (typical) capacitor as close as possible to the VREG5 and GND. This pin is not active when EN is low. SS 4 5 Soft-start control input pin. SS controls the soft start period. Connect a capacitor from SS to GND to set the soft-start period. GND 5 6 Ground pin is the main power ground for the switching circuit. SW 6 7, 8 BS 7 4 VIN 8 9, 10 EP — — AP65550 Document number: DS36336 Rev. 4 - 2 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high-side switch. Bootstrap pin. A bootstrap capacitor is connected between the BS pin and SW pin. The voltage across the bootstrap capacitor drives the internal high-side NMOS switch. A 0.1μF (typical) capacitor is required for proper operation. Supply input pin. A capacitor should be connected between the VIN pin and GND pin to keep the DC input voltage constant. Connect the exposed thermal pad to GND on the PCB. 2 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Functional Block Diagram Figure 2. Functional Block Diagram Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.) Symbol VIN VREG5 Parameter Rating Supply Voltage VREG5 Pin Voltage Unit -0.3 to 20 V -0.3V to +6.0 V VSW Switch Node Voltage -1.0 to VIN +0.3 V VBS Bootstrap Voltage -0.3 to VSW +6.0 V VFB Feedback Voltage -0.3V to +6.0 V VEN Enable/UVLO Voltage -0.3V to +6.0 V VSS Soft-Start PIN -0.3V to +6.0 V GND Pin Voltage -0.3 to 0.3 V TST Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C 2 kV 200 V VGND ESD Susceptibility (Note 5) Notes: HBM Human Body Model MM Machine Model 4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. AP65550 Document number: DS36336 Rev. 4 - 2 3 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Thermal Resistance (Note 6) Symbol Parameter θJA Junction to Ambient Rating Unit SO-8EP 39.4 °C/W θJC Junction to Case SO-8EP 8.6 °C/W θJA Junction to Ambient U-DFN3030-10 42 °C/W θJC Junction to Case U-DFN3030-10 6 °C/W Recommended Operating Conditions (Note 7) (@TA = +25°C, unless otherwise specified.) Symbol Notes: Parameter Min Max 4.5 18.0 V Operating Junction Temperature Range -40 +125 °C Operating Ambient Temperature Range -40 +85 °C VIN Supply Voltage TJ TA Unit 6. Test condition: SO-8EP, U-DFN3030-10: Device mounted on 2" x 2" FR-4 substrate PC board, 2oz copper with minimum recommended pad layout. 7. The device function is not guaranteed outside of the recommended operating conditions. Electrical Characteristics (@TA = +25°C, VIN = 12V, unless otherwise specified.) Parameter SUPPLY VOLTAGE (VIN PIN) Symbol Conditions Min — Typ Max Unit 4.5 — 18 V VFB=0.85V — 0.9 — mA ISHDN VEN=0V — 3.6 10 µA UVLO Threshold VUVLO VIN Rising Test VREG5 Voltage 3.45 3.75 4.05 V UVLO Hysteresis VHYS VIN Falling Test VREG5 Voltage 0.19 0.32 0.45 V VENH — 1.9 — — V VENL — — — 0.6 V Input Voltage VIN Quiescent Current IQ Shutdown Supply Current UNDER VOLTAGE LOCKOUT ENABLE (EN PIN) EN High-Level Input Voltage EN Low-Level Input Voltage VOLTAGE REFERENCE (FB PIN) Feedback Voltage VFB VOUT=1.05V 0.753 0.765 0.777 V Feedback Bias Current IFB VFB=0.8V -0.1 0 0.1 μA VREG5 OUTPUT VREG5 Output Voltage 6.0V<VIN<18V 0<IVREG5<5mA 4.7 5.1 5.5 V Source Current Capability — VIN=6V, VVREG5=4V — 110 — mA Load Regulation — 0<IVREG5<5mA — — 60 mV Line Regulation — 6.0V<VIN<18V IVREG5=5mA — — 20 mV MOSFET High-Side Switch On-Resistance Low-Side Switch On-Resistance VVREG5 RDSONH — — 0.065 — Ω RDSONL — — 0.036 — Ω 5.6 6.4 7.9 A CURRENT LIMIT High Level Current Limit ILIM-H L=1.5μH ON-TIME TIMER On Time Minimum Off Time tON tOFF-MIN VIN=12V, VOUT=1.05V — 150 — ns VFB=0.7V — 260 310 ns THERMAL SHUTDOWN Thermal Shutdown TOTSD — — +160 — °C Thermal Shutdown Hysteresis THYS — — +30 — °C VSS=1.2V 4.2 6.0 7.8 μA VSS=0.5V 0.1 0.2 — mA SOFT START (SS PIN) Soft-Start Source Current Soft-Start Discharge Current AP65550 Document number: DS36336 Rev. 4 - 2 ISS-SOURCE ISS-DISCHARGE 4 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Typical Performance Characteristics (@TA = +25°C, VIN = 12V, VOUT = 1.05V, unless otherwise specified.) AP65550 Document number: DS36336 Rev. 4 - 2 5 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Typical Performance Characteristics (cont.) (@TA = +25°C, VIN = 12V, VOUT = 1.05V, unless otherwise specified.) AP65550 Document number: DS36336 Rev. 4 - 2 6 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Typical Performance Characteristics (cont.) (@TA = +25°C, VIN = 12V, VOUT = 1.05V, L = 1.5µH, C1 = 20µF, C2 = 44µF, unless otherwise specified.) Steady State Test 5A Startup Through VIN No Load Startup Through VIN 5A Load VIN_AC (500mV/DIV) VIN (12V/DIV) VIN (12V/DIV) VOUT (1V/DIV) VOUT (1V/DIV) IOUT (1A/DIV) IOUT (5A/DIV) SW (10V/DIV) SW (10V/DIV) VOUT_AC (50mV/DIV) IOUT (5A/DIV) SW (5V/DIV) Time-500µs/div Time-1µs/div Startup with VREG5 No Load Shutdown Through VIN No load Time-500µs/div Shutdown Through VIN 5A Load VIN (12V/DIV) VIN (12V/DIV) VOUT (1V/DIV) VOUT (1V/DIV) IOUT (1A/DIV) IOUT (5A/DIV) EN (3V/DIV) VREG5 (5V/DIV) VOUT (500mV/DIV) SW (10V/DIV) SW (10V/DIV) Time-1ms/div Time-50ms/div Startup Through VEN No Load Startup Through VEN 5A Load Time-500µs/div Short Circuit Test VOUT (500mV/DIV) VEN (3V/DIV) VEN (3V/DIV) VOUT (1V/DIV) VOUT (1V/DIV) IOUT (1A/DIV) IOUT (5A/DIV) SW (10V/DIV) SW (10V/DIV) Time-1ms/div Shutdown Through VEN No load IOUT (2A/DIV) Time-100µs/div Time-1ms/div Shutdown Through VEN 5A Load Short Circuit Recovery VEN (3V/DIV) VEN (3V/DIV) VOUT (500mV/DIV) VOUT (1V/DIV) VOUT (1V/DIV) IOUT (5A/DIV) IOUT (1A/DIV) IOUT (2A/DIV) SW (10V/DIV) SW (10V/DIV) Time-20ms/div Time-20ms/div DCM Voltage Ripple (IO=30mA) Voltage Ripple at Output (IO=2A) Time-1ms/div Voltage Ripple at Input (IO=2A) VIN_AC (100mV/DIV) VOUT_AC (50mV/DIV) VOUT_AC (20mV/DIV) SW (5V/DIV) SW (5V/DIV) Time-1µs/div AP65550 Document number: DS36336 Rev. 4 - 2 SW (5V/DIV) Time-400ns/div 7 of 15 www.diodes.com Time-400µs/div January 2015 © Diodes Incorporated AP65550 Application Information Figure 3. Typical Application of AP65550SP (SO-8EP) Evaluation Board Figure 4. Typical Application of AP65550FN (U-DFN3030-10) Evaluation Board PWM Operation and Adaptive On-time Control The AP65550 is a synchronous step-down converter with internal-power MOSFETs. Adaptive constant on-time (COT) control is employed to provide fast transient response and easy loop stabilization. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal one-shot timer expires. This one shot is set by the converter input voltage (VIN), and the output voltage (VOUT) to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The output voltage variation is sensed by FB voltage. The one-shot timer is reset and the high-side MOSFET is turned on again when FB voltage falls below the 0.76V. AP65550 uses an adaptive on-time control scheme and does not have a dedicated in board oscillator. It runs with a pseudo-constant frequency of 650kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage. It can be calculated using the following equation: V TON = OUT VIN × f VOUT is the output voltage VIN is the input voltage f is the switching frequency After an ON-time period, the AP65550 goes into the OFF-time period. The OFF-time period length depends on VFB in most case. It will end when the FB voltage decreases below 0.76V, then the ON-time period is triggered. If the OFF-time period is less than the minimum OFF time, the minimum OFF time will be applied, which is typically about 260ns. Power Save Mode The AP65550 is designed with Power Save Mode (PSM) at light load conditions for high efficiency. The AP65550 automatically reduces the switching frequency and changes the TON time to TMIN-on time during a light load condition to get high efficiency and low output ripple. As the output current decreases from heavy load conditions, the inductor current decreases as well, eventually coming close to zero current, which is the boundary between CCM and DCM. The low-side MOSFET is turned off when the inductor current reaches zero level. The load is provided only by output capacitor, when FB voltage is lower than 0.76V, the next ON cycle begins. The on-time is the minimum on time that benefits for decreasing VOUT ripple at light load conditions. When the output current increases from light to heavy load the switching frequency increases to keep output voltage. The transition point to light load operation can be calculated using the following equation: AP65550 Document number: DS36336 Rev. 4 - 2 8 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Application Information (cont.) V −V ILOAD = IN OUT ×TON 2L TON is on-time Enable Above the ‘EN high-level input voltage’, the internal regulator is turned on and the quiescent current can be measured above this threshold. The enable (EN) input allows the user to control turning on or off the regulator. To enable the AP65550, EN must be pulled above the ‘EN high-level input voltage.’ To disable the AP65550, EN must be pulled below ‘EN low-level input voltage.’ In Figures 3 and 4, EN has a positive voltage through a 100KΩ pull-up to VIN. No supply input is required for EN. Soft-Start The soft-start time of the AP65550 is programmable by selecting a different CSS value. When the EN pin becomes high, the CSS is charged by a 6μA current source, generating a ramp signal fed into non-inverting input of the error comparator. Reference voltage VREF or the internal soft-start voltage SS, whichever is smaller, dominates the behavior of the non-inverting inputs of the error amplifier. Accordingly, the output voltage will follow the SS signal and ramp up smoothly to its target level. The capacitor value required for a given soft-start ramp time can be expressed as: C ×V tSS = SS FB ISS Where CSS is the required capacitor between SS pin and GND, tSS is the desired soft-start time and VFB is the feedback voltage. Over Current Protection (OCP) Figure 5 shows the over current protection (OCP) scheme of AP65550. In each switching cycle, the inductor current is sensed by monitoring the low-side MOSFET in the OFF period. When the voltage between GND pin and SW pin is smaller than the over current trip level, the OCP will be triggered and the controller keeps the OFF state. A new switching cycle will begin when the measured voltage is larger than limit voltage. The internal counter is incremented when OCP is triggered. After 16 sequential cycles, the internal OCL (Over Current Logic) threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is below the lower OCL threshold, the counter is reset and the OCL limit is returned to a higher value. Because the RDS(ON) of MOSFET increases with temperature, VLimit has xppm/°C temperature coefficient to compensate this temperature dependency of RDS(ON). Figure 5. Over Current Protection Scheme Under Voltage Lockout The AP65550 provides an under-voltage lockout circuit to prevent it from undefined status during startup. The UVLO circuit shuts down the device when VIN drops below 3.45V. The UVLO circuit has 320mV hysteresis, which means the device starts up again when VREG rises to 3.75V (nonlatch). Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown limit of 160°C, the AP65550 shuts itself off, and both HMOS and LMOS will be turned off. The output is discharged with the internal transistor. When the junction cools to the required level (130°C nominal), the device initiates soft-start as during a normal power-up cycle. Setting the Output Voltage The output voltage can be adjusted from 1.000 to 5V using an external resistor divider. Table 1 shows a list of resistor selections for common output voltages. Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network. However the tradeoff is output voltage accuracy due to the bias current in the error amplifier. R1 can be determined by the following equation: ⎞ ⎛V R1 = R 2 ⋅ ⎜⎜ OUT − 1⎟⎟ ⎠ ⎝ 0.765 AP65550 Document number: DS36336 Rev. 4 - 2 9 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Application Information (cont.) Output Voltage (V) R1 (kΩ) R2 (kΩ) 1 6.81 22.1 1.05 8.25 22.1 1.2 12.7 22.1 1.5 21.5 22.1 1.8 30.1 22.1 2.5 49.9 22.1 3.3 73.2 22.1 5 124 22.1 Figure 6. Feedback Divider Network Table 1. Resistor Selection for Common Output Inductor Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate the inductor value: L= VOUT ⋅ (VIN − VOUT ) VIN ⋅ ∆IL ⋅ fSW Where ∆IL is the inductor ripple current and fSW is the buck converter switching frequency. Choose the inductor ripple current to be 30% of the maximum load current. The maximum inductor peak current is calculated from: IL(MAX) = ILOAD + ∆IL 2 Peak current determines the required saturation-current-rating, which influences the size of the inductor. Saturating the inductor decreases the converter efficiency while increasing the temperatures of the inductor and the internal MOSFETs. Hence choosing an inductor with appropriate saturation current rating is important. A 1µH to 3.3µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor’s DC resistance should be less than 100mΩ. Use a larger inductance for improved efficiency under light load conditions. The phase boost can be achieved by adding an additional feed forward capacitor (C7) in parallel with R1. Output Voltage (V) 1 1.05 1.2 1.5 1.8 2.5 3.3 5 C7(pF) — — — — 5-22 5-22 5-22 5-22 L1(µH) 1.0-1.5 1.0-1.5 1.0-1.5 1.5 1.5 2.2 2.2 3.3 C8+C9(µF) 22-68 22-68 22-68 22-68 22-68 22-68 22-68 22-68 Table 2. Recommended Component Selection Input Capacitor The input capacitor reduces the surge current drawn from the input supply and the switching noise from the device. The input capacitor has to sustain the ripple current produced during the on time on the upper MOSFET. It must have a low ESR to minimize the losses. The RMS current rating of the input capacitor is a critical parameter that must be higher than the RMS input current. As a rule of thumb, select an input capacitor which has an RMS rating greater than half of the maximum load current. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used it must be surge protected, otherwise capacitor failure could occur. For most applications greater than 10µF, a ceramic capacitor is sufficient. AP65550 Document number: DS36336 Rev. 4 - 2 10 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Application Information (cont.) Output Capacitor The output capacitor keeps the output voltage ripple small, ensures feedback loop stability and reduces the overshoot of the output voltage. The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The converter recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. Maximum capacitance required can be calculated from the following equation: ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated from the equation below: Voutcapacitor = ∆Iinductor * ESR An output capacitor with ample capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor will be sufficient. ∆Iinductor 2 ) 2 Co = 2 (∆ V + Vout ) − Vout2 L(Iout + Where ∆V is the maximum output voltage overshoot. Bootstrap Capacitor To ensure the proper operation, a ceramic capacitor must be connected between the VBST and SW pin. A 0.1µF ceramic capacitor is sufficient. VREG5 Capacitor To ensure the proper operation, a ceramic capacitor must be connected between the VREG5 and GND pin. A 1µF ceramic capacitor is sufficient. PC Board Layout 1. The AP65550 works at a 5A load current. Heat dissipation is a major concern in the PCB layout. A 2oz Copper in both the top and bottom layer is recommended. 2. Provide sufficient vias in the thermal exposed pad for heat to dissipate to the bottom layer. 3. Provide sufficient vias in the Output capacitor GND side to dissipate heat to the bottom layer. 4. Make the bottom layer under the device as the GND layer for heat dissipation. The GND layer should be as large as possible to provide 5. a better thermal effect. Make the VIN capacitors as close to the device as possible. 6. Make the VREG5 capacitor as close to the device as possible. 7. The thermal pad of the device should be soldered directly to the PCB exposed copper plane to work as a heatsink. The thermal vias in the exposed copper plane increase the heat transfer to the bottom layer. Figure 7: PC Board Layout for SO-8EP AP65550 Document number: DS36336 Rev. 4 - 2 Figure 8: PC Board Layout for U-DFN3030-10 11 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Ordering Information Part Number Package Code Package AP65550SP-13 AP65550FN-7 SP FN SO-8EP U-DFN3030-10 Quantity Tape and Reel Part Number Suffix 2,500 3,000 -13 -7 Marking Information SO-8EP U-DFN3030-10 AP65550 Document number: DS36336 Rev. 4 - 2 Part Number Package Identification Code AP65550FN-7 U-DFN3030-10 TJ 12 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Package Outline Dimensions (All dimensions in mm.) Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version. SO-8EP Exposed Pad 8 5 E1 1 H 4 F b Bottom View 9° (All sides) N 7° A e Q 4° ± 3° E0 A1 D E 45° C Gauge Plane Seating Plane SO-8EP (SOP-8L-EP) Dim Min Max Typ A 1.40 1.50 1.45 A1 0.00 0.13 b 0.30 0.50 0.40 C 0.15 0.25 0.20 D 4.85 4.95 4.90 E 3.80 3.90 3.85 E0 3.85 3.95 3.90 E1 5.90 6.10 6.00 e 1.27 F 2.75 3.35 3.05 H 2.11 2.71 2.41 L 0.62 0.82 0.72 N 0.35 Q 0.60 0.70 0.65 All Dimensions in mm L U-DFN3030-10 A3 A SEATING PLANE A1 D D2 Pin#1 ID E E2 L z e b AP65550 Document number: DS36336 Rev. 4 - 2 U-DFN3030-10 Dim Min Max Typ A 0.57 0.63 0.60 A1 0 0.05 0.02 A3 0.15 ⎯ ⎯ b 0.20 0.30 0.25 D 2.90 3.10 3.00 D2 2.30 2.50 2.40 e 0.50 ⎯ ⎯ E 2.90 3.10 3.00 E2 1.50 1.70 1.60 L 0.25 0.55 0.40 z ⎯ ⎯ 0.375 All Dimensions in mm 13 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 Suggested Pad Layout Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version. SO-8EP X2 Y1 Y2 X1 Y C Dimensions Value(in mm) C 1.270 X 0.802 X1 3.502 X2 4.612 Y 1.505 Y1 2.613 Y2 6.500 X U-DFN3030-10 Y C X1 G X G Dimensions Value (in mm) Z 2.60 G 0.15 X 1.80 X1 0.60 Y 0.30 C 0.50 Z AP65550 Document number: DS36336 Rev. 4 - 2 14 of 15 www.diodes.com January 2015 © Diodes Incorporated AP65550 IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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