TI CSD18504KCS

CSD18504KCS
www.ti.com
SLPS365 – OCTOBER 2012
40-V, N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD18504KCS
FEATURES
1
•
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Ultra Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Logic Level
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
TO-220 Plastic Package
TA = 25°C
UNIT
Drain to Source Voltage
40
V
Qg
Gate Charge Total (10V)
19
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
Threshold Voltage
3.5
nC
VGS = 4.5V
8.0
mΩ
VGS = 10V
5.5
mΩ
1.9
V
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
CSD18504KCS
TO-220 Plastic
Package
Tube
50
Tube
APPLICATIONS
•
•
•
TYPICAL VALUE
VDS
DC-DC Conversion
Secondary Side Synchronous Rectifier
Motor Control
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
DESCRIPTION
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications.
VALUE
UNIT
VDS
Drain to Source Voltage
40
V
VGS
Gate to Source Voltage
±20
V
Continuous Drain Current (Package limited),
TC = 25°C
100
Continuous Drain Current (Silicon limited),
TC = 25°C
85
Continuous Drain Current (Silicon limited),
TC = 100°C
53
IDM
Pulsed Drain Current (1)
133
A
PD
Power Dissipation
93
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 42A, L = 0.1mH, RG = 25Ω
88
mJ
ID
A
(1) Pulse duration ≤300μs, duty cycle ≤2%
RDS(on) vs VGS
GATE CHARGE
10
TC = 25°C Id = 40A
TC = 125ºC Id = 40A
18
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
20
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 40A
VDS = 20V
9
8
7
6
5
4
3
2
1
0
0
4
8
12
Qg - Gate Charge (nC)
16
20
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
CSD18504KCS
SLPS365 – OCTOBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 32V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 20V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250μA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
40
1.5
V
1
μA
100
nA
1.9
2.3
V
VGS = 4.5V, ID = 40A
8.0
10.0
mΩ
VGS = 10V, ID = 40A
5.5
7.0
mΩ
VDS = 20V, ID = 40A
72
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
1380
1800
pF
320
416
pF
8.0
10.4
pF
Series Gate Resistance
1.5
3.0
Ω
Qg
Gate Charge Total (4.5V)
9.2
12.0
nC
Qg
Gate Charge Total (10V)
19
25
nC
Qgd
Gate Charge Gate to Drain
Qgs
Qg(th)
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VDS = 20V, f = 1MHz
VDS = 20V, ID = 40A
3.5
nC
Gate Charge Gate to Source
4.4
nC
Gate Charge at Vth
3.0
nC
19
nC
4.4
ns
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 10V,
IDS = 40A, RG = 0Ω
5.2
ns
11.2
ns
4.2
ns
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 40A, VGS = 0V
0.8
VDS= 20V, IF = 40A,
di/dt = 300A/μs
46
1
nC
V
33
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Thermal Resistance Junction to Case
PARAMETER
1.4
°C/W
RθJA
Thermal Resistance Junction to Ambient
62
°C/W
2
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MIN
TYP
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD18504KCS
CSD18504KCS
www.ti.com
SLPS365 – OCTOBER 2012
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
100
80
60
40
VGS =10V
VGS =6.5V
VGS =4.5V
20
0
0
0.2
0.4
0.6
0.8
1
VDS - Drain-to-Source Voltage (V)
1.2
1.4
VDS = 5V
80
60
40
TC = 125°C
TC = 25°C
TC = −55°C
20
0
0
G001
Figure 2. Saturation Characteristics
1
2
3
4
VGS - Gate-to-Source Voltage (V)
Product Folder Links: CSD18504KCS
G001
Figure 3. Transfer Characteristics
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Copyright © 2012, Texas Instruments Incorporated
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3
CSD18504KCS
SLPS365 – OCTOBER 2012
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 40A
VDS = 20V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
2
1
0
0
4
8
12
Qg - Gate Charge (nC)
16
10
20
0
10
20
30
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
20
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
ID = 250uA
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
−75
−25
25
75
125
TC - Case Temperature (ºC)
TC = 25°C Id = 40A
TC = 125ºC Id = 40A
18
16
14
12
10
8
6
4
2
0
175
0
2
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
18
20
G001
TEXT ADDED FOR SPACING
VGS = 4.5V
VGS = 10V
ID =40A
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
100
ISD − Source-to-Drain Current (A)
2
4
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
2.2
Normalized On-State Resistance
G001
Figure 5. Capacitance
2.5
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
4
40
1
G001
Figure 9. Typical Diode Forward Voltage
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD18504KCS
CSD18504KCS
www.ti.com
SLPS365 – OCTOBER 2012
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
1ms
10ms
1000
100ms
1s
DC
100
10
1
0.1
Single Pulse
Typical RthetaJA = 55ºC/W
0.01
0.01
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
5000
0.1
1
10
VDS - Drain-to-Source Voltage (V)
100
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD18504KCS
5
CSD18504KCS
SLPS365 – OCTOBER 2012
www.ti.com
MECHANICAL DATA
KCS Package Dimensions
Notes:
1. All linear dimensions are in inches
2. This drawing is subject to change without notice
3. Lead Dimensions are not controlled within "C" area
4. All lead dimensions apply before solder dip
5. The center lead is in electrical contact with the mounting tab
6. The chamfer at "F" is optional
7. Thermal pad contour at "G" optional with these dimensions
8. "H" Falls within JEDEC TO-220 variation AB, except minimum lead thickness, minimum exposed pad length,
and maximum body length.
Table 1. Pin Configuration
6
Position
Designation
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD18504KCS
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD18504KCS
ACTIVE
Package Type Package Pins Package Qty
Drawing
TO-220
KCS
3
50
Eco Plan
Lead/Ball Finish
(2)
Pb-Free (RoHS
Exempt)
CU SN
MSL Peak Temp
Samples
(3)
(Requires Login)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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