MP020-5

MP020-5
Offline, Primary-Side Regulator
with CC/CV Control and a 700V FET
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP020-5 is an offline, primary-side
regulator that provides accurate constant
voltage and constant current regulation without
an opto-coupler or a secondary feedback circuit.
It has an integrated 700V MOSFET.
•
The MP020-5's variable off-time control allows
a flyback converter to operate in discontinuous
conduction mode. The MP020-5 also features
protection functions such as VCC under-voltage
lockout,
over-current
protection,
overtemperature protection, open circuit protection
(OCkP) and over-voltage protection. Its internal
high-voltage start-up current source and powersaving technologies limit the no-load power
consumption to less than 30mW.
The MP020-5's variable-switching-frequency
technology provides natural spectrum shaping
to smooth the EMI signature, making it suitable
for offline, low-power battery chargers and
adapters.
The MP020-5 is available in SOIC8-7A.
Part Num.
RON
MP020-5GS
10Ω
Maximum Output
Power (85-265Vac)
Open
Adapter
Frame
5W
8W
•
•
•
•
•
•
•
•
•
•
Primary-Side–Control without Opto-Coupler
or Secondary Feedback Circuit
Precise Constant Current and Constant
Voltage Control (CC/CV)
Integrated 700V MOSFET with Minimal
External Components
Variable, Off-Time, Peak-Current Control
550µA High-Voltage Current Source
30mW No-Load Power Consumption
Programmable Cable Compensation
Multiple Protections: OVP, OCP, OCkP,
OTP, and VCC UVLO
Natural Spectrum Shaping for Improved
EMI Signature
Low Cost and Simple External circuit
SOIC8-7A Package
APPLICATIONS
•
•
•
•
Cell Phone Chargers
Adapters for Handheld Electronics
Stand-By and Auxiliary Power Supplies
Small Appliances
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology”, are Registered Trademarks
of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP020-5 Rev. 1.05
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
ORDERING INFORMATION
Part Number*
MP020-5GS
Package
SOIC8-7A
Top Marking
MP020-5
* For Tape & Reel, add suffix –Z (e.g. MP020-5GS–Z);
PACKAGE REFERENCE
8
SOIC8-7A
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Drain to GND ............................... -0.7V to 700V
VCC to GND.................................... -0.3V to 30V
CP to GND....................................... -0.3V to 7V
FB Input......................................... -0.7V to 10V
(2)
Continuous Power Dissipation (TA = +25°C)
SOIC8-7A…………………………………...1.3W
Junction Temperature.............................. 150°C
Lead Temperature ................................... 260°C
Storage Temperature............... -60°C to +150°C
ESD Capability Human Body Mode ..........2.0kV
ESD Capability Machine Mode ..................200V
SOIC8-7A .............................. 76 ...... 45... °C/W
Recommended Operating Conditions
(3)
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Operating Junction Temp. (TJ). -40°C to +125°C
Operating VCC range ..................... 6.6V to 28V
MP020-5 Rev. 1.05
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
ELECTRICAL CHARACTERISTICS
VCC = 15V, TA = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
16.8
17.3
17.8
V
VCC OFF threshold
VCCL
VCC operating voltage
Quiescent current
IQ
At no load condition, VCC=20V
Operating current
IOP
60kHz, VCC=20V
Leakage current from VCC Pin ILeak_VCC VCC=0VÆ16V, Drain float
Internal MOSFET (Drain Pin)
6
6.6
6.3
6.6
28
410
V
V
μA
μA
μA
Break-down Voltage
VBRDSS VCC=20V, VFB=7V
700
Supply current from Drain Pin
Leakage current from Drain
Pin
On-state resistance
Minimum switching frequency
Internal Current Sense
ICharge
450
Supply Voltage Management (VCC Pin)
VCC ON threshold
VCCH
Current limit
Leading-edge blanking
Feedback input (FB Pin)
FB pin input current
Feedback threshold
DCM detect threshold
FB open-circuit threshold
FB OVP threshold
ILeak_Drain
VCC=4V, VDrain=100V
VDS=500VDC
RON
fMIN
ID=10mA, TJ=20°C
At no load condition
ILimit
tLEB
VFB=-0.5V
IFB
VFB=4V, VCP=3V
VFB
VDCM
VFBOPEN
VFBOVP
OVP sample delay
tOVP
Output Cable Compensation (CP Pin)
Cable compensation voltage
Thermal Shutdown
Thermal shutdown threshold
Thermal shutdown recovery
threshold
VCP
Full load
360
500
0.1
1
V
550
750
µA
1
10
µA
10
120
13
Ω
Hz
365
230
380
300
395
370
mA
ns
12
3.93
80
-0.22
6.2
16
4
120
-0.15
6.35
20
4.07
160
-0.08
6.5
μA
V
mV
V
V
3.5
µs
2
V
150
°C
120
°C
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TYPICAL CHARACTERISTICS
4.0
700
650
600
Leakage Current vs.
Junction Temperature
800
3.0
750
2.0
1.5
500
25
0.0
-50 -25
50 75 100 125
VCC ON Threshold vs.
Junction Temperature
7.00
17.0
VCCL(V)
VCCH(V)
17.5
16.5
16.0
15.5
15.0
-50 -25
0
25
DCM Detect Threshold
vs. Temperature Chart
50
500
-50 -25
75 100 125
4.075
6.50
4.050
6.25
4.025
6.00
3.975
5.50
3.950
5.25
3.925
0
25
3.900
-50 -25
50 75 100 125
FB Open Circuit Threshold
vs. Junction Temperature
0.110
0.100
-50 -25
-0.080
-0.100
-0.120
-0.140
25
50 75 100 125
-0.200
-50 -25
25
50 75 100 125
FB OVP Threshold vs.
Junction Temperature
7.000
6.250
6.000
5.750
5.500
5.250
-0.180
0
0
6.500
-0.060
-0.160
0.105
75 100 125
6.750
VFB_OVP(V)
VFB_OPEN(V)
VDCM(V)
0.115
50
4.000
5.75
-0.040
0.120
25
4.100
-0.020
0.125
0
Feedback Threshold vs.
Junction Temperature
6.75
0.000
0.130
25
VCC OFF Threshold vs.
Junction Temperature
5.00
-50 -25
50 75 100 125
0
VFB(V)
0
650
550
0.5
400-50 -25
700
600
1.0
450
18.0
850
3.5
2.5
550
Breakdown Voltage vs.
Junction Temperature
VBRDSS(V)
Charge Current vs.
Junction Temperature
0
25
50 75 100 125
5.000
-50 -25
0
25
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50 75 100 125
4
MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TYPICAL CHARACTERISTICS (CONTINUED)
OVP Sample Delay vs.
Junction Temperature
On State Resistance vs.
Junction Temperature
400
CURRENT ILIMIT(mA)
20
5.0
4.5
15
4.0
10
3.5
3.0
5
2.5
2.0
-50 -25
Current ILimit vs.
Junction Temperature
0
25
50
75 100 125
0
-50 -25
0
25
50
75 100 125
390
380
370
360
350
-50 -25
0
25
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50
75 100 125
5
MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 230Vac, VOUT = 5V, IOUT=1A, L = 1.6mH, TA = 25°C, unless otherwise noted.
Input Power Startup
Input Power Shut Down
VDS
100V/div.
VDS
100V/div.
VOUT
2V/div.
VOUT
2V/div.
OCkP Recovery
VDS
100V/div.
VCC
5V/div.
VFB
2V/div.
OVP Entry
VCC
10V/div.
VDS
100V/div.
VFB
2V/div.
VOUT
2V/div.
VDS
100V/div.
VCC
5V/div.
VFB
2V/div.
OCkP Entry
Output Voltage Ripple
OVP Recovery
VCC
10V/div.
VDS
100V/div.
VFB
2V/div.
VOUT
2V/div.
Load Transient
VOUT
AC Coupled
50mV/div.
VOUT
1V/div.
IOUT
200mA/div.
Normal Operation
VDS
100V/div.
VFB
1V/div.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT=1A, L = 1.6mH, TA = 25°C, unless otherwise noted.
MP020-5 CV/CC Characteristic
25℃ CV/CC
5
4
Vo(V)
3
2
265Vac
230Vac
115Vac
1
85Vac
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Io(A)
0.7
0.8
0.9
1
MP020-5 Rev. 1.05
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1.1
7
MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
PIN FUNCTIONS
SOIC8-7A
Name Description
Pin #
1
3
4
2, 5, 6
8
Supply. IC begins functioning when VCC charges to VCCH through an internal high-voltage
VCC current source. When VCC falls below VCCL, the internal high-voltage current source turns on
to charge VCC. Connect 0.1µF decoupling ceramic capacitor for most applications.
Feedback. Provides the output reference voltage and detects falling voltage edges to
FB
determine the operation mode (CV mode and CC mode).
Output Cable Compensation. Connect a 1μF ceramic capacitor as a low pass filter. The
CP
upper resistor of resistor divider connected to FB adjusts the compensation voltage.
GND Ground.
Drain Internal MOSFET Drain. Input for the high-voltage start-up current source.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
FUNCTIONAL BLOCK DIAGRAM
Protection
Unit
FB
Power
Management
VCC
Start Up Unit
Constant
Current Control
DRV
Driving Signal
Management
Constant
Voltage Control
CP
Drain
Current
Sense
Cable
Compensation
GND
Figure 1: Functional Block Diagram
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
OPERATION
VD
NS
iS
NP
Working Principle
After startup, the internal MOSFET turns on and
the current sense resistor (RCS) senses the
primary current iP(t) internally. The current rises
linearly at a rate of:
NP_AU
iP
diP (t) VIN
=
dt
LM
VAUX
IPK
iP
Figure 2: Simplified Flyback Converter
Startup
Initially, the IC is self-supplying through the
internal high-voltage current source, which is
drawn from the Drain pin. The internal highvoltage current source will turn off for better
efficiency when VCC reaches the VCC ON
threshold. Then the transformer’s auxiliary
winding takes over as the power source. When
VCC falls below the VCC OFF threshold, the IC
stops switching and the internal high-voltage
current source turns on again. See Figure 3 for
the start-up waveform.
Vcc
0
Figure 4: Primary Current Waveform
As illustrated in Figure 4, when iP(t) rises up to
IPK, the internal MOSFET turns off. Then, the
energy stored in the inductor transfers to
secondary-side through the transformer.
The inductor, LM, stores energy with each cycle
as a function of:
E=
So the power transferred from the input to the
output is:
P=
VCCH
V CCL
1
2
LM × IPK
2
1
2
LM × IPK
× fS
2
Where fS is the switching frequency. When IPK is
constant, the output power depends on fS.
Drain
Switching Pulses
Constant-Voltage Operation
The MP020-5 detects the auxiliary winding
voltage from the FB pin and operates in
constant voltage (CV) mode to regulate the
output voltage.
High-voltage
current source
ON
OFF
Assume the secondary winding is the master
and the auxiliary winding is the slave. When the
secondary-side diode turns on, the FB pin
voltage is:
Figure 3: VCC UVLO
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
VFB =
NP _ AU
NS
× (VO + VD ) ×
RDOWN
RUP + RDOWN
In constant current (CC) operation, the product
of VZCD and Ipk approximately equals IO_REF:
IO _ REF = VZCD × IPK
Where
•
VD is the secondary-side-diode forward-drop
voltage,
•
Vo is the output voltage,
•
NP_AU and NS are the number of auxiliary
winding and secondary side winding turns
(respectively), and
•
RUP and RDOWN are the resistor-divider for
sampling.
Figure 5: Auxiliary Voltage Waveform
The output voltage differs from the secondary
voltage due to the current-dependant forwarddiode voltage drop. If the secondary voltage is
always detected at a fixed secondary current,
the difference between the output voltage and
the secondary voltage is a fixed VD. The
MP020-5 samples the auxiliary winding voltage
3.5µs after the primary switch turns off. The CV
loop control function turns the secondary side
diode off to regulate the output voltage.
Figure 6 shows the constant-current operation.
ZCD
Sample
VZCD
IPK
Io estimator
IO =
1 NP
×
× IO _ REF
2 NS
The MP020-5 maintains IO_REF as 0.152A.
Leading-Edge Blanking
The parasitic capacitances induce a spike on
the sense resistor when the power switch turns
on. The MP020-5 includes a 300ns leadingedge blanking period to avoid falsely
terminating the switching pulse. During this
blanking period, the current sense comparator
is disabled and the gate driver can not switch
off. Figure 7 shows the leading-edge blanking.
t LEB
VLimit
t
Figure 7: Leading-Edge Blanking
Constant Current Operation
VFB
So, the calculated output current from the IO
estimator block compares with reference value,
IO_REF, and the error signal, VCOMP_I, controls the
turn on signal of the integral MOSFET. So IO is
then.
VCOMP_I
DCM Detection
The MP020-5 operates in discontinuous
conduction mode (DCM) in both CV and CC
modes. To avoid operating in continuous
conduction mode (CCM), the MP020-5 detects
the falling edge of the FB input voltage with
each cycle. If the chip does not detect a 120mV
falling edge, it will stop switching.
IO_REF
Figure 6: CC Control Loop
The flyback always works in DCM, and the ZCD
sample block can detect the duty cycle of the
secondary-side diode.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
OVP & OCkP
The MP020-5 includes over-voltage protection
(OVP) and open-circuit protection (OCkP). If the
voltage at the FB pin exceeds 6.35V for 3.5µs,
or the FB input’s 0.15V falling edge cannot be
monitored, the MP020-5 immediately shuts off
the driving signals and enters hiccup mode. The
MP020-5 resumes normal operation when the
fault has been removed.
Thermal Shutdown (TSD)
When the temperature of the IC exceeds 150°C,
over-temperature protection (OTP) triggers and
the IC enters the auto recovery mode. When
the temperature falls below 120°C, the IC will
recover.
VFCP =
5.6 × DS
N
× 2 × RUP × S ;
3
360 × 10
NP _ AU
Where:
• VFCP is the secondary-side compensation
voltage drop,
• DS is the secondary-diode duty cycle in CC
mode (0.4 for the MP020-5),
• RUP is the upper resistor of resistor divider,
• NS is the number of turns for the secondaryside transformer windings, and
•
NP_AU is the number of transformer auxiliary
winding turns.
Output Cable Compensation
In order to compensate the secondary side
cable voltage drop for a more precise output
voltage, the MP020-5 has an internal output
cable compensation circuit as shown in Figure
8. The internal ZCD sample can detect the duty
of the secondary-side diode. A low-pass filter
converts the duty signal to a DC voltage (VCP)
that changes as the load current varies.
VCP can be converted to a current signal drawn
from the FB pin. The voltage drop on RUP helps
the output cable compensation. When the
system operates in maximum load, the CP pin
voltage reaches a maximum of 2V.
T1
RUP
*
V FCP
*
Vo
FB
RDOWN
+ V CP
CP
DS
Figure 8: Output Cable Compensator
The
equation
below
compensation voltage:
determines
the
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
APPLICATION INFORMATION
COMPONENT SELECTION
Input Filter
The input filter helps convert the AC input to a
DC source through the rectifier. Figure 9 shows
the input filter, and Figure 10 shows the typical
DC bus voltage waveform.
L
+
R
C1 +
AC Input
C2
+
DC Input
VDC(max)
DC input voltage
VDC(min)
AC input voltage
VAC
t
0
Figure 10: DC Input Voltage Waveform
Bulk capacitors (C1 and C2) filter the rectified AC
input. The inductor (L) forms a π filter with C1
and C2 to restrain the differential-mode EMI
noise. The resistor (R) in parallel with L restrains
the mid-frequency-band EMI noise. Normally, the
R is 1kΩ to 10kΩ.
C1 and C2 are usually set 2µF/W to 3µF/W for
the universal input condition. For 230VAC singlerange applications, halve the capacitor values.
Avoid very low minimum DC voltages to ensure
that the converter can supply the maximum
power load, which can be expressed as:
VDC(min) ≥
NP
DS
⋅ (VO + VD ) ⋅
NS
1 − DS
Output Capacitor
Use low ESR or very low ESR output capacitors
to meet the output voltage ripple requirement
without using an LC post filter. In addition, using
low ESR capacitors improves output voltage
regulation and feedback voltage sampling at high
temperatures or low temperatures. Use an output
capacitor with an ESR lower than 100mΩ for
better efficiency over non-low ESR output
capacitors.
Output Diode
Use a Schottky diode because of its fast
switching speed and low forward-voltage drop for
better high or low temperature CV regulation and
efficiency.
If the lower average efficiency (3% to 4%) is
acceptable, replace the output diode could with a
fast or ultra-fast diode to reduce costs. Be sure to
readjust the resistor divider values to for the
correct output voltage because of the forward
voltage drop is higher than the Schottky diode’s.
Figure 9: Input Filter
Vin
If VDC(min) can not satisfy this expression, increase
the value of the input capacitors to increase the
VDC(min).
Leakage Inductance
The transformer’s leakage inductance will
decrease the system efficiency and affect the
output current or voltage constant precision.
Optimize the transformer structure to minimize
the leakage inductance. Aim for a leakage
inductance less than 5% of the primary
inductance.
RCD Snubber
The transfomer’s leakage inductance causes the
MOSFET drain voltage to spike and the
excessive ringing on the drain voltage waveform,
which affects the output voltage sampling 3.5µs
after the MOSFET turns off.
The RCD snubber circuit can limit the Drain
voltage spike. Figure 11 shows the RCD snubber
circuit.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
CSN
RSN
power loss and the acceptable clamp voltage in
practical applications.
-
V SN
+
*
+
LM
DSN
*
R
LK
MP020-5
VCC
Drain
FB
CP
GND
Figure 11: RCD Snubber
The damping resistor in series with the RCD
has a relatively large value to prevent any
excessive voltage ringing that can affect the CV
sampling and increase the output ripple. Use a
damping resistor value in the range of 200Ω to
500Ω to restrain the drain-voltage ringing.
Divided Resistor
For better application performance, the select
the resistor divider values from 10kΩ to 100kΩ
to limit noise from adjacent components on the
FB pin. If necessary, use a resistor between
1kΩ and 2kΩ connected between the FB pin
and resistor divider limit substrate-injectioncurrent effects, as shown in Figure 12.
Select RSN and CSN to meet the voltage spike
requirements and improve system operation.
The power dissipated in the snubber circuit is
approximately.
PSN =
VSN
1
⋅ LK ⋅ IPK 2 ⋅
× fS
2
VSN − NPS × VO
Where:
RUP
RFB
RDOWN
•
LK is the leakage inductance,
•
VSN is the clamp voltage, and
•
NPS is the turn ratio of primary and
secondary side.
Since RSN consumes the majority of the power,
RSN is approximately,
RSN =
VSN2
PSN
The maximum ripple of the snubber capacitor
voltage is then:
ΔVSN =
VSN
CSN ⋅ RSN ⋅ fS
Generally, 15% ripple is reasonable, So the
previous equation can estimate CSN.
Normally, select a time constant (τ=RSN×CSN)
less than 0.1ms for better CV sampling.
Therefore, adjust the resistor based on the
Figure 12: Feedback Resistor Divider Circuit
For more accurate CV regulation, the accuracy
of these feedback resistors should be at least
1%.
Dummy Load
When system operates without any load and no
dummy load, the output voltage will rise above
normal operation because of the minimum
switching frequency limitation. Use a dummy
load for good load regulation. A large dummy
load will deteriorate efficiency and no-load
consumption, so the dummy load is tradeoff
between efficiency and load regulation. For
most applications, use a dummy load of around
10mW as it also satisfies the 30mW
requirement.
Maximum Switching Frequency
Use a secondary-side diode conduction time
that exceeds 5.4µs, as per the following
equation.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TS _ ON = IPK ⋅
NS ⋅ L M
> 5.4μs
NP ⋅ (VO + VD )
For high- or low-temperature applications,
select a maximum switching frequency below
75kHz.
PCB Layout Guide
PCB layout is very important to achieve reliable
operation, good EMI, and good thermal
performance. The following describe some
layout recommendations.
1. Minimize the loop area formed by the input
capacitor, the MP020-5 drain-source, and the
primary winding to reduce EMI noise.
Top Layer
2. The copper area connected to GND pins is
the heat conduction path for the MP020-5.
Provide at least 1 in2 of top-side copper for
adequate heat-sinking.
3. Minimize the clamp circuit loop to reduce EMI.
4. Minimize the secondary loop area of the
output diode and output filter to reduce EMI
noise. In addition, sufficient copper area should
be provided at the anode and cathode terminal
of the output diode to act as a heat sink.
5. Place the AC input away from the switching
nodes to minimize the noise coupling that may
bypass the input filter.
6. Place the bypass capacitor as close as
possible to the IC and source.
7. Place the feedback resistors next to the FB
pin and minimize the feedback sampling loop to
minimize noise coupling.
8. Use a single point connection at the negative
terminal of the input filter capacitor for the
MP020-5 source pin and bias winding return.
Figure 13 shows a sample layout.
Bottom Layer
Figure 13: PCB Layout
Design Example
Below is a design example following the
application guidelines based on these
specifications:
Table 1: Design Example
VIN
VOUT
IOUT
fS
85Vac~265Vac
5V
1A
60kHz
Figure 14 shows the detailed application
schematic This circuit was used for the typical
performance and circuit waveforms. For more
device applications, please refer to the related
evaluation board datasheets.
The transformer structure used in figure 14
could be benefit to pass the 3 wire Conducted
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
EMI (Output GND connect to earth) without Y
cap. The Y cap will bring about the leakage
current which is prohibited in some cell phone
charger application. Figure 15 could illustrate
how the Common Noise of the secondary side
diode be restrained. The secondary side
winding split to two separate windings NSEC1
and NSEC2 which have same turns and
approximate parasitic capacitor CSP1,and CSP2
but their ‘hot spot’ is opposite as the Point 9
and Point 10 in Figure 15, so the common
mode noise current produced at secondary side
windings can be counteracted each other.
The transformer structure could be simple if the
application does not need to pass the 3 wire
Conducted EMI or could use the Y cap. Figure
16 shows the schematic with the simple
transformer structure.
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
TYPICAL APPLICATION CIRCUITS
R7 20/1206
L1
EE16
L P=1.6mH
N P:NP_AU:NSEC1:N SEC2=127:18:4:4
1
10
1000uH/0.25A
R1
10K/0805
C3
1nF/630V/1206
R3
150K/1206
L
85VAC~265VAC
CR1
C2
10uF/400V
600V/0.5A
3.3uH/4A
Vo
9
NSEC1
C8
NSEC 2
470uF/10V
4
C1
4.7uF/400V
L2
D3 B540C/40V/5A
NP
3
FR1 10/1W
C7 1.2nF/100V
C9
470uF/10V
C10
1uF/10V
R8
2.2K
5V/1A
7
D1
FR107
6
NP_AU
AGND
N
1000V/1A
5
R2
T1
PGND
357/1206
CY1
AGND
NC
PGND
PGND
D2
S1ML/1000V/1A
C4
1uF/25V
U1
5
6
GND
CP
GND
FB
R4
R5
27K/1%
10/1206
4
3
2
GND
C11
22pF/50V
PGND
8
Drain
R6
13.3K/1%
1
VCC
C6
C5
MP020-5/SOIC8-7A
100nF/50V
22uF/50V
PGND
Figure 14: Typical Application, 5V/1A with Complicated Transformer Structure
Vin
Static point
1
NP
MP020-5
Drain
C SP2
3
5
Vcc
C SP1
N P_AU
4
7
Vout
Dynamic point
N SEC1 voltage
0V
+
9
D1
0V
Dynamic point
N SEC2 voltage
6
10
Static point
Figure 15: Secondary Side Windings Structure to Restrain the Common Mode Noise
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
R7 20/1206
L1
R1
T1
EE16
L P=1.6mH
NP:N P_AU:NS=127:18:8
1
10
1000 uH/0.25A
D3 B560C/60V/5A
Vo
10K/0805
C3
1nF/630V/1206
R3
150K/1206
NP
3
NS
C8
330uF/10V
L
4
FR1 10/1W
85VAC~265VAC
CR1
C7 1.2nF/100V
C1
4.7uF/400V
C2
10uF/400V
C10
R8
1uF/10V
2.2K
5V/1A
D1
FR107
1000 V/1A
6
NP_AU
AGND
N
600V/0.5A
C9
330uF/10V
5
R2
200/1206
PGND
CY1
AGND
2.2nF/250V
PGND
PGND
D2
U1
5
6
BAV21W
200V/0.2A
C4
1uF/25V
GND
CP
GND
FB
GND
R4
2.2/1206
4
R5
27K/1%
3
2
R6
13.3K/1%
PGND
8
Drain
VCC
1
C5
MP020-5GS/SOIC8-7A
100nF/50V
C6
22uF/50V
PGND
Figure 16: Typical Application, 5V/1A with Simple Transformer Structure
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
FLOW CHART
Y
Start
VCC<VCCL
Monitor VCC
N
N
Monitor V CC
V CC >VCCH
Y
Monitor Io
N
Monitor V FB
N
Y
CV
Operation
Io<Io_ref
V FB>6.35V
for 3.5us
V FB>-0.15V
for entire
cycle
N
Y
Y
CC
Operation
OVP
Operation
OCkP
Operation
Shut Off
Switching
Pulse
MP020-5 Rev. 1.05
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MP020-5 – OFFLINE, PRIMARY-SIDE REGULATOR WITH CC/CV CONTROL AND A 700V FET
PACKAGE INFORMATION
SOIC8-7A
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.050(1.27)
BSC
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH
,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) JEDEC REFERENCE IS MS-012.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal
responsibility for any said applications.
MP020-5 Rev. 1.05
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1/23/2014
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20