TI TPS55010RTET

TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
2.95V To 6V Input, 2W, Isolated DC/DC Converter with Integrated FETs
Check for Samples: TPS55010
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The TPS55010 is a transformer driver designed to
provide isolated power for isolated interfaces, such as
RS-485 and RS-232, from 3.3V or 5V input supply.
1
23
Isolated Fly-Buck™ Topology
Primary Side Feedback
100 kHz to 2000 kHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start
Adjustable Input Voltage UVLO
Open Drain Fault Output
Cycle-by-Cycle Current Limit
Thermal Shutdown Protection
3 mm x 3 mm 16 Pin QFN Package
The device uses fixed frequency current mode control
and half bridge power stage with primary side
feedback to regulate the output voltage for power
levels up to 2W. The switching frequency is
adjustable from 100 kHz to 2000 kHz so solution size,
efficiency and noise can be optimized. The switching
frequency is set with a resistor or is synchronized to
external clock using the RT/CLK pin. To minimize
inrush currents, a small capacitor can be connected
to the SS pin. The EN pin can be used as an enable
pin or to increase the default input UVLO voltage
from 2.6V.
APPLICATIONS
•
•
•
•
•
Noise Immunity in PLCs, Data Acquisition and
Measurement Equipment
Isolated RS-232 and RS-485 Communication
Channels
Powers Line Drivers, ISO Amplifiers, Sensors,
CAN Transceivers
Floating Supplies for IGBT Gate Drivers
Promotes Safety in Medical Equipment
With the same transformer the TPS55010 can
provide a solution for different input and output
voltage combinations by adjusting the primary side
voltage. Off the shelf transformers are available to
provide single positive, or dual positive and negative
output voltages.
The TPS55010 is available in a 3 mm x 3 mm 16 pin
QFN package with thermal pad.
Figure 1. SIMPLIFIED SCHEMATIC
VIN
BOOT
TPS55010
Cboot
T1
1:2.5
PH
Css
Rt
Figure 2. Efficiency vs Load Current
100
EN
FAULT
SS
VSENSE
RT/CLK
COMP
CO
RHS
RLS
GND
CC
+
VO
_
CPRI
90
5V
200mA
80
Efficiency (%)
3V
to
5.5 V
CIN
70
60
50
40
30
VOUT = 5V
FSW = 350kHz
20
10
0
0.00
VIN = 5V
0.05
0.10
0.15
0.20
Output Current (A)
0.25
0.30
G040
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Fly-Buck is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN CONFIGURATION
VIN
EN
FAULT
BOOT
RTE PACKAGE
(TOP VIEW)
16
15
14
13
VIN 1
VIN 2
5
6
7
8
RT/CLK
4
COMP
GND
VSENSE
3
GND
GND
Thermal
Pad
(17)
12
PH
11
PH
10
PH
9
SS
Table 1. PIN FUNCTIONS
Pin Name
Number
Description
VIN
1, 2, 16
Supplies the control circuitry and switches of the power converter.
GND
3, 4, 5
Power Ground. This pin should be electrically connected directly to the thermal pad under the IC.
VSENSE
6
Inverting node of the gm error amplifier.
COMP
7
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
RT/CLK
8
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when
using an external resistor to ground to set the switching frequency. If the pin is pulled above the
PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The
internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If
clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set
function.
SS
9
Slow-start. An external capacitor connected to this pin sets the output rise time.
PH
10, 11, 12
The source of the internal high side power MOSFET, and drain of the internal low side MOSFET.
BOOT
13
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below
the minimum required by the output device, the output is forced to switch off until the capacitor is
refreshed.
FAULT
14
An open drain output. Active low if the output voltage is low due to thermal shutdown, dropout,
overvoltage or EN shut down.
EN
15
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors.
THERMAL PAD
17
GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad
should be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
2
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
FAULT
EN
VIN
Shutdown
91%
Enable
Comparator
Logic
Thermal
Shutdown
UVLO
Shutdown
Shutdown
Logic
Enable
Threshold
108%
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
VSENSE
Boot
UVLO
PWM
Comparator
Current
Sense
BOOT
PWM
Latch
R
SS
Q
Logic
S
Shutdown
Logic
S
COMP
Slope
Compensation
PH
Current
Limit
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
RT/CLK
GND
THERMAL
PAD
ORDERING INFORMATION (1)
(1)
TJ
PACKAGE
PART NUMBER
-40°C to 150°C
3 x 3 mm QFN
TPS55010RTE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at ww.w.ti.com.
Copyright © 2011, Texas Instruments Incorporated
3
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS
www.ti.com
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
VIN
EN
-0.3
7
V
-0.3
3.6
V
PH + 7
V
BOOT
Voltage
VSENSE
-0.3
3
V
COMP
-0.3
3
V
FAULT
-0.3
7
V
SS
-0.3
3
V
RT/CLK
-0.3
6
V
7
V
7
V
BOOT-PH
PH
PH, 10ns Transient
Current
-0.6
10
V
EN
100
µA
RT/CLK
100
µA
COMP
100
uA
FAULT
10
mA
SS
100
µA
2
kV
Electrostatic Discharge (HBM)
(2)
QSS 009-105 (JESD22-A114A)
Electrostatic Discharge (CDM)
(2)
QSS 009-147 (JESD22-C101B.01)
-2
500
V
Operating Junction Temperature
-40
150
ºC
Storage Temperature
-65
150
ºC
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS55010
RTE (16 PINS)
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
55.5
θJB
Junction-to-board thermal resistance
24.9
ψJT
Junction-to-top characterization parameter
1.0
ψJB
Junction-to-board characterization parameter
24.9
θJCbot
Junction-to-case (bottom) thermal resistance
9.9
(1)
4
UNITS
60
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
TJ = –40°C TO 150°C, VIN = 2.95V TO 6V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
Operating input voltage
VIN
2.95
Shutdown current
EN = 0V, 25°C
Operating current
VSENSE = 0.9V, 25°C
TYP
MAX
UNIT
SUPPLY VOLTAGE
Internal undervoltage lockout
6
V
2
5
µA
360
575
µA
2.6
2.9
V
1.25
1.37
V
ENABLE
Enable threshold
Input current
rising
falling
1.15
1.18
Threshold - 50mV
-1.2
Threshold + 50mV
-4.6
Hysteresis
µA
µA
3.4
VOLTAGE REFERENCE
Reference
3V < VIN < 6V
0.804
0.829
0.854
V
MOSFET
High side switch resistance
BOOT- PH = 5 V
45
81
mΩ
Low side switch resistance
VIN = 5 V
45
81
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amp transconductance
-2 µA < I(COMP) < 2 µA
245
uMhos
Error amp dc gain
VSENSE = 0.8 V
500
V/V
3
MHz
Error amp source/sink
V(COMP) = 1V, 100 mV overdrive
±16
µA
COMP to Iph gm
Iph = 0.5 A
7.5
A/V
Minimum unity gain Bandwidth
CURRENT LIMIT
High side sourcing current limit
VIN = 3 V
2
2.75
A
Low Side Sinking Current Limit
VIN = 3 V
-3
-4.5
A
171
°C
12
°C
THERMAL SHUTDOWN
Thermal Shutdown
OT Hysteresis
RT/CLK
Switching frequency using RT mode
100
Switching Frequency
R(RT/CLK) = 195 kΩ
RT/CLK voltage
R(RT/CLK) = 195 kΩ
400
500
2000
kHz
600
kHz
0.5
RT/CLK high threshold
1.6
RT/CLK low threshold
0.4
Switching frequency using CLK mode
300
V
2.2
0.6
V
V
2000
kHz
Minimum CLK pulse width
75
ns
PLL lock in time
50
µs
RT/CLK falling edge to PH rising edge
delay
90
ns
130
ns
2.5
V
PH
Minimum On time
Measured at 10% to 10% of VIN
BOOT
Boot UVLO
Copyright © 2011, Texas Instruments Incorporated
5
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C TO 150°C, VIN = 2.95V TO 6V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Charge current
V(SS) = 0.4 V
0.5
SS to VSENSE matching
V(SS) = 0.4 V
SS to reference Crossover
98% reference
1.1
V
SS discharge current (overload)
VSENSE = 0 V
325
µA
SS discharge voltage
VSENSE = 0V
46
mV
SS discharge current (UVLO, EN,
thermal fault)
V(SS) = 0.5 V
1.2
mA
VSENSE falling
91
% VREF
VSENSE rising
108
% VREF
SS Slow Start
VIN UVLO to SS start time
µs
100
2.2
µA
4
35
mV
FAULT Pin
VSENSE threshold
Output high leakage
VSENSE = VREF, V(FAULT) = 5.5 V
Output low
I(FAULT) = 3 mA
Minimum VIN for valid output
V(FAULT) < 0.5 V at 100 µA
2
nA
0.3
V
1.6
V
Spacer
TYPICAL CHARACTERISTICS
SPACER
90
500
VIN = 5V
RT = 200kΩ
Oscillator Frequency (kHz)
On Resistance (mΩ)
80
70
60
50
40
30
High Side VIN = 5V
Low Side VIN = 5V
High Side VIN = 3.3V
Low Side VIN = 3.3V
20
10
0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
475
450
425
400
−50
150
Figure 3. HIGH SIDE AND LOW SIDE RDS(on)
vs TEMPERATURE
125
150
G002
VIN = 3.3V
VIN = 5V
−4.2
Current Limit Threshold (A)
Current Limit Threshold (A)
25
50
75
100
Junction Temperature (°C)
−4.0
VIN = 5V
VIN = 3.3V
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
−4.4
−4.6
−4.8
−5.0
−5.2
−5.4
−5.6
−5.8
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G003
Figure 5. HIGH SIDE CURRENT LIMIT (SOURCING) vs
JUNCTION TEMPERATURE
6
0
Figure 4. FREQUENCY vs TEMPERATURE
3.5
2.5
−50
−25
G001
−6.0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G004
Figure 6. LOW SIDE CURRENT LIMIT (SINKING) vs
JUNCTION TEMPERATURE
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
1.240
300
VIN = 5V
1.235
1.230
VENA− Enable (V)
Transconductance (µA)
250
200
150
100
1.225
1.220
Rising
Falling
1.215
1.210
1.205
1.200
1.195
50
1.190
0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
0
25
50
75
100
Junction Temperature (°C)
125
150
G006
Figure 8. EN PIN VOLTAGE vs TEMPERATURE
−0.1
−3.24
VIN = 5V
−0.2
VIN = 5V
−3.26
−0.3
ENA− Enable Hyst (µA)
ENA− Enable Current (µA)
−25
G005
Figure 7. ERROR AMPLIFIER TRANSCONDUCTANCE vs
TEMPERATURE
−0.4
−0.5
−0.6
−0.7
−0.8
−3.28
−3.30
−3.32
−3.34
−3.36
−3.38
−0.9
−1.0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
−3.40
−50
150
25
50
75
100
Junction Temperature (°C)
125
150
G008
2.76
VIN = 5V
2.74
2.72
−2.3
2.70
Input Voltage (V)
−2.2
−2.4
−2.5
−2.6
−2.7
2.66
2.62
2.60
2.58
2.56
0
25
50
75
100
Junction Temperature (°C)
125
150
G009
Figure 11. SS CHARGE CURRENT vs TEMPERATURE
Copyright © 2011, Texas Instruments Incorporated
VIN = 5V
2.64
−2.9
−25
Rising
Falling
2.68
−2.8
−3.0
−50
0
Figure 10. EN PIN HYSTERESIS CURRENT
vs TEMPERATURE
−2.0
−2.1
−25
G007
Figure 9. EN PIN PULLUP
vs TEMPERATURE (VEN = Threshold -50 mV)
SS Current (µA)
VIN = 5V
1.185
−50
150
2.54
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G010
Figure 12. INPUT START and STOP VOLTAGE vs
TEMPERATURE
7
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
2.5
400
EN = Open
VSENSE = 0.9V
2.0
380
Supply Current (µA)
Shutdown Current (µA)
EN = 0V
1.5
1.0
0.5
360
340
320
VIN = 5V
VIN = 3.3V
0.0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
VIN = 5V
VIN = 3.3V
300
−50
150
Figure 13. SHUTDOWN SUPPLY CURRENT vs
TEMPERATURE
0.831
0.830
0.829
0.828
0.827
0.826
G012
100
VIN = 5V
95
90
85
−25
0
25
50
75
100
Junction Temperature (°C)
125
80
−50
150
VSENSE Rising
VSENSE Falling
−25
0
G013
25
50
75
100
Junction Temperature (°C)
125
150
G014
Figure 15. VOLTAGE REFERENCE vs TEMPERATURE
Figure 16. FAULT THRESHOLD vs TEMPERATURE
160
36
VIN = 5V
VIN = 5V
SS to VSENSE Offset (mV)
140
On Resistance (Ω)
150
105
0.825
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G015
Figure 17. FAULT ON-RESISTANCE vs TEMPERATURE
8
125
110
0.832
0.824
−50
25
50
75
100
Junction Temperature (°C)
VIN = 5V
Fault Threshold (% VREF)
Voltage Reference (V)
0
Figure 14. VIN SUPPLY CURRENT vs TEMPERATURE
0.834
0.833
−25
G011
35
34
33
32
31
30
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G016
Figure 18. SS to VSENSE OFFSET vs TEMPERATURE
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
Detailed Description
The TPS55010 is a half bridge transformer driver designed to implement a high efficiency, low power isolated
supply. The primary side feedback implemented using two resistors and a primary side capacitor provides
excellent regulation over line and load compared to an open loop push pull converter.
The half bridge power stage consists of two integrated n-channel MOSFETs with 45 mΩ on resistance. The drive
voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The
switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase
lock loop (PLL) on the RT/CLK pin that is used to synchronize the high side power switch turn on to a falling
edge of an external system clock. The wide switching frequency of 100 kHz to 2000 kHz (300kHz to 2000kHz in
CLK mode) allows for efficiency, size optimization or noise avoidance when selecting the switching frequency.
The TPS55010 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS55010 is typically 360 µA when not switching and under no load. When the device
is disabled, the supply current is less than 5 µA. The slow start (SS) pin is used to minimize inrush currents
during start up.
Fixed Frequency PWM Control
The TPS55010 uses an adjustable fixed frequency, peak current mode control. The primary voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level. The TPS55010 adds a compensating ramp to the switch
current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases.
Half Bridge and Bootstrap Voltage
The TPS55010 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric and a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
Error Amplifier
The TPS55010 uses a transconductance error amplifier. The amplifier compares the VSENSE voltage to the
lower of the SS pin voltage or the internal 0.829 V voltage reference. The transconductance of the error amplifier
is 245 µA/V. The frequency compensation components are placed between the COMP pin and ground.
Voltage Reference
The voltage reference system produces a precise ±3.0% voltage reference over temperature by scaling the
output of a temperature-stable band gap circuit. The band gap and scaling circuits produce 0.829 V at the
non-inverting input of the error amplifier.
Adjusting the Output Voltage
The primary side voltage is set with a resistor divider from the primary side capacitor to the VSENSE pin. It is
recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the RLS resistor and use
Equation 1 to calculate RHS. The output voltage is a function of the primary voltage, transformer turns ratio and
forward voltage of the diode.
æV
- 0.829V ö÷
÷÷
RHS = RLS × ççç PRI
çè
0.829V
ø÷
(1)
spacer
Copyright © 2011, Texas Instruments Incorporated
9
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
N
VOUT = VPRI × SEC - Vfd
NPRI
(2)
spacer
VIN
Npri:Nsec
PH
VFD
VO
CO
TPS55010
VSENSE
-
RHS
+
0.829V
VPRI
RLS
GND
CPRI
Figure 19. Setting the Output Voltage
Enable and Adjusting Undervoltage Lockout
The TPS55010 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 20 to adjust the input voltage UVLO by using
two external resistors. The EN pin has an internal pull-up current source of 1.2 µA that provides the default
condition of the TPS55010 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an
additional 3.4 µA of hysteresis is added. When the EN pin is pulled below 1.18 V, the hysteresis current is
removed.
TPS55010
VIN
I1
Ihys
RUVLO1
EN
RUVLO2
VENA
Figure 20. Adjustable Under Voltage Lock Out
æ
ö
çç VENfalling ÷÷
÷÷ - V
VSTART çç
STOP
÷÷
çç V
è ENrising ø÷
RUVLO1 =
æ V
ö
çç
ENfalling ÷÷
I1 × ç1÷÷ + IHYS
çç V
÷
ENrising ø÷
è
(3)
spacer
10
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
RUVLO1 × VENfalling
VSTOP - VENfalling + RUVLO1 × (I1 + IHYS )
RUVLO2 =
(4)
Adjusting Slow Start Time
A capacitor on the SS pin to ground implements a slow start time to minimize inrush current during startup. The
TPS55010 regulates to the lower of the SS pin and the internal reference voltage. The TPS55010 has an internal
pull-up current source of 2.2 µA which charges the external slow start capacitor. Equation 5 calculates the
required slow start capacitor value where TSS is the desired slow start time in ms, Iss is the internal slow start
charging current of 2.2 µA, and VREF is the internal voltage reference of 0.829 V.
If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.18 V, or a thermal shutdown
event occurs, the TPS55010 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or
a thermal shutdown is exited, then SS is discharged to below 40 mV before reinitiating a powering up sequence.
The VSENSE voltage will follow the SS pin voltage with a 35 mV offset up to 85% of the internal voltage
reference. When the SS voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS voltage to the internal voltage reference. If no slow start time
is needed, the SS pin can be left open. The slow start capacitor should be less than 0.47 µF.
CSS (nF) =
TSS (ms) × ISS (uA)
VREF (V)
(5)
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS55010 is adjustable over a wide range from 100 kHz to 2000 kHz by placing
a maximum of 1070 kΩ and minimum of 42.2 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use Equation 6.
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum
controllable on time is typically 130 ns.
RT (kW) =
156000
fsw (kHz)1.0793
(6)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 21. The square wave amplitude must transition lower than 0.4V and higher than 2.2V on the RT/CLK pin
and have a high time greater than 75 ns. The synchronization frequency range is 300 kHz to 2000 kHz. The
rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device has the default frequency
set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 21 through another resistor (e.g 50
Ω) to ground for clock signal that are not Hi-Z or tri-state during the off state. The RT resistor value should set
the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization
signal through a 10 pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK
threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage source is
removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the external CLK frequency within 50 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency.
Copyright © 2011, Texas Instruments Incorporated
11
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
TPS55010
TPS55010
RT/CLK
RT/CLK
PLL
PLL
Clock
Source
RT
Hi-Z
Clock
Source
RT
Figure 21. Synchronizing to a System Clock
Overcurrent Protection
The TPS55010 implements a cycle by cycle current limit. During each switching cycle the high side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
Reverse Overcurrent Protection
The TPS55010 implements low side current protection by detecting the voltage across the low side MOSFET.
When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if
the reverse current is more than 4.5 A
FAULT Pin
The Fault pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage is below
91% or rising above 108% of the nominal internal reference voltage. It is recommended to use a pull-up resistor
between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or less. The Fault pin is in a valid state
once the VIN input voltage is greater than 1.6 V. The FAULT pin is pulled low, if the input UVLO or thermal
shutdown is asserted, or the EN pin is pulled low.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 171°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 159°C, the device reinitiates the power up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 12°C.
OPERATION OF THE Fly-Buck™ CONVERTER
Figure 22 shows a simplified schematic and the two primary operational states of the Fly-Buck converter. The
power supply is a variation of a Flyback converter and consists of a half bridge power stage SHS and SLS,
transformer, primary side capacitor, diode and output capacitor. The output voltage is regulated indirectly by
using the primary side capacitor voltage, VPRI, as feedback. The Fly-Buck is a portmanteau of flyback and buck
since the transformer is connected as a flyback converter and the input to output voltage relationship is similar to
a buck derived converter, assuming the converter is operating in steady state and the transformer has negligible
leakage inductance.
The CPRI and LPRI are charged by the input voltage source VIN during the time the high side switch SHS is on.
During this time, diode D1 is reversed biased and the load current is supplied by output capacitor CO.
12
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
During the off time of SHS, SLS conducts and the voltage on CPRI continues to increase during a portion of the SLS
conduction time. The voltage increase is due to the energy transfer from LPRI to CPRI. For the remaining portion of
the SLS conduction time, the CPRI voltage decreases because of current in LPRI reverses; see the ILPRI and VPRI
waveforms in Figure 23. By neglecting the diode voltage drop, conduction dead time and leakage inductance, the
input to output voltage conversion ratio can be derived as shown in Equation 7 from the flux balance in LPRI. It
can be seen in Equation 7 that the input to output relationship is the same as a buck-derived converter with
transformer isolation. The dc voltage VPRI on the primary side capacitor in Equation 8 has the same linear
relationship to the input voltage as a buck converter.
SHS
D1
T1
D1
T1
CIN
SLS
NPRI
NSEC
CO
_
+
SHS
VIN C
IN
NPRI
NSEC
CO
+
VPRI
VO
_
SHS
+
VPRI
_
CPRI
D x Ts
_
SLS
+
VO
D1
T1
CPRI
CIN SLS
NPRI
NSEC
_
+
VO
_
+
VPRI
CO
CPRI
(1 - D) x Ts
Figure 22.
The small signal model for the Fly-Buck is derived by changing the transformer to the inductor equivalent and
reflecting the output filter to the primary side for the circuit shown in Figure 22. Assuming negligible leakage
inductance and equivalent series resistance for the capacitors, the VPRI transfer function is similar to the current
mode control buck power stage transfer function with the exception that the CO and load are in parallel with the
CPRI only for the 1-D time. Averaging the secondary side components, an approximate transfer function is shown
in Equation 9 and pole location in Equation 10. RO is the secondary side load resistance and the RLM is the dc
resistance of the primary. Ri is the inverse of the Comp to PH gm.
VO
VIN
=
NSEC
×D
NPRI
(7)
spacer
VPRI
=D
VIN
(8)
Spacer
Copyright © 2011, Texas Instruments Incorporated
13
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
2
æ
æN
ö÷ ÷ö
çç RO
ç
PRI
÷÷ ÷÷÷
RLM + çç
× çç
ççè (1- D) èç NSEC ø÷÷ ÷÷ø
Vˆ PRI
»
æ
Vˆ C
s
÷÷ö
Ri × ççç1 +
÷
2 × p x fPOLE ÷÷ø
èç
(9)
Spacer
fPOLE =
1
2
2
æ
æN
ö ÷ö æç
æN
ö
÷ö
ç RO
÷
÷
÷
ç
÷
ç
SEC
ç
PRI
ç
2 × p ×çç
× çç
÷÷ ÷÷ × ç(1 - D) × CO × çç
÷÷ + CPRI ÷÷÷
çè NPRI ÷÷ø
çèç(1 - D) çè NSEC ÷÷ø ÷÷ø ççè
÷ø
(10)
SHS
SLS
ILpri_pospk
ILpri
Im_valley
ILpri_negpk
Vpri
ID1_pk
ID1
DTs
(1-D) x Ts
Figure 23. Simplified Voltage and Current Waveforms
14
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
Overview
The following design example illustrates how to determine the components for a single output isolated power
supply. TI offers an EVM (TPS55010EVM-009) with user guide (SLVU459) and excel calculator tool (SLVC363)
to expedite the design process. The support material is available on the TPS55010 product folder at www.ti.com.
INPUT
VIN
BOOT
+5V
CIN
TPS55010
CBOOT
T1
1:2.5
PH
EN
CO
FAULT
5V
_
VSENSE
SS
RT/CLK
COMP
CSS
+
RHS
CPRI
RLS
GND
CY
Rt
CC
Figure 24. 5V to 5V ISOLATED POWER SUPPLY Schematic
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
Input Voltage
5V nominal (4.5V to 5.5V)
Output Voltage
5V
Output Voltage Ripple
<0.5%
Output Current
200mA
Start Voltage
4.5V
Stop Voltage
4V
PRIMARY SIDE VOLTAGE
The output voltage is a function of the primary voltage, transformer turns ratio and the diode voltage. The primary
voltage is a function of the duty cycle and input voltage, and is similar to a step down (buck) regulator as shown
in Equation 11. The primary side voltage must be lower than the minimum operating input voltage by 500 mV to
avoid maximum duty cycle problems and allow sufficient time for energy transfer during the low side power
switch on time. Typically, a primary side voltage that is 50% of the input voltage is ideal, but 20% to 80% is
acceptable. Using the design constraints, the primary side voltage could be from 3.6 V to 1.1 V. A 2.2 V primary
side voltage is selected, and the duty cycle is approximately 45%.
D=
VPRI
VIN
Copyright © 2011, Texas Instruments Incorporated
(11)
15
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
TURNS RATIO
The transformer turns ratio is calculated using the desired output voltage, diode voltage and the primary voltage.
Assuming a diode voltage of 0.5 V, VOUT of 5 V, VPRI of 2.2 V yields a NPRI:NSEC turns ratio of 1:2.5.
NSEC
=
NPRI
VOUT + VFD
VPRI
(12)
VOLTAGE FEEDBACK
Selecting 61.9 kΩ for the RLS, RHS is calculated to be 102.4 kΩ using Equation 13. Choose 100 kΩ as the
nearest standard value.
It may be necessary to adjust the feedback resistors to optimize the output voltage over the full load range.
Usually checking and setting the output voltage to the nominal voltage at 50% load, yields the best results.
æV
- 0.829V ö÷
÷÷
RHS = RLS × ççç PRI
çè
0.829V
ø÷
(13)
SELECTING THE SWITCHING FREQUENCY and PRIMARY INDUCTANCE
The selection of switching frequency is usually a trade-off between efficiency and component size. However,
when isolation is a requirement, switching frequency is not the key variable in determining solution size. Low
switching frequency operation improves efficiency by reducing gate drive losses and MOSFET and diode
switching losses. However, a lower switching frequency operation requires a larger primary inductance which will
have more windings and higher dc resistance.
The optimal primary inductance should be selected between two inductance values, LOMAX and LOMIN. The
primary inductance should be less than LOMAX to maintain good efficiency and greater than Lomin to avoid the
peak switch current from exceeding the high side power switch current limit. Once the primary inductance is
selected, check against the low side current limit using the Equation 17 and the high side current limit. For this
design example, the switching frequency is selected to be 350 kHz. Using Equation 6, the resistor value is 280
kΩ. LOMAX and Lomin are calculated to be 3.52 µH and 1.17 µH respectively assuming a current limit of 2 A.
Selecting a primary inductance of the 2.5 µH, the positive and negative peak current are calculated as 1.204 A
and -1.99 A in the primary which do not exceed the current limits of the power switch. The rms currents can be
calculated and used to determine the power dissipation in the device.
The magnetizing ripple current is caculated as 1.41 A using Equation 18. The highside FET and lowside FET rms
currents are calculated as 0.43 A and 0.61 A, respectively using Equation 19 and Equation 20. The sum of these
currents, i.e. 1.04 A is the primary side rms current for the magnetics.
LOMAX =
VIN × D × (1 - D)
N
2 × SEC × IOUT × fsw
NPRI
(14)
Spacer
LOMIN =
VIN × D × (1 - D)
æ
ö÷
N
2 × fsw × çççIHSCL - IOUT × SEC ÷÷
NPRI ø÷÷
çè
(15)
Spacer
N
V × D × (1 - D)
ILpri_pospk » IOUT SEC + IN
N
2 × fsw × LOPRI
PRI
(16)
Spacer
16
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
N
æ1 + D ö÷ VIN × D × (1-D)
ILpri _ negpk » - IOUT SEC × çç
çè 1 - D ø÷÷ 2 × f
NPRI
× LOPRI
sw
(17)
Spacer
Im_ ripple =
VIN × D × (1 - D)
f
sw
× LOPRI
(18)
Spacer
æ
ç
ç
Ihs _ rms » ççD ×
ççè
1
2
ö÷2
æ
NSEC ö÷
D
÷
ççI
2
÷ +
× Im_ ripple ÷÷
ç OUT N
÷÷
÷÷
12
÷
èç
ø
PRI
ø
(19)
Spacer
1
2
æ
ö2
æ
Im_ripple x IOUT x NSEC
NSEC ö÷
1-D
çç 3 × D-1
2÷
ç
÷÷ +
Ils _ rms » ç
× çI
x
+
× Im_ripple ÷÷÷
çç 3 × (1-D) çè OUT
÷
÷ø
N
3
x
N
12
PRI ø
PRI
è
(20)
Spacer
ILrms » IHS _ rms+ ILS _ rms
(21)
PRIMARY SIDE CAPACITOR
The ΔVPRI voltage should be less than 10% of VPRI. The rated RMS current of CPRI should be greater than
Equation 22. It is desirable to have a larger primary capacitance to minimize ripple but this will slow the transient
response. For this design example, assuming the ΔVPRI is 0.22 V, the primary side capacitance is 4.74 µF and
the rms current is 1.04 A. A 4.7 µF/10V X5R ceramic capacitor is used.
Spacer
ICPRI_rms = ILrms
(22)
Spacer
D + (1 - D) x
ICPRI_ch » ILCPRI _pospk x
ILPRI _pospk
ILPRI _pospk - ILPRI _negpk
3
(23)
Spacer
tCPRI »
D
fSW
+
ILPRI _pospk
(1 - D)
x
fSW
ILPRI _pospk - ILPRI _negpk
(24)
Spacer
CPRI =
ICPRI_ch × tCPRI
DVPRI
Copyright © 2011, Texas Instruments Incorporated
(25)
17
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
SECONDARY SIDE DIODE
The diode should be selected to handle the voltage stress and rms current calculated in Equation 26 and
Equation 27. Typically, a low duty cycle or high turns ratio design will have a larger voltage stress on the diode.
At the maximum input voltage of 5.5V, the Vdiode_max voltage is calculated at 13.3 V. The rms current is
calculated as 0.31 A. The diode peak current is 0.71 A using Equation 28 and the power dissipated in the diode
is 0.1 W. The B120 diode is used which is rated for 20 V and 1 A.
N
Vdiode _ max = (VIN - VPRI ) × SEC + VOUT
NPRI
(26)
Spacer
1
æ
ö÷2
1
÷÷
Idiode _ rms = 2 × IOUT × ççç
çè 3 × (1 - D)ø÷
(27)
Spacer
I
Idiode _ peak = 2 × OUT
1-D
(28)
Spacer
Pdiode = Vfd × IOUT
(29)
SECONDARY SIDE CAPACITOR
The ΔVCO voltage should be 0.25% to 1% of VCO voltage. The converter transfers energy each switching period
to the secondary, since the converter has primary side feedback, at light or no load conditions the output voltage
may rise above the desired output. If the application will experience a no load condition, attention to the capacitor
voltage ratings should be considered. Adding a ballast load, zener diode or linear regulator can help prevent the
overvoltage at light or no load.
The output capacitance is calculated to be 10.1 µF using Equation 30 and the rms current is 0.24 A.
Two 10 µF/10V X5R ceramic capactors are used. The effective capacitance is lower than the 20 µF, because of
dc voltage bias.
CO =
IOUT × D
fSW × D VCO
(30)
Spacer
ICO _ rms = Idiode _ rms2 - IOUT 2
(31)
INPUT CAPACITOR
The ΔVCIN voltage should be 0.25% to 1% of VIN. The TPS55010 requires a high quality ceramic, type X5R or
X7R, input decoupling capacitor of at least 2.2 µF of effective capacitance or larger coupled to VIN and GND
pins and in some applications additional bulk capacitance. The effective capacitance includes any DC bias
effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the TPS55010.
The input ripple current can be calculated using Equation 33. The value of a ceramic capacitor varies significantly
overtemperature and the amount of DC bias applied to the capacitor. The capacitance variations due to
temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R
ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to
volume ratio and are fairly stable overtemperature. The output capacitor must also be selected with the DC bias
taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases.
In applications with significant unload transients, the bulk input capacitance must be sized to include energy
transfer from the primary side capacitor to the input capacitor.
18
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
The input capacitance is calculated 12.6 µF using Equation 32 and the rms current is 0.46 A. A 47 µF/10V X5R
ceramic capacitor is used on the input. A 0.1 µF ceramic capacitor is placed as close to the VIN and GND pins
as possible for a good bias supply.
CIN =
N
IOUT SEC × D
NPRI
fSW × DVCIN
(32)
Spacer
ICin _ rms = ILpri _ pospk ×
D
3
(33)
Y – Capacitor
The Y-capacitor should be used between the primary and secondary to attenuate common mode (CM) noise in
noise sensitive applications. When connecting the primary and secondary grounds with a large loop area, the
primary side switching noise can be injected via the interwinding capacitance of the isolation transformer,
creating common mode noise in the secondary. A Y-capacitor can be used to provide a local return path for
these currents with a small capacitor connected between the secondary ground and the primary ground. The
voltage rating of the Y-capacitor should be equivalent to the transformer insulation voltage. If the converter is
used for safety isolation there is an upper limit on the amount of capacitance. The inter-winding capacitances of
the transformer and maximum leakage current (e.g. UL60950 Class I equipment leakage current <3.5 mA)
allowed by the safety standard will set the maximum value. It is not recommended to use the Y-capacitor in
applications which experience large voltage transients such as a floating gate drive supply in a power inverter.
SLOW START CAPACITOR
To minimize overshoot during power up or recovery from an overload condition a slow start capacitor is used. A
35-ms slow start is desired and using Equation 5 a 0.1 µF capacitor is calculated.
BOOTSTRAP CAPACITOR SELECTION
A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
UVLO Resistors
Using the start and stop voltages of 4.5 V and 4 V, respectively, the uvlo resistors 71.5 kΩ and 26.7 kΩ are
calculated using Equation 3 and Equation 4.
COMPENSATION
There are several methods used to compensate DC/DC regulators. The method presented here ignores the
effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the
actual cross over frequency should be lower than the cross over frequency used in the calculations. This method
assumes the cross over frequency is between the modulator pole and 20 times greater the modulator pole. When
choosing a crossover frequency with the single compensation capacitor method (i.e. type 1), use the lower end of
the recommended range when developing a supply if the primary capacitor ripple voltage is <1%. Type 2 or 3
compensation should be considered if a low primary ripple design is preferred. To get started, the modulator pole
frequency, fPOLE, determined from Equation 10 should be used to select the crossover frequency, fCO. In this
example, 5 kHz is selected as the crossover frequency. The next step is to determine the compensation gain,
ACOMP, at the crossover frequency to compensate the loop. Equation 35 uses the dc gain of the power stage,
modulator pole, and crossover frequency to estimate the gain. Ri is the current sense gain which is the inverse of
the Comp to IPH transconductance, which is 7.5 A/V. 10.1 dB is calculated for ACOMP. The compensation pole
frequency fCOMP_POLE can be calculated using Equation 36. AOL in Equation 36 is the open loop gain of the error
amplifier and is 500 V/V. fCOMP_POLE is calculated as 8.27 Hz. Using Equation 37, CCOMP is calculated to be 0.01
μF.
Copyright © 2011, Texas Instruments Incorporated
19
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
wPOLE
2×p
< fCO < 20 ×
www.ti.com
wPOLE
2×p
(34)
Spacer
æ
RO ÷ö
çç R
÷÷
+
æ 2×p×f
ö
ççç LM (1 - D)÷÷
CO ÷÷
÷÷ - 20 × logççç
A COMP = 20 × logç
÷÷
ç
÷
Ri
èç 2 × p × fPOLE ÷ø
÷÷÷
ççç
÷ø
çè
(35)
Spacer
VPRI
fCOMP_POLE =
10
Acomp
20
× fCO
× A OL × VREF
(36)
Spacer
1
CCOMP =
2×p×
A OL
gmea
-
× fCOMP_POLE
gmea
2 × p × BW
(37)
VENDORS
At the time of the product release, there are two catalog transformers available for the TPS55010. The
transformers are available at Digikey or directly through Wurth Elektronics Midcom.
Table 2.
20
Part Number
Specifications
Vendor
750311880
2.5 µH, 1:2.5 Turns Ratio, Basic Insulation, 2500 Vrms
750311780
2.0 µH, 1:8:8 Turns Ratio, Basic Insulation, 2000 Vrms
Wurth Elektronics Midcom
www.we-online.com/midcom
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
HOW TO SPECIFY A Fly-Buck TRANSFORMER
If a catalog or standard off the shelf transformer is not available, use this section to determine the transformer
specifications to supply a vendor. Selecting the magnetizing inductance is similar to the conventional flyback
converter operating in continuous conduction mode. One distinction is the voltage across the transformer during
the on time is different. The voltage is the difference in the input voltage and voltage across the primary
capacitor. For a conventional flyback, only the input voltage is across the primary. Another distinction is the peak
current in the primary is the negative current peak.
Table 3. Transformer Design Form
Input Voltage Range (V)
Output Voltage (V)
Output Current (A)
Operating Mode
Continuous Conduction Mode
Primary Voltage (V)
Use Equation 11 and Equation 12
Duty Cycle Range (%)
Use Equation 11
Turns Ratio (NPRI:NSEC)
Use Equation 12
Switching Frequency (Hz)
Use Equation 14 to Equation 17
Primary Inductance (H)
Use Equation 14 to Equation 17
Peak Current Positive (A)
Use Equation 14 to Equation 17
Peak Current Negative (A)
Use Equation 14 to Equation 17
Insulation Requirements
Functional, Basic, Reinforced
Regulatory Agencies/Specification
UL, IEC
Dielectric Withstand Voltage
AC
DC
Working Voltage
AC
DC
D1
T1
SHS
VIN C
IN
NPRI
NSEC
CO
+
VO
_
SLS
+
VPRI
_
CPRI
Figure 25. Topology
Copyright © 2011, Texas Instruments Incorporated
21
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
CHARACTERISTICS
6
100
90
5.75
80
5.5
Output Voltage (V)
Efficiency (%)
70
60
50
40
VOUT = 5V
FSW = 350kHz
30
10
0
0.00
0.05
0.10
0.15
0.20
Output Current (A)
0.25
5
4.75
4.5
VIN = 4.5V
VIN = 4.75V
VIN = 5V
VIN = 5.25V
VIN = 5.5V
20
5.25
VIN = 4.5V
VIN = 4.75V
VIN = 5V
VIN = 5.25V
VIN = 5.5V
4.25
0.30
4
0
0.05
0.1
0.15
0.2
Output Current (A)
0.25
0.3
G040
Figure 26. Efficiency vs Output Current
G025
Figure 27. Output Voltage vs Output Current
5.250
IOUT =100 mA
VIN = 5 V / div
Output Voltage (V)
5.125
VOUT = 2 V / div
5.000
VPRI = 2 V / div
4.875
ILOAD = 200 mA / div
4.750
4.50
Time = 10 msec / div
4.75
5.00
Input Voltage (V)
5.25
5.50
G026
Figure 28. Output Voltage vs Input Voltage
22
Figure 29. Power Up with Input Voltage
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
VIN = 5 V / div
EN = 5 V / div
VOUT = 2 V / div
VOUT = 2 V / div
VPRI = 2 V / div
VPRI = 2 V / div
ILOAD = 200 mA / div
ILOAD = 200 mA / div
Time = 20 msec / div
Time = 10 msec / div
Figure 30. Power Up with Enable Pin
Figure 31. Power Down with Input Voltage
VIN = 5 V / div
EN = 5 V / div
ENA = 2 V / div
VOUT = 2 V / div
VOUT = 2 V / div
VPRI = 2 V / div
IIN = 200 mA / div
ILOAD = 200 mA / div
Time = 2 msec / div
Time = 20 ms / div
Figure 32. Power Down with Enable Pin
Figure 33. Inrush Current During Power Up
VPRI = 500 mV / div (ac coupled)
VIN = 50 mV / div (ac coupled)
VIN = 5 V
VIN = 5 V
IOUT = 200 mA
RT/CLK = 5 V / div
PH = 5 V / div
IOUT = 200 mA
RT/CLK = 5 V / div
PH = 5 V / div
VOUT = 50 mV / div (ac coupled)
VOUT = 50 mV / div (ac coupled)
Time = 1 ms / div
Figure 34. Output Ripple Voltage
Copyright © 2011, Texas Instruments Incorporated
Time = 1 ms / div
Figure 35. Synchronize to External Clock
23
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
VOUT = 200 mV / div (ac coupled)
VOUT = 200 mV / div (ac coupled)
ILOAD = 100 mA / div
ILOAD = 100 mA / div
VIN = 5 V
VIN = 5 V
Time = 100 ms / div
Time = 100 ms / div
Figure 36. Load Step Response
Figure 37. Load Step Response
VIN = 2 V / div
VIN = 2 V / div
VOUT = 50 mV / div (ac coupled)
VOUT = 50 mV / div (ac coupled)
ILOAD = 100 mA / div
ILOAD = 100 mA / div
IOUT = 200 mA
IOUT = 200 mA
Time = 40 ms / div
Time = 40 ms / div
Figure 38. Line Step Response
Figure 39. Line Step Response
180
60
VIN = 5 V
IOUT = 200 mA
VIN = 5 V
IOUT = 200 mA
PH = 5 V / div
50
135
40
90
30
45
20
0
10
−45
0
−90
Phase (°)
Gain (dB)
VOUT = 50 mV / div (ac coupled)
ILSEC = 500 mA / div
ILPRI = 1 A / div
−135
−10
Gain
Phase
−20
Time = 1 ms / div
1
10
100
1k
10k
Frequency (Hz)
100k
−180
1M
G045
Figure 40. Steady State Waveforms
24
Figure 41. Frequency Response
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
Table 4. Reference Design for Common Applications
5V to 5V/0.2A
3.3V to 5V/0.2A
5V to 3.3V/0.3A
3.3V to 3.3V/0.3A
CIN
47 µF X5R 6.3V
100 µF X5R 6.3V
47 µF X5R 6.3V
100 µF X5R 6.3V
COUT
2 x 10 µF X5R 10V
47 µF X5R 6.3V
22 µF X5R 6.3V
47 µF X5R 6.3V
CPRI
4.7 µF X5R 10V
22 µF X5R 6.3V
10 µF X5R 6.3V
10 µF X5R 6.3V
CBOOT
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
CSS
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
CC
0.01 µF X5R 10V
0.022 µF X5R 10V
0.01 µF X5R 10V
0.01 µF X5R 10V
RHS
16.5k
16.5k
8.25k
8.25k
RLS
10k
10k
10k
10k
RT
280k
511k
332k
511k
T1
750311880
750311880
750311880
750311880
Wurth Electronics Midcom Wurth Electronics Midcom Wurth Electronics Midcom Wurth Electronics Midcom
D1
B120
Copyright © 2011, Texas Instruments Incorporated
B120
B120
B120
25
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
POWER DISSIPATION
BOOT
INPUT
VIN
+5V
CBOOT
PH
TPS55010
CIN
EN
NPRI
FAULT
Rt
+
COpos
Nsec1
VOpos
COneg
Nsec2
+
_
VOneg
_
VSENSE
SS
RT/CLK
GND
COMP
CSS
T1 Dpos
1:8:8
RHS
Dneg
CPRI
RLS
CY
CC
Figure 42. 5V to 15V/-15V Isolated Power Supply
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
Table 5.
Input Voltage
5V nominal (4.5V to 5.5V)
Positive Output Voltage, Vopos
+15V
Negative Output Voltage, Voneg
-15V
Output Voltage Ripple
<0.5%
Output Current Iopos, Ioneg
40mA
Start Voltage
4.5V
Stop Voltage
4V
PRIMARY SIDE VOLTAGE FOR DUAL OUTPUT
Similar to the single output design, the dual output voltages are a function of the primary voltage, transformer
turns ratio and the diode voltages. Using the same design constraints as the single, the primary side voltage
could be from 3.6 V to 1.1 V. A 1.93 V primary side voltage is selected, and the duty cycle is approximately
38.5%.
D=
VPRI
VIN
26
(38)
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
Turns Ratio
The transformer turns ratio is calculated using the desired output voltages, diode voltages and the primary
voltage. Assuming diode voltages of 0.5 V, VOpos of 15 V, VOneg of -15V and a VPRI of 1.93 V yields a NPRI x
NSEC1 x NSEC2 turns ratio of 1:8:8. Since the TPS55010 is flexible on the adjusting the primary side, a couple
iterations of selecting turns ratio may help find a solution that is good for multiple applications with the same
transformer.
NSEC1 + NSEC2
V
- VONEG
= OPOS
NPRI
VPRI
+
2 x VFD
(39)
VOLTAGE FEEDBACK
Selecting 10 kΩ for the RLS , RHS is calculated to be 13.28 kΩ using Equation 40. Choose 13.7 kΩ as the nearest
standard value.
æV
- 0.829V ö÷
÷÷
RHS = RLS × ççç PRI
çè
0.829V
ø÷
(40)
SELECTING THE SWITCHING FREQUENCY and PRIMARY INDUCTANCE
For this design example, the switching frequency is selected to be 400 kHz. Using Equation 6, the timing resistor
value is 243 kΩ. LOmax and LOmin are calculated to be 2.31 µH and 1.09 µH respectively assuming a current
limit of 2 A. Selecting a primary inductance of the 2 µH, the positive and negative peak current are calculated as
1.38 A and -2.19 A in the primary which do not exceed the current limits of the power switch. The rms currents
can be calculated and used to determine the power dissipation in the device. The magnetizing ripple current is
calculated as 1.48 A using Equation 46.
The highside FET and lowside FET rms currents are calculated as 0.478 A and 0.681 A, respectively using
Equation 47 and Equation 48. The sum of these currents, i.e. 1.16 A is the primary side rms current for the
magnetics.
æ
N
N
IOPN = ççIOPOS SEC1 + IONEG SEC2
çè
NPRI
NPRI
÷÷ö
÷÷
ø
(41)
Spacer
LOMAX =
VIN × D × (1 - D)
2 × IOPN× fSW
(42)
Spacer
LOMIN =
VIN × D × (1 - D)
2 × fSW × (IHSCL - IOPN )
(43)
Spacer
V × D × (1 - D)
ILpri_pospk » IOPN + IN
2 × fSW × LOPRI
(44)
Spacer
æ1 + D ö÷ VIN × D × (1 - D)
ILpri_negpk » -IOPN x çç
çè 1 - D ø÷÷ 2 × f
× LOPRI
SW
(45)
Spacer
Copyright © 2011, Texas Instruments Incorporated
27
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
Im_ ripple =
www.ti.com
VIN × D × (1 - D)
f
sw
× LOPRI
(46)
Spacer
1
æ
ö2
D
IHS _ rms » ççD × IOPN2 +
× Im_ripple2 ÷÷÷
çè
ø
12
(47)
Spacer
1
æ 3×D-1
ö÷2
Im_ripple
1-D
ILS _ rms » ççç
× IOPN2 +
× IOPN +
× Im_ripple2 ÷÷
÷ø
çè 3 × (1 - D)
3
12
(48)
PRIMARY SIDE CAPACITOR
The ΔVPRI voltage should be less than 10% of VPRI. The rated RMS current of CPRI should be greater than
Equation 49. It is desirable to have a larger primary capacitance to minimize ripple but this will slow the transient
response. For this design example, the charging current and time need to be calculated using Equation 50 and
Equation 51. The ICPRI_ch is 0.63 A and the tCPRI is 1.56 µs. Assuming the ΔVPRI is 0.193 V, the primary side
capacitance is 5.09 µF using Equation 49. The rms current is 1.16 A from Equation 49. A 10 µF/25 V X5R
ceramic capacitor is used.
Spacer
ICPRI_rms » ILS_rms + IHS_rms
(49)
Spacer
D + (1 - D) x
ICPRI_ ch » ILpri_pospk x
ILpri_pospk
ILpri_pospk - ILpri_negpk
3
(50)
Spacer
tCPRI »
D
fSW
+
(1 - D)
ILpri_pospk
x
fSW
ILpri_pospk - ILpri_negpk
(51)
Spacer
CPRI
ICPRI_ch × tCPRI )
(
=
DVPRI
(52)
SECONDARY SIDE DIODE
The diodes should be selected to handle the voltage stresses and rms currents calculated in Equation 53 and
Equation 55. Typically, a low duty cycle or high turns ratio design will have a larger voltage stress on the diode
At the maximum input voltage of 5.5 V, the Vdiode_max voltage is calculated at 43.56 V. The rms current is
calculated as 0.059 A. The diode peak current is 0.130 A using Equation 54 and the power dissipated in the
diode is 0.02 W. The B1100 diode will be used which is rated for 100 V and 1 A.
Spacer
Vdiode_max = (VIN_max - VPRI ) x
28
NSEC1
NPRI
+ VOPOS = (VIN_max - VPRI ) x
NSEC2
NPRI
+ VONEG
(53)
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
I
I
Idiode_peak = 2 × OPOS = 2 × ONEG
1-D
1-D
(54)
Spacer
1
2
æ
1
÷÷ö = 2 x I
Idiode _ rms = 2 x IOPOS x çç
ONEG
çè 3 x (1 - D) ÷ø
1
æ
ö÷2
1
xç
÷
çç
è 3 x (1 - D) ø÷
(55)
Spacer
Pdiode = VFD × IOPOS = VFD × IONEG
(56)
SECONDARY SIDE CAPACITOR
The ΔVCOPOS and ΔVCONEG voltage should be 0.25% to 1% of the respective nominal voltage. The converter
transfers energy each switching period to the secondary, since the converter has primary side feedback, at light
or no load conditions the output voltage may rise above the desired output. If the application will experience a no
load condition, attention to the capacitor voltage ratings should be considered. Adding a ballast load, zener diode
or linear regulator can help prevent the overvoltage at light or no load.
The output capacitance is calculated to be 0.51 µF assuming a ΔVCOPOS of 75 mV using Equation 57 and the
rms current is 0.043 A from Equation 58. 10 µF/25 V capacitors are used for VOPOS and VONEG output.
CO =
IOPOS × D
IONEG × D
=
fSW × ΔVCOPOS
fSW × ΔVCONEG
(57)
Spacer
ICO_rms = Idiode_rms2 - IOPOS2
(58)
INPUT CAPACITOR
The ΔVCIN voltage should be 0.25% to 1% of VIN. The TPS55010 requires a high quality ceramic, type X5R or
X7R, input decoupling capacitor of at least 2.2 µF of effective capacitance or larger coupled to VIN and GND
pins and in some applications additional bulk capacitance. The effective capacitance includes any DC bias
effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The input
ripple current can be calculated using Equation 60, select a capacitor with a larger ripple current rating.
In applications with significant unload transients, the bulk input capacitance must be sized to include energy
transfer from the primary side capacitor to the input capacitor. The input capacitance is calculated 12.4 µF using
Equation 59 and the rms current is 0.495 A. A 47 µF/10 V X5R ceramic capacitor is used on the input. A 0.1 µF
ceramic capacitor is placed as close to the VIN and GND pins as possible for a good bias supply.
Spacer
CIN =
IOPN × D
fSW × DVCIN
(59)
Spacer
ICIN_rms = ILpri_pospk x
D
3
(60)
COMPENSATION
Similar to the single output design, there are several methods used to compensate DC/DC regulators. Since the
slope compensation is ignored, the actual cross over frequency could be lower than the cross over frequency
used in the calculations. This method assumes the cross over frequency is between the modulator pole and 20
times greater the modulator pole. When choosing a crossover frequency with the single capacitor compensation
method (i.e. type 1), use the lower end of the recommended range when developing a supply if the primary
Copyright © 2011, Texas Instruments Incorporated
29
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
capacitor ripple voltage is <1%. Type 2 or 3 compensation should be considered if a low primary ripple design is
preferred. To get started, the modulator pole frequency, fPOLE, determined from Equation 61 should be used to
select the crossover frequency, fCO. In this example, 0.4 kHz is selected as the crossover frequency. The next
step is to determine the compensation gain, ACOMP , at the crossover frequency to compensate the loop.
Equation 64 uses the dc gain of the power stage, modulator pole, and crossover frequency to estimate the gain.
Ri is the current sense gain which is the inverse of the CCOMP to IPH transconductance, which is 7.5 A/V. 11.58
dB is calculated for ACOMP. The compensation pole frequency fCOMP_POLE can be calculated using Equation 65.
AOL in Equation 65 is the open loop gain of the error amplifier and is 500 V/V. fCOMP_POLE is calculated as 0.49
Hz. Using Equation 66, CCOMP is calculated to be 0.159 µF. A 0.1 µF capacitor will be used for CCOMP.
2
æ
æN
ö ö÷
çç
VPRI
÷
RLM + çç
× ççç PRI ÷÷ ÷÷÷
÷
x
I
(1
D)
ççè OPN
èç NSEC ÷ø ø÷÷
Vˆ PRI
»
æ
Vˆ C
s
÷÷ö
Ri × ççç1 +
÷
2 × p x fPOLE ÷÷ø
èç
(61)
Spacer
fPOLE =
1
æ
æV
1 ö÷÷ çç
ç
PRI
2 × p ×çç
×
÷ × ç(1 - D) ×
çèIOPN
(1- D) ÷ø÷ ççç
è
2
ö÷
æC
æ
öö
ççç OPOS x CONEG × çç NSEC1 + NSEC2 ÷÷ ÷÷÷ + C ÷÷
÷÷ ÷÷
çç
PRI ÷÷
çC
NPRI
÷ø ÷
è
çè OPOS + CONEG
ø
ø÷÷
(62)
Spacer
wPOLE
2×p
< fCO < 20 ×
wPOLE
2×p
(63)
Spacer
æ
ö÷
VPRI
çç R
÷÷
+
æ 2×p×f
ö
ççç LM IOPN x (1 - D)÷÷
CO ÷÷
÷÷ - 20 × logççç
A COMP = 20 × logç
÷÷
ç
÷
Ri
èç 2 × p × fPOLE ø÷
÷÷÷
ççç
èç
ø÷÷
(64)
Spacer
VPRI
fCOMP_POLE =
10
Acomp
20
× fCO
× A OL × VREF
(65)
Spacer
1
CCOMP =
2×p×
30
A OL
gmea
× fCOMP_POLE
-
gmea
2 × p × BW
(66)
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
CHARACTERISTICS
18
100
−12
VIN = 5 V
IOPOS = IONEG
IOPOS = IONEG
95
17
−13
16
−14
15
−15
14
−16
90
Positive Voltage (V)
85
Efficiency (%)
80
75
70
65
60
13
VIN = 4.5V
VIN = 4.75V
VIN = 5V
55
50
0.00
0.01
0.02
0.03
Output Current (A)
0.04
−17
VOPOS
VONEG
12
0
0.01
0.05
0.02
0.03
Output Current (A)
0.04
−18
0.05
G051
G050
Figure 43. Efficiency vs Output Current
Figure 44. Output Voltage vs Output Current
−13
16
IOPOS = IONEG = 20 mA
15.5
−13.5
Positive Voltage (V)
VIN = 2 V / div
15
−14
14.5
VOPOS = 10 V / div
−14.5
VOPOS
VONEG
VONEG = 10 V / div
14
−15
VPRI = 2 V / div
13.5
13
VIN = 5 V
IOPOS = IONEG = 40 mA
−15.5
4
4.5
5
Output Current (A)
5.5
6
Figure 45. Output Voltage vs Input Voltage
Copyright © 2011, Texas Instruments Incorporated
Time = 20 ms / div
−16
G051
Figure 46. Power Up with Input Voltage
31
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
VIN = 5 V
IOPOS = IONEG = 40 mA
EN = 5 V / div
VIN = 2 V / div
VOPOS = 10 V / div
VOPOS = 10 V / div
VONEG = 10 V / div
VONEG = 10 V / div
VPRI = 2 V / div
VPRI = 2 V / div
VIN = 5 V
IOPOS = IONEG = 40 mA
Time = 20 ms / div
Time = 20 ms / div
Figure 47. Power Up with Enable Pin
Figure 48. Power Down with Input Voltage
EN = 5 V / div
VONEG = 500 mV / div (ac coupled)
VOPOS = 500 mV / div (ac coupled)
VOPOS = 10 V / div
VONEG = 10 V / div
VIN = 5 V / div
VPRI = 2 V / div
VIN = 5 V
IOPOS = IONEG = 40 mA
Time = 20 ms / div
Time = 40 ms / div
Figure 49. Power Down with Enable Pin
Figure 50. Load Step Response
VOPOS = 500 mV / div
VOPOS = 500 mV / div (ac coupled)
VONEG = 500 mV / div (ac coupled)
VONEG = 500 mV / div (ac coupled)
VIN = 2 V / div
VIN = 5 V / div
IPOS = 50 mA / div
32
VIN = 5 V
IOPOS = IONEG = 20 mA to 40 mA
IPOS = 50 mA / div
VIN = 5 V
IOPOS = IONEG = 40 mA to 20 mA
VIN = 4.5 V to 5.5 V
IOPOS = IONEG = 40 mA
IPOS = 50 mA / div
Time = 40 ms / div
Time = 40 ms / div
Figure 51. Load Step Response
Figure 52. Line Step Response
Copyright © 2011, Texas Instruments Incorporated
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
VIN = 5 V
IOPOS = IONEG = 40 mA
VPRI = 50 mV / div (ac coupled)
VOPOS = 500 mV / div (ac coupled)
VONEG = 500 mV / div (ac coupled)
VONEG = 50 mV / div
IDPOS = 100 mA / div
VIN = 2 V / div
VIN = 5.5 V to 4.5 V
IOPOS = IONEG = 40 mA
ILPRI = 2 A / div
IPOS = 50 mA / div
Time = 40 ms / div
Time = 400 ns / div
Figure 53. Line Step Response
Figure 54. Steady State Waveforms
VIN = 5 V
IOPOS = IONEG = 40 mA
VIN = 50 mV / div (ac coupled)
Gain (dB)
VONEG = 50 mV / div (ac coupled)
50
180
40
135
30
90
20
45
10
0
IDPOS = 100 mA / div
0
−45
−10
−90
VIN = 5 V
IOPOS = IONEG = 40 mA
ILPRI = 2 A / div
−20
−135
Gain
Phase
Time = 400 ns / div
−30
1
10
100
1k
10k
Frequency (Hz)
100k
−180
1M
G055
Figure 55. Steady State Waveforms
Figure 56. Frequency Response
Table 6. Reference Design BOM for Dual Output
Application
5V to +15V/-15V/0.04A
CIN
47uF X5R 6.3V
COPOS,CONEG
10uF X5R 25V
CPRI
10uF X5R 10V
Cboot
0.1uF X5R 10V
CSS
0.1uF X5R 10V
Cc
0.1uF X5R 10V
RHS
13.7k
RLS
10k
Rt
243k
T1
750311780
Wurth Electronics Midcom
DPOS, DNEG
B1100
Copyright © 2011, Texas Instruments Incorporated
33
TPS55010
SLVSAV0A – APRIL 2011 – REVISED JUNE 2011
www.ti.com
PCB LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 57 for a PCB layout example. The GND pins should
be tied directly to the thermal pad under the IC. The power pad should be connected to any internal PCB ground
planes using multiple vias directly under the IC. Additional vias can be used to connect the top side ground area
to the internal planes near the input and output capacitors.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the primary
side of the transformer. Since the PH connection is the switching node, the transformer should be located close
to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation component, slow start capacitor and frequency set resistor should be connected to
a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. Avoid connecting y
capacitor on nodes which experience high dv/dt.
UVLO
Adjust
Resistors
BOOT
FAULT
PH
Thermal
Pad
GND
PH
GND
SS
Secondary
Side Diode
PH
COMP
Network
Output
Capacitor
GND
Slow Start
Capacitor
Resistor
Divider
VOUT
RT/CLK
PH
COMP
VIN
GND
Topside
Ground
Area
VIN
VSENSE
VIN
Input
Bypass
Capacitor
EN
VIN
Via to Ground Plane
Isolation
Transformer
VPRI
Frequency Set
Resistor
Primary
Capacitor
Y Capacitor
Figure 57. PCB Layout
REVISION HISTORY
Changes from Original (April 2010) to Revision A
•
34
Page
Added production data .......................................................................................................................................................... 1
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS55010RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS55010RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS55010RTER
Package Package Pins
Type Drawing
WQFN
RTE
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS55010RTER
WQFN
RTE
16
3000
346.0
346.0
29.0
Pack Materials-Page 2
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