Preliminary R2A20132SP Critical Conduction Mode Interleave PFC Control IC REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Description The R2A20132SP controls two boost converters to provide a active power factor correction. The R2A20132SP is based on R2A20112 and additional functions are Slave drop function at light load, Off time control, Brownout, Double OVP, Dynamic under voltage protection, and ZCD signal open detection. Also the reference voltage tolerance is improved. The R2A20132SP adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improve ripple current on input or output capacitor by 180 degrees phase shift. The feedback loop open detection, over current protection are built in the R2A20132SP, and can constitute a power supply system of high reliability with few external parts. Features • Maximum ratings ⎯ Supply voltage Vcc: 24 V ⎯ Operating junction temperature Tj-opr: –40 to +150°C • Electrical characteristics ⎯ VREF output voltage VREF: 5.0 V ± 1.5% ⎯ UVLO operation start voltage Vuvlh: 10.5 V ± 0.7 V ⎯ UVLO operation shutdown voltage Vuvll: 9.3 V ± 0.5 V ⎯ UVLO hysteresis voltage Hysuvl: 1.2 V ± 0.5 V • Functions ⎯ Boost converter control with critical conduction mode ⎯ Interleaving control with slave drop (SD) function at light load ⎯ Off time control (OTC) function: Switching loss is decreased at light load. ⎯ Brownout function ⎯ Double OVP: Two line sense for over voltage protection ⎯ Dynamic under voltage protection (DUVP): Sense for under voltage protection ⎯ AC Hi voltage detection (ACDET) ⎯ Feedback loop open detection ⎯ ZCD signal open detection ⎯ Master and Slave independenced over current protection ⎯ 140 μs restart timer ⎯ Package lineup: Pb-free SOP-20 Ordering Information Part No. R2A20132SPW0 Package Name FP-20DAV REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 1 of 8 Package Code PRSP0020DD-B Taping Spec. 2000 pcs./one taping product R2A20132SP Preliminary Pin Arrangement ZCD-M 1 20 VCC ZCD-S 2 19 GD-M BO 3 18 GND VREF 4 17 GD-S SD1 5 16 OCP-M ACDET 6 15 OCP-S RT 7 14 OCT RAMP 8 13 FB(+) SD2 9 12 OVP2 COMP 10 11 FB(–) (Top view) Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name ZCD-M ZCD-S BO VREF SD1 ACDET RT RAMP SD2 COMP FB(–) OVP2 FB(+) Input/Output Input Input Input Output Input Output Input/Output Input/Output Input Output Input Input Input Function Master converter zero current detection input terminal Slave converter zero current detection input terminal Brownout input terminal Reference voltage output terminal Slave drop threshold voltage input terminal (for Lo line: 100 V) AC hi voltage detection output terminal Oscillator frequency setting terminal Ramp waveform setting terminal Slave drop threshold voltage change terminal (for Hi line: 200 V) Error amplifier output terminal Error amplifier input (–) terminal Over voltage detection terminal Error amplifier input (+) terminal OTC OCP-S OCP-M GD-S GND GD-M VCC Input Input Input Output — Output Input Off time control input terminal Slave converter over current detection terminal Master converter over current detection terminal Slave converter Power MOSFET drive terminal Ground Master converter Power MOSFET drive terminal Supply voltage terminal REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 2 of 8 R2A20132SP Preliminary Block Diagram VCC VREF: 5 V ZCD-M Clamp – 0 V to 6.4 V + Clamp 0 V to 6.4 V GD-M GND – Slave Control + RT GD-S VREF BO OCP COMP1 + OCP-M Stop GD + 1.4 V – OCP COMP2 + OCP-S Hi: ON – LOGIC GD Disable + OCP-M – 7.7 μA 3.6 V/3.0 V VCC ZCD open detector Vzcd_lo = 1.4 V 300 mVhys ZCD-S UVLO ON: 10.5 V OFF: 9.3 V OCP-S – OVP2 0.31 V OVP BLOCK COMP Discharge ACDET FB(–) OVP2 – + VCC Error Amp – Slave off 7.7 μA FB(–) + Hi: ON FB(+) Hi: SD1 SD2 1.3 V + SD1 COMP – VCC + Iramp – Hi: OFF OTC 1.3 V RAMP 9.1 V COMP REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 3 of 8 R2A20132SP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings –0.3 to 24 Unit V Note –300 +1200 mA 3 Supply voltage GD peak current VCC Ipk-gd GD DC current Idc-gd –15 +60 mA ZCD terminal current Izcd mA BO terminal current RT terminal current Vref terminal current COMP terminal current ACDET terminal current Terminal voltage Vref terminal voltage Power dissipation Operating junction temperature Ibom Irt Iref Icomp Iacdetm Vt-group1 Vt-group2 Vt-ref Pt Tj-opr +10 –10 300 –200 –5 ±1 500 –0.3 to Vcc –0.3 to Vref –0.3 to Vref + 0.3 1 –40 to +150 Storage temperature Tstg –55 to +150 °C Notes: 1. 2. 3. 4. μA μA mA mA μA V V V W °C Rated voltages are with reference to the GND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. This is the rated voltage for the following pins: RAMP, ACDET 5. This is the rated voltage for the following pins: FB(+), FB(–), OCP-M, OCP-S, OVP2, SD1, SD2, OTC 6. In case of R2A20132SP (SOP): θja = 120°C/W This value is a thing mounting on 40 × 40 × 1.6 [mm], a glass epoxy board of wiring density 10%. REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 4 of 8 4 5 6 R2A20132SP Preliminary Electrical Characteristics (Ta = 25C, VCC = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, FB(+) = 2.5 V, FB(–) = COMP, BO = 5 V, OVP2 = GND, SD1 = SD2 = GND) Item Supply Brownout VREF Error amplifier RAMP Symbol Min Typ Max Unit Test Conditions UVLO turn-on threshold Vuvlh 9.8 10.5 11.2 V UVLO turn-off threshold Vuvll 8.8 9.3 9.8 V UVLO hysteresis Hysuvl 0.7 1.2 1.7 V Standby current Istby — 150 230 μA VCC = 8.9 V, ZCD = OPEN Operating current Icc — 5.2 7.5 mA FB(–) = open BO threshold voltage Vbo 1.33 1.40 1.47 V BO pin hysteresis current Ibo 6.9 7.7 8.5 μA BO = 1 V Output voltage Vref 4.925 5.000 5.075 V Isource = –1 mA Line regulation Vref-line — 5 20 mV Isource = –1 mA, Vcc = 10 V to 24 V Load regulation Vref-load — 5 20 mV Isource = –1 mA to –5 mA Temperature stability dVref — ±80 — ppm/°C Feedback voltage Vfb(–) 2.462 2.500 2.538 V FB(–)-COMP Short, RAMP = 0 V Input bias current1 Ifb(–) –0.5 –0.3 –0.1 μA Measured pin: FB(–), FB(–) = 3 V Input bias current2 Ifb(+) 0.1 0.3 0.5 μA Measured pin: FB(+), FB(+) = 3 V Ta = –40 to +125°C * 1 Open loop gain Av — 50 — dB *1 Upper clamp voltage Vclamp-comp 8.0 9.1 10.6 V FB(–) = 2.0 V, COMP: Open Low voltage Vl-comp — 0.1 0.3 V FB(–) = 3.0 V, COMP: Open Source current1 Isrc-comp1 — –120 — μA FB(–) = 0 V to 1.5 V, COMP = 2.5 V Source current2 Isrc-comp2 — –1 — mA FB(–) = 3 V to 1.5 V, COMP = 2.5 V Sink current Isnk-comp — 300 — μA FB(–) = 3.5 V, 1 COMP = 2.5 V * Transconductance gm 100 180 270 μs FB(–) = 2.45 V ↔ 2.55 V, COMP = 2.5 V RAMP charge current1 Ic-ramp1 72 82 92 μA RAMP = 0 V to 7 V, FB(–) = 2 V, COMP = 2 V, SD2 = 2.5 V RAMP charge current2 Ic-ramp2 150 165 180 μA RAMP = 0 V to 7 V, FB(–) = 2 V, COMP = 5 V, SD2 = 2.5 V RAMP discharge current Id-ramp 7 15 29 mA FB(–) = 3 V, COMP = 2 V, RAMP = 1 V Low voltage Vl-ramp — 17 200 mV FB(–) = 3 V, COMP = 3 V, Isink = 100 μA Zero Upper clamp voltage Vzcdh 5.8 6.4 7.0 V current detector Lower clamp voltage Vzcdl –0.5 0 0.5 V Isink = 3 mA ZCD low threshold voltage Vzcd-lo 0.95 1.40 1.65 V *1 ZCD hysteresis Hyszcd 180 300 390 mV *1 Input bias current Izcd –14 –10 –6 μA 1.2 V < Vzcd <5 V Note: 1. Design spec. REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 5 of 8 Isource = –3 mA R2A20132SP Preliminary Electrical Characteristics (cont.) (Ta = 25C, VCC = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, FB(+) = 2.5 V, FB(–) = COMP, BO = 5 V, OVP2 = GND, SD1 = SD2 = GND) Item Symbol Min Typ Max Unit Test Conditions Restart Restart time delay Tstart 105 140 175 μs FB(–) = 2.0 V, COMP = 5 V * ACDET ACDET current Iacdet 0 1 2 μA Vacdet = 12 V, Vbo = 3.3 V ACDET voltage Vacdet 0.2 0.4 0.6 V Iacdet = 500 μA, Vbo = 3.7 V High threshold voltage Vacdet-hi 3.2 3.6 4.0 V Measured Pin: BO Low threshold voltage Vacdet-lo 2.6 3.0 3.4 V Measured Pin: BO Slave control Phase delay Phase 160 180 200 deg On time ratio Ton-ratio –5 — 5 % *1, *3 Slave drop Input bias current Isd1 –1.0 –0.5 1.0 μA SD1 = 1 V, COMP = 4 V, FB(–) = 0 V Isd2 –1.0 –0.5 1.0 μA SD2 = 1 V, COMP = 4 V, FB(–) = 0 V SD pin hysteresis current Isd-hys –8.5 –7.7 –6.9 μA SD1 = 2 V, BO = 2 V, COMP = 2 V, FB(–) = 0 V Input bias current Iotc –1.0 0 1.0 μA OTC = 3 V Off time control Note: *1, *3 1. Design spec. 2. Tstart (140 μs) [A period without ZCD-M trigger] Vzcd-lo (1.4 V: provide 300 mV hysteresis) ZCD-M GD-M Restart pulse 3. Tperiod (25 μs) Ton-m (17 μs) GD-M Tdelay GD-S Phase = Tdelay × 360 [deg] Tperiod Ton-ratio = 1 – Ton-s × 100 [%] Ton-m REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 6 of 8 Ton-s 2 R2A20132SP Preliminary Electrical Characteristics (cont.) (Ta = 25C, VCC = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, FB(+) = 2.5 V, FB(–) = COMP, BO = 5 V, OVP2 = GND, SD1 = SD2 = GND) Item Gate drive Over Symbol Min Typ Max Unit Test Conditions Master gate drive rise time tr-gdm — 30 100 ns GD-M: 1.2 V to 10.8 V, CL = 100 pF Slave gate drive rise time tr-gds — 30 100 ns GD-S: 1.2 V to 10.8 V, CL = 100 pF Master gate drive fall time tf-gdm — 5 30 ns GD-M: 10.8 V to 1.2 V, CL = 100 pF Slave gate drive fall time tf-gds — 5 30 ns GD-S: 10.8 V to 1.2 V, CL = 100 pF Master gate drive low voltage Vol1-gdm — 0.02 0.1 V Isink = 2 mA Vol2-gdm — 0.01 0.2 V Isink = 1 mA, VCC = 5 V Master gate drive high voltage Voh-gdm 11.5 11.9 — V Isource = –2 mA Slave gate drive low voltage Vol1-gds — 0.02 0.1 V Isink = 2 mA Vol2-gds — 0.01 0.2 V Isink = 1 mA, VCC = 5 V Slave gate drive high voltage Voh-gds 11.5 11.9 — V Isource = –2 mA * OCP threshold voltage Vocp 0.28 0.31 0.34 V Dynamic OVP threshold voltage Vdovp VFB(+) VFB(+) VFB(+) V COMP = OPEN ×1.035 ×1.050 ×1.065 OVP1 threshold voltage Vovp1 VFB(+) VFB(+) VFB(+) V COMP = OPEN ×1.075 ×1.090 ×1.105 1 current protection Over voltage protection ZCD open detector Note: OVP1 hysteresis Hys-ovp1 50 100 150 mV COMP = OPEN FB(–) open detect threshold voltage Vfbopen 0.45 0.50 0.55 V COMP = OPEN FB(–) open detect hysteresis Hysfbopen 0.16 0.20 0.24 V COMP = OPEN OVP2 threshold voltage Vovp2 2.635 2.685 2.735 V COMP = OPEN, VFB(–) = 2.5 V OVP2 hysteresis Hys-ovp2 50 100 150 mV COMP = OPEN, VFB(–) = 2.5 V OVP2 pin input bias current Iovp2 –0.5 0 0.5 μA Measured pin: OVP2 Dynamic UVP threshold voltage Vduvp VFB(+) VFB(+) VFB(+) V COMP = OPEN ×0.89 ×0.92 ×0.95 Slave ZCD open minimum detect delay time tzcds — 100 — 1. Design spec. REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 7 of 8 ms COMP = 5 V, 1 Gate drive 10 kHz * R2A20132SP Preliminary Package Dimensions JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 10 1 Z e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F REJ03D0921-0100 Rev.1.00 Oct 02, 2009 Page 8 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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