MP020-5 - Monolithic Power Systems

AN062
Offline Primary-Side Regulator
With CV/CC control and 700V FET
The Future of Analog IC Technology
Application Note for Flyback Converter
Using the Primary-Side Regulator
MP020-5
Prepared by Simen Long
April 10, 2012
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
AN062
Offline Primary-Side Regulator
With CV/CC control and 700V FET
The Future of Analog IC Technology
ABSTRACT
This paper mainly presents design guidelines for flyback converter using the primary-side regulatorMP020-5. Typical application schematic is shown in Figure 1. Design of a flyback converter with
primary-side regulator of MP020-5 is quite simple and straightforward through the step-by-step design
procedure described in this application note. Some importance aspects we need to pay attention during
the design procedure are also clearly stated. Experimental results based on the design example are
presented in the last part.
Figure 1-Flyback Converter with the Primary-Side Regulator-MP020-5
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
2
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
INDEX
Abstract ................................................................................................................................................. 2
1. Introduction........................................................................................................................................ 4
2. Primary-side regulator operation introduction..................................................................................... 4
3. Design procedure .............................................................................................................................. 6
A. Predetermined Input and Output Specifications ......................................................................... 6
B. Determine the Startup Circuitry .................................................................................................. 7
C. Primary Side Inductance Lp ....................................................................................................... 9
D. Turns Ratio-Nps ......................................................................................................................... 9
D-1. Maximum Nps ........................................................................................................................ 10
D-2. Nps calculation ....................................................................................................................... 11
E. Transformer Design.................................................................................................................. 14
E-1. Transformer Core Selection .................................................................................................. 14
E-2. Primary and Secondary Winding Turns ................................................................................. 14
E-3. Wire Size............................................................................................................................... 15
E-4. Air Gap.................................................................................................................................. 16
F. Cable Compensation ................................................................................................................ 16
G. Design the RCD Snubber......................................................................................................... 17
H. Design the Output Filters.......................................................................................................... 19
I. Key points for system operation................................................................................................. 19
4. Design Summary ............................................................................................................................. 22
5. Experimental verification.................................................................................................................. 24
6. References: ..................................................................................................................................... 29
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
3
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
1. INTRODUCTION
The MP020-5 is a high performance AC/DC power supply regulator adopting primary-side control
technique which can provides accurate constant output voltage and tight constant output current
regulation without opto-coupler and a secondary feedback circuit. MP020-5 has an integrated 700V
MOSFET designed for offline supplies within 5W output power. Typical applications include cell phone
charges, adapters for handheld electronics, stand-by and auxiliary power supplies and LED driver and
so on.
The IC uses a variable off-time control method and it always operates in discontinuous conduction
mode (DCM). The regulator decreases its frequency as the load becomes lighter. As a result, it offers
excellent light load efficiency and the switching frequency will decrease to the minimum frequency
when converter run at no load conditon.
The MP020-5 also features complete protection functions such as VCC under-voltage lockout, overcurrent protection, over temperature protection, open loop protection and over voltage protection. Its
internal high-voltage start-up current source and power-saving technologies limit the no-load power
consumption to less than 30mW.
Table 1: Output power table
Part Num.
MP020-5GS
Ron(Ω)
10
I_limit(A)
0.38
Package
SOIC8-7A
Maximum Output
Power(W) (85-265Vac)
Adapter
5
This application note presents detailed step-by-step design guidelines for an off-line flyback converter
employing MP020-5, mainly including transformer design, component selection and other key points.
2. PRIMARY-SIDE REGULATOR OPERATION INTRODUCTION
The MP020-5 is a high performance AC/DC power supply regulator for the cost effective low power
charger and adapter applications. It can achieve accurate constant voltage (CV) and tight constant
current (CC) regulation without opto-coupler and secondary control circuitry. Meanwhile, it also
eliminates the need of loop compensation circuitry while maintaining system stability. In addition, its
internal high-voltage start-up current source and power-saving technologies limit the no-load power
consumption to less than 30mW.
The MP020-5 uses a variable off-time control method (PFM) and it always operates in discontinuous
conduction mode. So, the switching frequency presents a linear characteristic with the change of load.
The CV and CC regulation are all realized by modulating switching frequency.
Constant Voltage Operation (CV)
The MP020-5 detects the auxiliary winding voltage from the FB pin and operates in constant voltage
(CV) mode to regulate the output voltage.
Assuming the secondary winding and the auxiliary winding are well coupled, the FB pin voltage can be
got as follow:
VFB =
Naux
Rdown
× (VO + Vf ) ×
Ns
Rup + Rdown
(1)
Where Vf is the secondary diode forward drop voltage. Rup and Rdown are the divided resistors.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
4
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 2- Auxiliary Winding Waveform
The output voltage is different from the secondary voltage because of a current-dependant diode
forward voltage drop. If the secondary voltage is always detected at a fixed secondary current, the
difference between the output voltage and the secondary voltage will be a fixed Vf. The MP020-5
samples the auxiliary winding voltage at 3.5µs after the primary switch turns off. The CV loop control
function of MP020-5 then generates the secondary side diode OFF time to regulate the output voltage.
Constant Current Operation (CC)
Figure-3 shows the illustration of the constant current operation.
Figure 3- CC Operation
The flyback always works in DCM using the MP020-5 and in constant current (CC) operation, the ZCD
sample block can detect the duty cycle of the secondary side diode. The calculated output current from
the Io estimator block compares with Io_ref and the error signal Vcomp_i controls the turn on signal of the
integral MOSFET. So the output current Io can be got as follow from the Figure 3.
Io =
1 Np
×
× Ipk × Ds
2 NS
(2)
Where:
Ds: the duty cycle of the secondary diode;
Ipk: the peak current of the primary side MOSFET;
Np: the turns of the transformer primary side
Ns: the turns of the transformer secondary side.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
3. DESIGN PROCEDURE
There is quite few external component need to choose so it makes the application simple and cost
down. The key parameter is the primary-secondary turns ratio of the transformer for tight CC
characteristic and the Design flow about the transformer can be referred to Figure 4.
Figure 4- Transformer Design Flow Chart
A. Predetermined Input and Output Specifications
- Input AC voltage range: VAC(min), VAC(max), for example 85Vac~265Vac RMS universal input;
- Output: Vo, Io(min),Io(max),Pout;
- Estimated efficiency: η, it is used to estimate the power converter efficiency to calculate the
maximum input power. Generally, η is set to be 0.65~0.8 according to different output applications.
For example, η can be estimated about 0.7 in the 5W cell phone application.
Then the maximum input power can be given as:
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
6
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Pin =
Vo × I o
η
(3)
Figure-5 illustrates the typical DC bus voltage waveform. The DC input capacitor Cin is usually set as
2uF/W for the universal input condition and full bridge rectifier for 230Vac single range application, the
capacitance can be half the value.
Figure 5- Input Voltage Waveform
From Figure-5, the AC input voltage Vac and DC input voltage VDC can be got as follow:
VDC (Vac ,t) = 2 × Vac 2 −
2 × Pin
×t
Cin
(4)
At t1, the DC bus voltage equals to the AC input again, and the DC bus capacitor will be charged up
again. Then, the DC bus voltage at t1 is its minimum value VDC(min), which can be calculated as:
VDC (min) = VDC (VAC(MIN) ,t1 )
(5)
Then, the minimum average DC input voltage Vin(min) is given as:
VIN(min) =
2 ⋅ Vac(min) + VDC(min)
2
(6)
The maximum average DC input voltage Vin(max) can be got as :
VIN(max) = 2 ⋅ Vac(max)
(7)
In application, the minmum DC input voltage should be not too low which can not supply the full load.
It’s recommend that the minmum DC input voltage is not less than 2/3 Nps(Vo+Vf). If the minmum DC
input voltage is too low, the input line ripple and output ripple will be bigger than normal operation.
B. Determine the Startup Circuitry
Initially, the IC is self supplied by the internal high voltage current source, which is drawn from the Drain
pin. The internal high voltage current source will turn off for better efficiency as soon as the voltage of
Vcc pin reaches the Vcc ON threshold. Afterward, it will be taken by the auxiliary winding of the
transformer. When Vcc falls below the Vcc OFF threshold, the IC stops the switching and the internal
high voltage current source turns on again. The theoretical startup waveforms are shown as Figure6.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
7
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 6- Vcc UVLO
To satisfy the requirement of the startup time, the cap of the VCC should be chose as follow:
Cvcc ≤
Ich arg e ⋅ Tstartup
VCCH
(8)
Where:
Cvcc:the cap of Vcc for IC power supply;
Icharge: the charge current of internal high voltage current;
Tstartup: the startup time of the IC start to work normally;
VCCH: the Vcc on threshold or the threshold of the internal high voltage current source turn off;
For example, if the Tstartup is 0.5s, Icharge is 550μA typically, VCCH is 17.3V typically, so the Vcc can be
calculated about 16μF.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
8
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
C. Primary Side Inductance Lp
For a flyback converter with MP020-5, due to the DCM operation, the output power is given as:
Po =
1
⋅ Lm ⋅ Ipk 2 ⋅ fs ⋅ ηs
2
(9)
Where Lm is the inductance of the transformer, Ipk is the peak current of the primary-side(Ipk is constant
about 0.38A in MP020-5), fs is the switching frequency of the converter at full load and the ηs is the
efficiency of the power transferred to secondary side by transformer, as usually,. ηs can be estimated
about 0.95 in 5W application.
The output power Po increases linearly with the switching frequency fs increase because the Ipk keeps
constant. So, we can calculate the Lm with equation (10).
Lm =
2 ⋅ Po
Ipk ⋅ fs ⋅ ηs
2
(10)
D. Turns Ratio-Nps
The system should work in DCM under all conditions, especially with minimum input voltage and full
load. Therefore equation (11) must be satisfied to guarantee the converter in DCM operation with
minimum input voltage and full load condition. According to (11), we can derive the maximum turn ratio
Nps limitation.
Figure 7- VDS, Primary Side Current and Secondary Side Current
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
9
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Ts ≥ Tp _ on + Ts _ on
(11)
Where:
Tp_on: the time of switch turn on;
Ts_on: the time of secondary side diode turn on;
Ts: the working cycle;
Tw: the resonant time of inductance and capacitor of the switch;
Ipk: the peak current of the primary side;
Ipks: the peak current of the secondary side;
D-1. Maximum Nps
Figure-7 shows the primary side MOSFET Drain-Source voltage, primary side current and secondary
side current waveform. Since the converter operates in DCM mode, the magnetizing current increases
from zero to its peak value and then drops to zero linearly in each switching cycle. The primary side
switch on time and secondary diode on time can be calculated as follow:
Tp _ on = Ipk
Ts _ on = Ipk
Lm
Vin
(12)
Lm
Nps (Vo + Vf )
(13)
Where:
Vf: the forward voltage of secondary diode;
Nps:the transformer turns ratio (primary to secondary)
From the equation (11),(12),(13), we can get the (14).
Ipk
Lm
L
+ Ipk m ≤ Ts
Nps (Vo + Vf )
Vin
(14)
As described in the operation principle of MP020-5 under CC mode, the CC loop control function of
MP020-5 will keep the calculated Io by Io estimator block about the Io_ref, so the Ds is kept constant
indirectly and the Ds is about 0.4 in CC mode.
Ts = Ts _ on ×
1
Ds
(15)
So, from the equation (12), (13), (14) and (15), the following expression will be got:
Vin ≥ Nps ⋅ (Vo + Vf ) ⋅
Ds
1 − Ds
(16)
The input DC voltage should satisfy the in equation (16) to ensure the converter can supply the power
for load in DCM operation. It’s easy to satisfy the in equation with high input voltage, but it should also
be satisfied with low input voltage. The equation (16) can be rewritten as,
Nps ≤
Vin
1 − Ds
⋅
(Vo + Vf ) Ds
(17)
When the Vin is the minimum value, the maximum Nps can be got as following:
Nps ≤ Nps max =
AN062 Rev. 1.2
12/30/2013
Vin min 1 − Ds
⋅
(Vo + Vf ) Ds
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
(18)
10
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Ineqation (18) sets the up limit for the transformer turns ratio with a given minimum DC voltage. If the
calculated Nps described below doesn’t satisfy the in equation (18), we should recalculate the Nps by
increasing the value of the input cap to increase the Vinmin.
D-2. Nps calculation
Figure-8 shows the ideal current waveform at secondary side, the output current can be easily
calculated as:
Io =
T
1
1
× Ipks × s _ on = × Ipks × Ds
2
Ts
2
(19)
Ipks is the peak current of the secondary side.
Figure 8- Secondary Side Current Waveform
And,
Ipks = Nps ⋅ Ipk
(20)
Assume there is no power loss during the period when the magnetizing currnt transfers from primary
side to secondary side after the primary siwtch turns off and the transition time can be neglected, so
we can take (20) into equation (19),
Io =
1
× Nps × Ipk × D s
2
(21)
Baed on the equation(21), the Nps can be determined based on the desired output current under this
ideal assumption.
Nps =
2 × Io
Ipk × D s
(22)
In practice applicaiton, there is always leakage inductance and core loss,so the acutual Is_pk will be
slightly less than Nps ⋅ Ipk. And the practical waveform is illustrated as Figure-9.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
11
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 9- The Transition of the Primary Side Current and Secondary Side Current
Considering the leakage inductance and core loss, the energy transferred to output should exclude the
energy stored in the leakage inductor and the core loss. The power stored in the leakage inductor is
given in equation(23).
Plk =
1
⋅ Lk ⋅ Ipk 2 ⋅ fs
2
(23)
Assume the coupling coefficient of the transformer is K and K is determined by transformer structure.
K = 1−
Lk
Lm
(24)
So the equation(23) also can be expression as follow:
Plk =
1
⋅ (1 − K)Lm ⋅ Ipk 2 ⋅ fs
2
(25)
On the other side ,the core loss can be got as follow:
Ptrans = Cm ⋅ fs xBac y ⋅ (Cto − Ct1 ⋅ Tcore + Ct2 ⋅ Tcore 2 ) ⋅ Ve
(26)
Where:
Cm, x, y, Ct0, Ct1, Ct2 are coefficients related to core of PC40, Cm=2.65901, x=1.37276, y=2.51937,
Ct0=4.2061, Ct1=0.065, Ct2=0.00032938483. The coefficients should be adjusted according different
materials.
Tcore: the working temperature of the core;
Ve: the volume of the core;
Considering these effect, the practical power transferred to secondary side can be got :
Plm = Pm − Plk − Ptrans
(27)
According the equation(23), (24), (25), (26), (27), the equivalent peak current of primary side can be got
as follow:
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
12
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
K ⋅ Lm ⋅ Ipk 2 ⋅ fs − 2 ⋅ Ptrans
2 ⋅ (Pm − Plk − Ptrans )
Ipk1 =
=
Lm ⋅ f s
Lm ⋅ fs
(28)
If the transition time can not be ignored, the practical secondary side peak current can be got as
equation (29):
Ipks = Nps ⋅
K ⋅ Lm ⋅ Ipk 2 ⋅ fs − 2 ⋅ Ptrans
Lm ⋅ fs
(29)
Due to the exisiting of leakage inductance, there is certain currnt transition time when the magnetizing
current transfers from primary side to secondary side as shown as figure-9.
This transition interval includes two sub-intervals, one is charging cource of paristic capacitor of the
primary side mosfet (T1) and the second sub-interval is current commuation period, secondary side
current rise to peak current(T2).
T1 =
Cp ⋅ [Nps ⋅ (Vo + Vf ) + Vin]
Ipk
(30)
Where Cp is the parasitic capacitor of the primary MOSFET and T1 is just the time for voltage across
the MOSFET rises from zero to Nps ⋅ (Vo + Vf ) + Vin .
T2 =
Lk ⋅ Ipk
Vclamp
=
K ⋅ Lm ⋅ Ipk
Vclamp
(31)
Where Vclamp is the calmp voltae of RCD clamp circuit and T2 is the time of secondary side current
rise from zero to peak current.
The calculation of Vclamp can be refered to RCD design and usually, the Vclamp is about 50%~100%
Nps ⋅ (Vo + Vf ) .
The ideal secondary side diode conduction time Ts_on and the T1,T2 can be calculated from equation
(13), (30) and (31), so the secondary side peak current considering these non-ideal characteritic can be
calculated as follow:
Ipks1 = Ipks ⋅ (1 −
T1 + T2
)
Ts _ on
(32)
So, the output current can be got:
Io =
1
× Ipks1 × Ds
2
(33)
According the equation(29), (30), (31), (32), (33), the relationship between output current Io and Nps is
given in (34). And we can resolve it to get the desired Nps.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
13
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
K ⋅ Lm ⋅ Ipk 2 ⋅ fs − 2 ⋅ Ptrans
2 × Io
= Nps ×
Ds
Lm ⋅ fs
⎡
⎢
⎢ Cp ⋅ [Nps ⋅ (Vo + Vf ) + Vin] K ⋅ Lm ⋅ Ipk
+
⎢
Ipk
Vclamp
× ⎢1 −
⎢
K ⋅ Lm ⋅ Ipk 2 ⋅ fs − 2 ⋅ Ptrans
⎢
Nps ×
Lm ⋅ fs
⎢
⎢
Nps ⋅ (Vo + Vf )
⎣
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎦
(34)
If the Nps calculated from (34) satisfies the inequation (18), the result is ok. If not, we should modify the
minimum input voltage and recalculate the Nps Until it satisfies inequation (20) at the same time.
E. Transformer Design
E-1. Transformer Core Selection
A core appropriate for certain output power at the operating frequency needs to be selected fristly.
Ferrite is usually preferred for flyback transformer. The core area product (AeAw) which is the core
magnetic cross-section area multiplied by its window area available for winding, is widely used for an
initial estimate of core size for a given application. A rough indication of the required area product is
given by following:
⎛ L ⋅I ⋅I
× 10 4 ⎞
A e ⋅ A w = ⎜ m pk p _ rms
⎜ Bmax ⋅ K u ⋅ K j ⋅ fs min ⎟⎟
⎝
⎠
43
cm4
(35)
Where:
Ku :winding factor which is usually 0.25 - 0.3 for an off-line transformer;.
Kj : the current density coefficient which is typically 400 - 600 for ferrite core;
Ipk: the maximum peak current of primary inductance;
Ip_rms: the RMS current of the primary inductance;
Bmax : the allowed maximum flux density which is usually preset to be the saturation flux density of the
core material (0.3T - 0.4T). It can be minished properly for good audible noise;
fs: the switching frequency at low line and full load condition.
MP020-5 works in DCM, so the RMS current can be given by following:
Ip _ rms =
Lm ⋅ Ipk 3
3 × Vin min
⋅ fs
(36)
Refer to the ferrite core manufacture’s datasheet to select a proper core.
E-2. Primary and Secondary Winding Turns
With a given core size, of the primary side winding turns Np is given as follows to prevent the core from
saturation and to achieve desired inductance:
Np =
Lm ⋅ Ipk
A e × Bmax
(37)
Bmax should be smaller than saturation density Bsat at high operation temperature because the Bsat will
decrease as the temperature increases.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
14
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Secondary winding turns Ns can be easily calculated with transformer turns ratio Nps and Np, which is
given as:
Ns =
Np
(38)
Nps
E-3. Wire Size
Once all the winding turns are determined, the wire size should be properly chosen to minimize the
winding conduction loss and leakage inductance. The winding loss depends on the its RMS current, the
length and the cross section area of the wire, also the transformer winding structure.
The wire size could be determined by the RMS current of the winding. For a flyback converter, the RMS
current on primary side is given by equation (39), and the RMS current on secondary side is given by
following:
Is_ rms =
Lm ⋅ Ipk 3
3 × Vo
⋅ fs ⋅ Nps
(39)
Then, the wire cross section area required for secondary side is:
Ss =
Sp =
Is_ rms
J
Ip _ rms
J
(mm2 )
(40)
(mm2 )
(41)
Here J is the current density of the wire which is 500A/cm2 typically.
Due to the skin effect and proximity effect of the conductor ,the diameter of the wire should be less than
2 Δd ( Δd : the skin effect depth):
Δd =
1
(mm)
π ⋅ fs ⋅ μ ⋅ σ
(42)
Where:
σ : the conductivity of the wire, typically about 6 × 107 S / m at 0 deg for copper, and it will increases as
the temperature increases, which means the Δd will get smaller.
μ : the magnetic permeability of the conductor, which usually equals to the permeability of vacuum for
most conductor, 4π × 10−7 H / m ; If the required size of the winding is larger than Δd , multiple strands of
thinner wire or Litz wire is usually adopted to minimize the AC resistance. The effective cross section
area of multi-strands wire or Litz wire should be large enough to meet the requirement set by the
current density.
After the wire size have been determined, it is necessary to check whether the window area with
selected core can accommodate the windings calculated in the previous steps. The window area
required by each winding should be calculated respectively and add together, the area for inter-winding
insulation, bobbin and spaces existing between the turns should also be taken into consideration. The
fill factor, means the winding area to the whole window area of the core, should be well below 1 due to
these inter-winding insulation and spaces between turns. It is recommended that a fill factor no greater
than about 0.3. For transformers with multiple outputs this factor may need to be reduced further.
Based on these considerations the total required window area is then compared to the available
window area of a selected core. If the required window area is larger than the selected one, either wire
size must be reduced, or the larger core must be chose. Of course, a reduction in wire size increases
the copper loss of the transformer.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
15
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
E-4. Air Gap
With the selected core and winding turns, the air gap of the core can be calculated by following
expression:
L gap = μ0 ⋅ A e ⋅
Np 2
Lm
−
lc
μr
(43)
Where:
μ0 : the permeability of vacuum which equals 4π × 10−7 H / m ;
μr : the relative magnetic permeability of the core material;
Ae: the cross sectional area of the selected core;
lc: the core magnetic path length;
Lm: the primary inductance ;
Np: the primary winding turns.
Usually, the μr is very large, so the Lgap can be approximately calculated as equation(44).
L gap ≈ μ0 ⋅ A e ⋅
Np 2
Lm
(44)
F. Cable Compensation
The MP020-5 has an internal output cable compensation circuit as shown in Figure-10. The internal
ZCD sample can can detect the duty of the secondary side diode. The duty signal can be converted to
a DC voltage through a low-pass filter. The filter voltage VCP changes as the load current variety.
VCP can be converted to a current signal sinks current from the FB pin. The voltage drop on the upper
resistor of the divider will change the output voltage and realizes the output cable compensation..
Figure 10- Output Cable Compensation
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
16
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
The formula of the compensation voltage of full load as follow:
VFCP =
5.6 × DS
N
× 2 × RUP × S
3
360 × 10
NAUX
(45)
VFCP: the compensation voltage drop on the secondary side diode and the cable resistor when full
load;
DS: the duty cycle of secondary side diode, it’s about 0.4 in CC mode;
Rup: upper resistor of divided voltage resistor;
NS: the secondary side winding turns of transformer;
Naux: the auxiliary winding turns of transformer;
So, we can choose the Rup to design the cable compensation voltage.
It should be noted that the Rup is also the key component as the divider resistor to decide the output
voltage. From equation (1), we can get the following equation.
Vref =
Naux
Rdown
× (VO + Vf ) ×
Ns
Rup + Rdown
(46)
Where the Vref is the reference voltage of the IC for CV, Rdown is the down resistor of the voltage divided
resistors.
So, when the Rup is determined by the equation (45), then the Rdown should be designed based on (46).
To achieve more accurate CV regulation, the accuracy of these feedback resistors should be at least
1%. Besides, the divided resistors is recommended to select from 10k Ω to 100k Ω for better
performance to avoid the noise disturb the internal logic.
Another key point for the good CV characteristic is the output filter capacitor. A low ESR capacitor is
preferred to reduce the output voltage ripple caused by the pulsing current, which will make the
sampling point more precise.
G. Design the RCD Snubber
The energy stored in the leakage inductor can not be transferred to the secondary side in the Flyback
converter when switch turns off. And the energy may result in a high voltage spike across the primary
side switch, which may destroy the MOSFET if the spike is not damped. So, the voltage spikes should
be suppressed to an acceptable level to protect the switch.
The RCD snubber is usually adopted to clamp the drain voltage. The RCD clamp circuit and its key
steady state waveforms are shown in the Figure-11 and Figure-12 respectively. The energy stored in
the parasitic inductor must be dissipated by the RC network during each cycle and the value of the
capacitor Csn and resistor Rsn sets the clamp voltage Vsn.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
17
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 11- The RCD Clamp Circuit
Figure 12- Waveforms
The energy stored in the leak indcutor is expressed as follow:
Psn =
1
⋅ Lk ⋅ Ipk 2 ⋅ fs
2
(47)
Where Lk is the primary side referred leakage inductance and the Ipk is the peak current in the primary
side.
The RCD snubber circuit absorbs the energy in the leakage inductor when the Vds exceeds Vin+Vsn. It is
assumed that the snubber capacitor is large enough thus its voltage keeps constant during a switching
period.
When the MOSFET turns off and Vds is charged to Vin+Nps×Vo, the secondary diode turns on at the
same time. The primary current continues to flow through the snubber diode (Dsn) to Csn. The voltage
stress of MOSFET is clamped to Vin+Vsn. Therefore, the voltage across Lk is Vsn- Nps×Vo. The slope of
isn is given by equation (48).
V − Nps × Vo
disn
= −( sn
)
dt
Lk
(48)
Where isn is the current flows into the snubber circuit, Vsn is the voltage across the snubber capacitor
Csn. The transition time ts is obtained by following equation:
ts =
AN062 Rev. 1.2
12/30/2013
Lk
× Ipk
Vsn − Nps × Vo
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
(49)
18
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Typically, we can assume an acceptable clamp voltage Vsn which is usually 50%~100% higher than the
reflected output voltage Nps × Vo. So, the power dissipated in the snubber circuit is obtained by equation
(50)
Psn = Vsn ⋅
Ipk ⋅ t s
2
Vsn
1
⋅ Lk ⋅ Ipk 2 ⋅
× fs
2
Vsn − Nps × Vo
⋅ fs =
(50)
On the other hand, since the power consumed in the snubber resistor is Vsn 2 Rsn , the resistance is
calculated as:
Rsn =
Vsn 2
Vsn
1
⋅ Lk ⋅ Ipk 2 ⋅
⋅ fs
2
Vsn − Nps × Vo
(51)
The maximum ripple of the snubber capacitor voltage is obtained as follow:
ΔVsn =
Vsn
Csn ⋅ R sn ⋅ fs
(52)
Generally, 15% ripple is reasonable.
Normally, it’s recommended the time constant τ=Rsn×Csn is less than 0.1ms for better CV sampling
So, the resistor can be adjusted based on the power loss and the acceptable clamp voltage in practical
application.
H. Design the Output Filters
The RMS current of the output capacitor can be obtained as:
Icap = Is _ rms 2 − Io 2
(53)
Where Is_rms is the secondary RMS current.
The RMS current should be smaller than the RMS current specification of the capacitor.
The voltage ripple on the output cap can be estimate by:
ΔVripple =
Io ⋅ (Tp _ on + Tw )
Cout
+ (Ipks − Io ) ⋅ RESR
(54)
Where Ipks is the secondary side peak current; RESR is the ESR of the output capacitor; Cout is the output
filter capacitor.
In practical application, we should choose the output filter capacitor with sufficiently low ESR to meet
the output voltage ripple requirement without adding an extra LC post filter. Another advantage by using
the low ESR capacitor is more precise for the output voltage sampling at auxiliary winding.
Sometimes it is impossible to meet the ripple specification with a single electrolytic capacitor due to the
high ESR and the parasitic inductance. Then, additional extra ceramic capacitor paralleled with the
electrolytic capacitor or LCL filter can be used to provide a low impendence current path for high
frequency current ripple.
I. Key points for system operation
In order to better performance and system operation, several key points need to be attention.
(1), Output capacitor
It’s better to use the low ESR or very low ESR output capacitor for better precision of output voltage.
The ripple will be lower and the efficiency will be little higher than non-low ESR output capacitor
adoption. The ESR of output capacitor lower than 100mΩ is recommended.
(2), Secondary side diode
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
19
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
The Schottky diode will be recommended because of the fast switch rate and low forward drop for
better high/low temperature CV regulation and efficiency.
(3), Leakage inductance of transformer
The leakage inductance of transformer should be as smaller as possible. Leakage inductance will affect
the sampling point, decrease the efficiency and reduce the output current constant precision. So,
optimize the transformer structure to improve the coupling of primary side and secondary side. It is
better that the leakage inductance is less than 5% inductance.
(4), RCD snubber
Because of the leakage inductance of transformer always exists which will induce the drain voltage
ringing, the damping resistor around 200Ω to 500Ωin series with the clamp diode is suggested to
restrain the drain voltage ringing which will affect the sampling point, reduce the output voltage
regulation and worsen the ripple. Figure 13 shows the compare result with the damping resistor.
(a) Schematic with Damping Resistor
(b) Waveforms Compare with the Damping Resistor
(CH1: VDS; CH2: VFB)
Figure 13-Damping Resistor
AN062 Rev. 1.0
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
20
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
(5), Divided resistor
The divided resistor is recommended to select from 10kΩ to 100kΩ to avoid the FB pin disturbed by
noise. About 1kΩ to 2kΩ resistor can be added between the divided resistor and the FB pin usually to
restrain the noise disturbance caused by layout or component usually which is shown as Figure 14.
MP020-5
VCC
Drain
CP
GND
FB
Figure 14-FB Pin in series with one resistor
(6), Maximum switching frequency
The maximum switching frequency is recommended lower than 75kHz because of the 3.5us sampling
time tolerance and inductance tolerance. So considering the parameter tolerance of the chip and
application in high or low temperature operation, the secondary side diode conduction time should be
longer than 5.4µs normally which function can be expressed as follow.
Tons = Ipk ⋅
Ns ⋅ L m
> 5.4us
Np ⋅ (Vo + Vd )
(54)
(7), Dummy load
When system operates in no load and no dummy load is used in circuit, the output voltage will rise
higher than normal operation because of the minimum switching frequency limitation. One dummy load
is required to use in application for good load regulation. Increasing the dummy load will deteriorate the
efficiency and no load consumption, so the dummy load is tradeoff with the efficiency and load
regulation. Normally, around 10mW dummy load is enough for good load regulation and it also satisfies
the 30mW requirement.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
21
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
4. DESIGN SUMMARY
•
A detailed reference design of primary side regulator with MP020-5 and BOM are shown in Figure15 and Table 2. The input voltage is 85Vac to265Vac and the output is 5V/1A.
•
By sensing the voltage on auxiliary winding to achieve protection function. When output voltage is
too high which make the voltage on auxiliary winding trigger the OVP threshold of FB pin. The
auxiliary winding is used for powering the regulator and detecting the Vds to ensure DCM and OCkP.
•
The transformer’s turns ratio is 127:18:4:4(Np:Np_au:Nsec1:Nsec2) and the primary inductance is
1.6mH. The transformer specification is shown as Figure-16.
N
L
Figure15- Schematic with MP020-5
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
22
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Table 2: Bill of materials
Qty
Ref
Value
Description
Manufacture
Package
Part Number
1
1
C1
C2
4.7μF
10μF
Nichicon
Ltec
DIP
DIP
UVY2G4R7MPD 10*12.5
TY Series 10*12.5
1
C3
1nF
Murata
1206
GRM31A7U2J102JW31D
2
C4,C5
1μF
TDK
0603
C1608X5R1E105K
1
C6
22μF
Jianghai
DIP
CD281L-50V22
1
C7
1.2nF
muRata
0603
GRM188R72A122KA01D
2
C8,C9
330μF
Jianghai
DIP
HCN-10V330
1
C10
1μF
Murata
0603
GRM188R71A105KA61D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CR1
D1
D2
D3
FR1
L1
R1
R2
R3
R4
R5
R6
R7
R8
MB6F
FR107
BAV21W
B560C
10Ω
1000uH
10kΩ
200Ω
150kΩ
10Ω
27kΩ
13.3kΩ
20Ω
2.2kΩ
Diodes
Diodes
Diodes
Diodes
Yageo
Wurth
Yageo
Yageo
Yageo
Yageo
Yageo
Yageo
Yageo
Yageo
SOP-4
DO-41
SOD-123
SMC
DIP
DIP
0805
0805
1206
1206
0603
0603
1206
0603
1
T1
1
U1
Capacitor; 400V; 20%
Capacitor; 400V; 20%
Ceramic Capacitor;
630V; X7R
Ceramic Capacitor; 25V;
X5R
Electrolytic Capacitor;
50V;
Ceramic Capacitor;
100V; X7R
Electrolytic Capacitor;
10V;
Ceramic Capacitor;
10V; X7R
Diode; 600V; 0.5A
Diode; 1000V; 1A
Diode; 200V; 0.2A;
Schottky Diode; 60V; 5A;
Fusible Resistor,1W, 1%
Inductor;1mH,6Ω,0.25A
Film Resistor; 5%
Film Resistor; 5%;
Film Resistor; 5%;
Film Resistor; 5%;
Film Resistor; 1%;
Film Resistor; 1%
Film Resistor; 5%;
Film Resistor; 5%;
Transformer;1.6mH;
Np:Np_au:Nsec1:Nsec2
=127:18:4:4
Primary side regulator
AN062 Rev. 1.2
12/30/2013
MB6F
FR107
BAV21W-7-F
B560C
FKN1WSJT-52-10R
7447462102
RC0805JR-0710KL
RC0805JR-07200RL
RC1206JR-07150KL
RC1206JR-0710RL
RC0603FR-0727KL
RC0603FR-0713K3L
RC1206JR-0720RL
RC0603JR-072K2L
EE16
MPS
SOIC8-7A
MP020-5
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
23
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
10
1
7
Np
3
4
Nsec1 Nsec2
Np_a u
9
5
6
PRI
SEC
Core is connected to Pin 4 by
wire
WINDING START
TEFLON TUBE
(a) Electrical Diagram
(b) Winding Diagram
Figure 16- Transformer Specification
5. EXPERIMENTAL VERIFICATION
A prototype of primary side control adopting MP020-5 with the parameters given above has been built
and tested (Input:85Vac~265Vac; Output:5V/1A). All the components in the circuit are as the same as
that shown in Figure-15.
The operation waveforms are described as follows.
Figure 17 shows the startup waveform. When the VCC is charged to about 17.3V by internal high
voltage current source, the converter starts to work.
Figure 18 shows the output voltage sampling signal. The sampling point is about 4V during sampling
time after the switch turns off.
Figure 19 shows the OVP function of MP020-5. When the FB pin senses the voltage higher than 6.35V,
the MP020-5 will immediately shuts off the internal driving signals logic block and enter hiccup mode
and it returns to normal operation when the fault has been removed.
Figure 20 shows the dynamic response with VOUT is monitored at the end of board and it can meet the
requirement of “USB Battery Charging 1.2 Compliance Plan”.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
24
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 21 shows the CV/CC characteristic. From the curve, it can achieve accurate voltage regulation
with error about +/- 5%. And it also has tight output current regulation with error +/-5%.
Figure 22 shows the measured efficiency. The average efficiency is about 76.56% with 230Vac input,
75.16% with 115Vac input.
Table 3 shows the no load power consumption and it is less than 30mW.
Figure 23 shows the test result of audible noise with the board enclosed into case and the noise probe
keep 5cm distance to the case. Normally, human ear is insensitive with audible noise below 25dB.
Figure 24 shows the conducted EMI with the output connected to ground.
Figure 17- Startup Waveform (220Vac)
(CH1: VDS; CH2: VCC)
Figure 18- Switch Drain-Source Voltage and FB pin Sampling Signal (220Vac)
(CH1:VDS; CH2:VFB)
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
25
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Figure 19- OVP Function (220Vac)
(CH1: VDS; CH2: VCC; CH3: VFB)
(a) IOUT: 0A~0.1A
(b) IOUT: 0.1A~0.5A
Figure 20- Load Response
Frequency: 25Hz; Duty-cycle: 50%; Slew rate: 0.1A/μs
(CH2: VOUT; CH4: IOUT)
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
26
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
CV/CC Characteristic
6
-10℃_265Vac
-10℃_230Vac
-10℃_115Vac
-10℃_85Vac
28℃_265Vac
28℃_230Vac
28℃_115Vac
28℃_85Vac
50℃_265Vac
50℃_230Vac
50℃_115Vac
50℃_85Vac
5
Vo(V)
4
3
2
1
0
0
0.2
0.4
0.6
Io(A)
0.8
1
1.2
Figure 21- CV/CC Characteristic
Efficiency
0.79
0.77
Efficiency(%)
0.75
0.73
0.71
0.69
230Vac
0.67
115Vac
0.65
0
0.2
0.4
0.6
Io(A)
0.8
1
1.2
Figure 22- Efficiency of the system
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
27
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
Table 3: No Load Power Consumption
Input Voltage (Vac)
85
115
220
265
Input Power (mW)
21.53
22.4
23.81
26.51
Audible noise
30
29
28
Noise(dB)
27
26
25
24
23
22
21
20
0
50
100
150
200
250
Io(mA)
300
350
400
450
Figure 23- Audible Noise
(5cm distance and enclosed into case)
Att 10 dB
dBµV
120
RBW
9 kHz
MT
1 s
PREAMP OFF
1 MHz
Att 10 dB
dBµV
10 MHz
120
1 MHz
RBW
9 kHz
MT
1 s
PREAMP OFF
10 MHz
110
110
SGL
SGL
1 PK
CLRWR
2 AV
CLRWR
1 PK
CLRWR
100
90
TDS
2 AV
CLRWR
100
90
TDS
80
80
70
70
EN55022Q
EN55022Q
60
60
EN55022A
6DB
EN55022A
50
50
40
40
30
30
20
20
10
10
6DB
0
0
150 kHz
30 MHz
150 kHz
(a) Live wire
30 MHz
(b) Neutral wire
Figure 24- Conducted EMI
(output connected to ground)
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
28
AN062-OFFLINE PRIMARY-SIDE REGULATOR WITH CV/CC CONTROL AND 700V FET
6. REFERENCES:
[1],Lloyd H. Dixon, “Magnetics Design for Switching Power Supplies”, in Unitrode Magnetics Design
Handbook, 1990.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
AN062 Rev. 1.2
12/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
29