SC4150 Negative Voltage Hot Swap Controller POWER MANAGEMENT Description Features The SC4150 is a negative voltage hotswap controller that allows the insertion of line cards into a live backplane. Programmable slew of the inrush current when The inrush current is programmable and closed loop operation limits the maximum current even under short circuit conditions. A built in timing circuit prevents false shutdown. The signal from the drain voltage is fed to the timer, providing safety for the MOSFET when in linear mode. The SC4150 latches off under abnormal condition and attempts to restart after a time out period. The device comes in two options, PWRGD (SC4150H) and PWRGD (SC4150L). These signals can be directly used to enable power modules. used for hot insertion in the negative 24V and 48V backplane Closed loop operation limits the maximum current even in short circuit condition Built in timer prevents false shutdown, when the closed loop operation limits the current. Sensing the drain voltage allows for immediate shutdown in short circuit condition, where current spikes and noise is ignored. Power good signal Input UVLO and OVLO sensing SO-8 package Applications Central office switching -48V Distributed power systems Power supply hotswap & inrush control Typical Application Circuit GND C1 0.1 U1 SC4150 PWRGD/PWRGD 1 PWRGD /PWRGD VCC 8 VEE Vee GND(remote) 2 R1 562k OV DRAIN 7 R6 18k 3 R2 9.31k 4 UV GATE VEE SENSE 6 C4 3.3nF C5 150 5 R5 10 R3 10.2k C2 0.001 C3 0.33 R4 0.01 Q1 -- 48V Figure 1 Revision: April 14, 2004 1 www.semtech.com SC4150 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units V CC -0.3 to 100 V DRAIN, PWRGD/ PWRGD -0.3 to 100 V SENSE, GATE -0.3 to 20 V UV, OV -0.3 to 60 V Supply Voltage Thermal Resistance Junction to Ambient θJ A 163 °C Thermal Resistance Junction to Case θJ C 38.8 °C Operating Junction Temperature Range TJ -40 to 125 °C Storage Temperature Range TSTG -65 to 150 °C Lead Temperature (Soldering) 10 sec TLEAD 300 °C Electrical Characteristics Unless specified: TA = 25°C, VCC = 48V, VEE = 0V. Values in bold apply over full operating temperature range. Parameter Symbol Test Conditions Min Typ Max Units 80 V 4 7 mA 60 70 mV DC Characteristics Supply Operating Range V CC Supply Current ICC UV = 3V, 0V = VEE, SENSE = VEE Circuit Breaker Trip Voltage V CB VCB = (VSENSE - VEE) Gate Pin Pull-up Current IPU Gate drive ON, VGATE = VEE -50 µA Gate Pin Pull-down Current IPD Any fault condition 40 mA Sense Pin Current ISENSE VSENSE = 50mV -0.05 µA External Gate Drive ∆VGATE (VGATE -VEE), 20V < VDD ≤ 80V 10 50 9 (VGATE -VEE), 10V ≤ VDD ≤ 20V 13 16 V 8 UV Pin High Threshold Voltage VUVH UV Low to High transition 1.241 1.273 1.305 V UV Pin Low Threshold Voltage VUVL UV High to Low transition 1.192 1.223 1.253 V UV Pin Hystersis VUVHY 50 mV -0.1 µA UV Pin Input Current IINUV VUV = VEE OV Pin High Threshold Voltage VOVH OV Low to High transition 1.192 1.223 1.253 V OV Pin Low Threshold Voltage VOVL OV High to Low transition 1.153 1.188 1.223 V OV Pin Hystersis VOVHY OV Pin Input Current 2004 Semtech Corp. VOV ≥ 1.5V IINOV 2 35 mV -0.05 µA www.semtech.com SC4150 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, VCC = 48V, VEE = 0V. Values in bold apply over full operating temperature range. Parameter Power Good Threshold Symbol Test Conditions Min Typ Max Units V PG VDRAIN - VEE, High to Low transition 1.5 1.75 2.0 V 0.4 V Power Good Threshold Hysteresis VPGHY Drain Input Bias Current IDRAIN VDRAIN = 48V 15 Output Low Voltage VOL SC4150H, VOL = PWRGD - VDRAIN @ VDRAIN = 5V, IO = 1mA 1 V SC4150L, VOL = PWRGD - VEE @ VDRAIN = 1V, IO = 1mA 1 V SC4150H, VDRAIN -VEE = 1V, VPWRGD = 80V 1.0 10 µA SC4150L, VDRAIN -VEE = 5V 1.0 10 µA Output Leakage IOH 50 µA AC Characteristics OV High to Gate Low tPHLOV 1.7 µs UV Low to Gate Low tPHLUV 1.5 µs OV Low to Gate High tPLHOV 5.5 µs UV Low to Gate High tPLHUV 6.5 µs tPHLSENSE 3 µs SENSE High to Gate Low DRAIN Low to PWRGD Low DRAIN Low to (PWRGD - DRAIN) High tPHLPG DRAIN High to PWRGD High DRAIN High to (PWRGD - DRAIN) Low tPLHPG Gate ON Time - Time Delay tON_1 Gate ON Time - Time Delay Gate OFF Time 0.5 µs 0.5 µs VDRAIN > 8V, after short circuit 5 µs tON_2 VDRAIN < 7V, after short circuit 250 µs tOFF SC4150, After short, prior to retry 100 ms SC4150-4, After short, prior to retry 400 Note: (1) This device is ESD sensitive. Use of standard ESD handling precaution is required. 2004 Semtech Corp. 3 www.semtech.com SC4150 POWER MANAGEMENT Pin Configuration Ordering Information Part Number(1)(2)(3) TOP VIEW SC4150HISTRT SC4150LISTRT PWRGD/PWRGD 1 8 VCC SC4150HIS-4TRT OV 2 7 DRAIN SC4150LIS-4TRT UV 3 6 GATE VEE 4 5 SENSE P ackag e SO-8 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Device marking: SC4150H, SC4150L - 100ms 4150H-4, 4150L-4 - 400ms (3) Lead free product. (SO-8) Pin Descriptions Pin Pin Name 1 PWRGD/PWRGD Power Good output pin. This pin will toggle when VDRAIN is within VPG of VEE. This pin can be connected directly to the enable pin of a power module, 0.1µF to VEE is optional. 2 OV Analog Overvoltage input. When OV is pulled above 1.223V threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.188V high to low threshold. 3 UV Analog Undervoltage input. When UV is pulled below the 1.223V threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.273 threshold. 4 VEE 5 SENSE Circuit breaker sense pin. With a sense resistor placed in the supply path between VEE and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds 60mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, VEE and SENSE can be shorted together. 6 GATE Gate drive output for external n-channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, t he OV pin is low and (VSENSE - VEE) < 60mV. The GATE pin is pulled high by a 50µA current source and pulled low with a 40mA current source. 7 DRAIN Analog Drain sense input. Connect this pin to the drain of the external N-channel FET and the V(-) pin of the power module. When the DRAIN pin is below VPG, the PWRGD or PWRGD pin will toggle. 8 VC C 2004 Semtech Corp. Pin Function Negative supply voltage input. Connect to the lower potential of the power supply. Positive supply voltage input. Connect this pin to the higher potential of the power supply input and the V(+) pin of the power module. 4 www.semtech.com SC4150 POWER MANAGEMENT Block Diagram Active High PWRGD Vcc PWRGD 12.5V Reg 1.223V 50uA UV _ + _ Timer OV + _ +7V + _ + Delay 1.75V _ 60mV + Vee SENSE GATE DRAIN Active Low PWRGD Vcc PWRGD 12.5V Reg 1.223V 50uA UV _ + _ Timer OV + _ +7V + Delay _ _ 60mV Vee 2004 Semtech Corp. + SENSE + 1.75V GATE DRAIN 5 www.semtech.com SC4150 POWER MANAGEMENT Applications Information Insertion of a power circuit board into a live backplane would draw enormous inrush currents. This is mostly due to the charging of the bulk electrolytic capacitors at the input of the power module being plugged in. Resistors R1, R2 and R3 make up a voltage divider to set the Under-Voltage (UV) and Over-Voltage (OV) trip points. When the input power supply ramps up the UV trips at 1.273V and OV trips at 1.223V; during the ramp down transition the UV trips at 1.223V and OV trips at 1.198V. The transient currents would send glitches all over the power system and could cause corruption of the signals and even a power down if the source isn’t able to handle these high surges. The 50mV hysteresis for UV and 25mV hysteresis for OV provide the necessary guard-bands to prevent false tripping during power up and power down conditions. This section describes the components selection needed for a typical application utilizing the SC4150. Let’s assume the following requirements for a representative system: As an additional noise killing and stabilizing measure, the capacitor C1 should be placed at the OV terminal with the value in range from 1,000 to 10,000pF. Input voltage range: 36V to 72V Nominal current: 2A typ. For the UV=38V and OV=70V the values of the resistor can be calculated as follows: Over-current condition: 5A Vuv = 1.273V · (R1+R2+R3) ÷ (R2+R3) Bulk capacitance: Cload = 150µF Vov = 1.223V · (R1+R2+R3) ÷ R3 The schematic in Figure 2 combines internal function blocks along with the external components of the application circuit. +48V Vcc PWRGD 12.5V Reg 1.223V R1 50uA UV _ + R2 _ Timer OV + _ +7V + C1 R3 Delay _ _ 60mV Vee + + 1.75V SENSE GATE DRAIN C3 R5 Cload 150uF R6 C2 -48V Q1 R4 Figure 2 2004 Semtech Corp. 6 www.semtech.com SC4150 POWER MANAGEMENT Applications Information (Cont.) With the input bias current of the UV and OV comparators in the range of 20-30nA, let’s choose the R1 to be 562kΩ. This yields the values of R2=9.31kΩ and R3 = The inrush can be calculated using the following equation: IMAX = (50µA • CLOAD) / C3 10.2kΩ. With these values the accuracy is about 1% which is quite acceptable for those functions. Resistor R4 sets the over-current trip. To choose R4, the user must determine the level of the current where it should trip. As a rule of thumb, the over-current is set to be 200-300% of the nominal value. In our case, we assumed this value to be 5A. With the values shown in the schematic the actual inruch current will be about 2A, which is within the limits we have chosen. Resistor R5 will produce a time constant which prevents Q1 from turning on when power is initially applied and the circuit is not ready to actively pull the gate low. It’s value is not critical and 18k ensures the adequate delay. Considering the minimum trip voltage is 50mV the value of R4 is 50mV ÷ 5A = 10 mΩ. The value of C2 is chosen to prevent false turn-on of the FET due to the current flowing via C3 into the gate of the FET when the circuit initially connects to the power source. Capacitors C2 and C3 form a divider from Vin to GND. C2 must keep the initial voltage at the gate below Vth minimum. The tolerance of this resistor is usually price driven and 5% is an adequate range of accuracy. The actual position and layout of the circuitry around the sense resistor R4 is critical to avoid a false over-current tripping. The trace routing between R4 and SC4150 should be as short as possible and wide enough to handle the maximum current with zero current in the sense lines – ideally “Kelvin” like. Additionally, there is a shor t delay circuit at the comparator to filter out unwanted noise and otherwise induced transients. For the typical FET, this threshold is around 1V to 2V, therefore C2 = 100 • C3 will keep gate voltage at 0.7V, even at the ”worst” case of Vin = 70V. The choice of the Q1 is quite straightforward and is guided mostly by thermal considerations due to the power dissipation in the steady state. For instance, in our case, the nominal current is 2A, the power dissipation due to the conducting losses will be Inrush Current is being controlled by the R5C3 network and swamping capacitor C2. Pdis = Inom² • Rds_on. When a board is plugged into a live backplane, the input bulk capacitance of the board’s power supply produces large current transients due to the rush of the currents charging those capacitors. The main feature of the SC4150 is to provide an orderly and well-controlled inrush current. The MOSFET should be able to withstand Vdss ≥ 100V with continuous drain current Id ≥ 6A. Device SUD06N10 or similar fits this application. It has an Rds_on = 0.2Ω, and will dissipate Pdis = 2² • 0.2 = 0.8W, which can be handled by this DPAK device. Since the minimum trip voltage is 50mV, let’s choose the inrush current to be 3A. If there is a consideration of reducing the temperature of the MOSFET then the lower Rds_on device should be chosen or a different style (D2PAK) which has lower Junction-to-Ambient thermal characteristics. Imax = Cload · ∆Vmax /dt dt = Cload · ∆Vmax /Imax = 150µF · 70V / 3A = 3.5ms The R6 has a function of dumping high frequency oscillations. The value of it is not critical and can be in the range of 5Ω to 20Ω. This would be the minimum time for the gate voltage plateau during which the Vdd linearly decreases maintaining 3A charge current of the Cload. 2004 Semtech Corp. 7 www.semtech.com SC4150 POWER MANAGEMENT Typical Characteristics Below are the snap-shots taken at start-up with different loading conditions and during the application of the overcurrent at the output of the circuit. For all figures, Ch1: VDRAIN; Ch2: VGATE; Ch3: PWRGD; Ch4: VR4 (Input current) Figure 3. Start-up with no load. Figure 4. Start-up in over load. Figure 5. Start-up with 1Amp load. Figure 6. From 3A load into “short circuit”. 2004 Semtech Corp. 8 www.semtech.com SC4150 POWER MANAGEMENT Typical Characteristics (Cont.) The following set of snapshots demonstrates effectiveness of SC4250 circuit in the case where connection to the live back plane is very “bouncy”, which is usually the situation with manual replacements of the power cards. For all figures, Ch1: VDRAIN; Ch2: VGATE; Ch3: PWRGD (referenced to VDRAIN); Ch4: VR4 (Input current) Figure 7. Short circuit hiccup. Figure 8. Inrush limit. Figure 9. Inrush limit. Figure 10. Inrush limit. 2004 Semtech Corp. 9 www.semtech.com SC4150 POWER MANAGEMENT Evaluation Board Schematic R7 (opt) GND Copt 0.1 U1 SC4150H/L GND(remote) 1 PWRGD/PWRGD VCC 8 C1 0.1 ON/OFF 2 R1 562k DRAIN 7 +Vin R6 18k 3 R2 9.31k R3 10.2k OV 4 UV GATE VEE SENSE 6 C4 3.3nF C5 150 C6(opt) 0.1 +Vout POWER MODULE 5 -Vin -Vout R5 10 C2(opt) 0.01 R4 0.01 C3 0.33 -- 48V Q1 IRF1310 Evaluation Board 2004 Semtech Corp. 10 www.semtech.com SC4150 POWER MANAGEMENT Evaluation Board - Bill of Materials R ef Qty 1 1 C1 0.1/100V Ceramic cap 1210 2 1 C2 (opt.) 0.01 Ceramic cap 0805 3 1 C3 0.33 Ceramic cap 1206S 4 1 C4 0.0033/100V Ceramic cap 0805 5 1 C5 150/80V Aluminum cap CAP-AL-H 6 1 C6 (opt.) 0.1/100V Ceramic cap 1210 7 1 Q1 IRF1310 MOSFET D2PAK 8 1 R1 562k Resistor 0805 9 1 R2 9.31k Resistor 0805 10 1 R3 10.2k Resistor 0805 11 1 R4 0.01 Resistor 2010C S 12 1 R5 10 Resistor 0805 13 1 R6 18k Resistor 0805 14 1 R7 5.1k Resistor 1206S 15 1 U1 S C 4150 Semtech IC SO-8 2004 Semtech Corp. Designator Value Description 11 Footprint www.semtech.com SC4150 POWER MANAGEMENT Outline Drawing - SO-8 JEDEC REF: MS-012AA Minimum Land Pattern - SO-8 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 12 www.semtech.com