SC4250 Datasheet

SC4250
Negative Voltage
Hot Swap Controller
POWER MANAGEMENT
Description
Features
The SC4250 is a negative voltage hotswap controller
that allows the insertion of line cards into a live backplane.
u Programmable slew of the inrush current when
The inrush current is programmable, and the closed loop
operation limits the maximum current even under short
circuit conditions. A built-in timing circuit prevents false
shutdown. The signal from the drain voltage is fed to the
timer, providing safety for the MOSFET when in linear
mode. The SC4250 latches off under abnormal conditions The power has to be recycled in order to resume
operation.
u
used for hot insertion in the negative 24V and 48V
backplane
Closed loop operation limits the maximum current
even in short circuit condition
Built in timer prevents false shutdown when the
closed loop operation limits the current
Sensing the drain voltage allows for immediate
shutdown in short circuit conditions where current
spikes and noise are ignored
Power good signal
Input UVLO and OVLO sensing
Circuit breaker and retry
SO-8 package
u
u
u
u
u
u
The device comes in two options, PWRGD (SC4250H)
and PWRGD (SC4250L). These high or low signals can
be directly used to enable power modules.
Applications
u Central office switching
u -48V Distributed power systems
u Power supply hotswap & inrush control
Typical Application Circuit
GND
GND
C1
0 .1
U1
SC 4 2 5 0
PW R GD/ PW R GD
1
PWRGD /PWRGD
VCC
8
Vee
VEE
GND(r em ote)
2
R1
562k
OV
DRAIN
7
R6
18k
3
R2
9 .3 1 k
4
UV
GATE
VEE
SENSE
C4
3 .3 nF
C5
150
6
5
R5
10
R3
1 0 .2 k
C2
0 .0 0 1
C3
0 .3 3
R4
0 .0 1
-- 4 8 V
Q1
-- 4 8 V
Figure 1
Revision 2.0
1
SC4250
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
VCC
-0.3 to 100
V
DRAIN, PWRGD/ PWRGD
-0.3 to 100
V
SENSE, GATE
-0.3 to 20
V
UV, OV
-0.3 to 60
V
Supply Voltage
Thermal Resistance Junction to Ambient
θJA
168
°C
Thermal Resistance Junction to Case
θJC
38.8
°C
Operating Junction Temperature Range
TJ
-40 to 125
°C
Storage Temperature Range
TSTG
-65 to 150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
300
°C
Electrical Characteristics
Unless specified: TA = 25°C, VCC = 48V, VEE = 0V.
Values in bold apply over full operating temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
80
V
3
5
mA
60
70
mV
DC Characteristics
Supply Operating Range
V CC
Supply Current
ICC
UV = 3V, 0V = VEE, SENSE = VEE
Circuit Breaker Trip Voltage
VCB
VCB = (VSENSE - VEE)
Gate Pin Pull-up Current
IPU
Gate drive ON, VGATE = VEE
-50
µA
Gate Pin Pull-down Current
IPD
Any fault condition
40
mA
Sense Pin Current
ISENSE
VSENSE = 50mV
-0.05
µA
External Gate Drive
∆VGATE
(VGATE -VEE), 20V < VDD ≤ 80V
10
50
9
(VGATE -VEE), 10V ≤ VDD ≤ 20V
13
16
V
8
UV Pin High Threshold Voltage
VUVH
UV Low to High transition
1.241
1.273
1.305
V
UV Pin Low Threshold Voltage
VUVL
UV High to Low transition
1.192
1.223
1.253
V
UV Pin Hystersis
VUVHY
50
mV
-0.1
µA
UV Pin Input Current
IINUV
VUV = VEE
OV Pin High Threshold Voltage
VOVH
OV Low to High transition
1.192
1.223
1.253
V
OV Pin Low Threshold Voltage
VOVL
OV High to Low transition
1.153
1.188
1.223
V
OV Pin Hystersis
VOVHY
OV Pin Input Current
IINOV
VOV ≥ 1.5V
35
mV
-0.05
µA
2
SC4250
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: TA = 25°C, VCC = 48V, VEE = 0V.
Values in bold apply over full operating temperature range.
Parameter
Power Good Threshold
Symbol
Test Conditions
Min
Typ
Max
Units
V PG
VDRAIN - VEE, High to Low transition
1.5
1.75
2.0
V
Power Good Threshold Hysteresis
VPGHY
Drain Input Bias Current
IDRAIN
VDRAIN = 48V
15
Output Low Voltage
VOL
SC4250H, VOL = PWRGD - VDRAIN
@ VDRAIN = 5V, IO = 1mA
1
V
SC4250L, VOL = PWRGD - VEE
@ VDRAIN = 1V, IO = 1mA
1
V
SC4250H, VDRAIN -VEE = 1V, VPWRGD = 80V
1.0
10
µA
SC4250L, VDRAIN -VEE = 5V
1.0
10
µA
Output Leakage
IOH
0.4
V
50
µA
AC Characteristics
OV High to Gate Low
tPHLOV
1.7
µs
UV Low to Gate Low
tPHLUV
1.5
µs
OV Low to Gate High
tPLHOV
5.5
µs
UV Low to Gate High
tPLHUV
6.5
µs
tPHLSENSE
3
µs
SENSE High to Gate Low
DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
tPHLPG
DRAIN High to PWRGD High
DRAIN High to (PWRGD - DRAIN)
Low
tPLHPG
Gate ON Time - Time Delay
tON_1
Gate ON Time - Time Delay
tON_2
µs
0.5
0.5
µs
VDRAIN > 8V, after short circuit
5
µs
VDRAIN < 7V, after short circuit
250
µs
Note:
(1) This device is ESD sensitive. Use of standard ESD handling precaution is required.
3
SC4250
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number
TOP VIEW
(1)
SC4250HISTR
SC4250HISTRT(2)
PWRGD/PWRGD
1
8
VCC
OV
2
7
DRAIN
UV
3
6
GATE
VEE
4
5
SENSE
(SO-8)
P ackag e
SO-8
SC4250LISTR
SC4250LISTRT(2)
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and RoHS
compliant.
Pin Descriptions
Pin
Pin Name
Pin Function
1
PWRGD/PWRGD
Power Good output pin. This pin will toggle when VDRAIN is within VPG of VEE. This pin can
be connected directly to the enable pin of a power module, 0.1µF to VEE is optional.
2
OV
Analog Overvoltage input. When OV is pulled above the 1.223V threshold, an overvoltage
condition is detected and the GATE pin will be immediately pulled low. The GATE pin will
remain low until OV drops below the 1.188V high to low threshold.
3
UV
Analog Undervoltage input. When UV is pulled below the 1.223V threshold, an
undervoltage condition is detected and the GATE pin will be immediately pulled low. The
GATE pin will remain low until UV rises above the 1.273 threshold. The UV pin is also
used to reset the electronic circuit breaker in the "latch OFF" version. If the UV pin is
cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur.
4
VEE
5
SENSE
Circuit breaker sense pin. With a sense resistor placed in the supply path between VEE
and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds
60mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If
the circuit breaker trip current is set to twice the normal operating current, only 25mV is
dropped across the sense resistor during normal operation. To disable the circuit breaker,
VEE and SENSE can be shorted together.
6
GATE
Gate drive output for external N-channel. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin is low and (VSENSE - VEE) <
60mV. The GATE pin is pulled high by a 50µA current source and pulled low with a 40mA
current source.
7
DRAIN
Analog Drain sense input. Connect this pin to the drain of the external N-channel FET
and the V(-) pin of the power module. When the DRAIN pin is below VPG, the PWRGD or
PWRGD pin will toggle.
8
VC C
Positive supply voltage input. Connect this pin to the higher potential of the power supply
input and the V(+) pin of the power module
Negative supply voltage input. Connect to the lower potential of the power supply.
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SC4250
POWER MANAGEMENT
Block Diagrams
Active High PWRGD
Vcc
PWRGD
12.5V Reg
1.223V
50uA
UV
+
-
OV
+
-
+7V
+
+
-
Delay
1.75V
-
60mV
+
Vee
SENSE
GATE
DRAIN
Active Low PWRGD
PWRGD
Vcc
12.5V Reg
1.223V
50uA
UV
+
-
OV
+
-
+7V
+
+
-
Delay
1.75V
-
Vee
+
60mV
SENSE
GATE
DRAIN
5
SC4250
POWER MANAGEMENT
Applications Information
Resistors R1, R2 and R3 make up a voltage divider to
set the Under-Voltage (UV) and Over-Voltage (OV) trip points.
Insertion of a power circuit board into a live backplane
would draw enormous inrush currents. This is mostly due
to the charging of the bulk electrolytic capacitors at the
input of the power module being plugged in.
When the input power supply ramps up the UV trips at
1.273V and OV trips at 1.223V; during the ramp down
transition the UV trips at 1.223V and OV trips at 1.198V.
The transient currents would send glitches all over the
power system and could cause corruption of the signals
and even a power down if the source isn’t able to handle
these high surges.
The 50mV hysteresis for UV and 25mV hysteresis for OV
provide the necessary guard-bands to prevent false tripping
during power up and power down conditions.
This section describes the components selection needed
for a typical application utilizing the SC4250. Let’s assume
the following requirements for a representative system:
As an additional noise killing and stabilizing measure, the
capacitor C1 should be placed at the OV terminal with
the value in range from 1,000 to 10,000pF.
Input voltage range: 36V to 72V
Nominal current: 2A typ.
For the UV=38V and OV=70V the values of the resistor
can be calculated as follows:
Over-current condition: 5A
Vuv = 1.273V · (R1+R2+R3) ÷ (R2+R3)
Bulk capacitance: Cload = 150µF
Vov = 1.223V · (R1+R2+R3) ÷ R3
The schematic in Figure 2 combines internal function blocks
along with the external components of the application
circuit.
With the input bias current of the UV and OV comparators
in the range of 20-30nA, let’s choose the R1 to be 562kΩ.
This yields the values of R2=9.31kΩ and R3 = 10.2kΩ.
With these values the accuracy is about 1% which is quite
acceptable for those functions.
Resistor R4 sets the over-current trip. To choose R4, the
+48V
Vc c
PW R GD
1 2 .5 V Reg
1 .2 2 3 V
R1
5 0 uA
UV
_
+
R2
_
OV
+
_
+7 V
+
C1
R3
_
60mV
Vee
_
Delay
+
+
1.75V
SENSE
GA TE
C3
R5
DRA IN
Cload
150uF
R6
C2
-48V
R4
Q1
Figure 2
6
SC4250
POWER MANAGEMENT
Applications Information (Cont.)
user must determine the level of the current where it should
trip. As a rule of thumb, the over-current is set to be 200300% of the nominal value. In our case, we assumed this
value to be 5A.
Considering the minimum trip voltage is 50mV the value
of R4 is 50mV ÷ 5A = 10 mΩ.
The tolerance of this resistor is usually price driven and 5%
is an adequate range of accuracy.
The actual position and layout of the circuitry around the
sense resistor R4 is critical to avoid a false over-current
tripping. The trace routing between R4 and SC4250 should
be as short as possible and wide enough to handle the
maximum current with zero current in the sense lines –
ideally “Kelvin” like. Additionally, there is a short delay
circuit at the comparator to filter out unwanted noise and
otherwise induced transients.
Inrush Current is being controlled by the R5C3 network
and swamping capacitor C2.
When a board is plugged into a live backplane, the input
bulk capacitance of the board’s power supply produces
large current transients due to the rush of the currents
charging those capacitors. The main feature of the SC4250
is to provide an orderly and well-controlled inrush current.
Since the minimum trip voltage is 50mV, let’s choose the
inrush current to be 3A.
Imax = Cload · ∆Vmax /dt
dt = Cload · ∆Vmax /Imax = 150µF · 70V / 3A = 3.5ms
This would be the minimum time for the gate voltage
plateau during which the Vdd linearly decreases
maintaining 3A charge current of the Cload.
The inrush can be calculated using the following equation:
IMAX = (50µA • CLOAD) / C3
circuit is not ready to actively pull the gate low. It’s value
is not critical and 18k ensures the adequate delay.
The value of C2 is chosen to prevent false turn-on of the
FET due to the current flowing via C3 into the gate of the
FET when the circuit initially connects to the power source.
Capacitors C2 and C3 form a divider from Vin to GND. C2
must keep the initial voltage at the gate below Vth
minimum.
For the typical FET, this threshold is around 1V to 2V,
therefore C2 = 100 • C3 will keep gate voltage at 0.7V,
even at the ”worst” case of Vin = 70V.
The choice of the Q1 is quite straightforward and is guided
mostly by thermal considerations due to the power
dissipation in the steady state.
For instance, in our case, the nominal current is 2A, the
power dissipation due to the conducting losses will be
Pdis = Inom² • Rds_on.
The MOSFET should be able to withstand Vdss ≥ 100V
with continuous drain current Id ≥ 6A. Device SUD06N10
or similar fits this application. It has an Rds_on = 0.2Ω,
and will dissipate
Pdis = 2² • 0.2 = 0.8W, which can be handled by this
DPAK device.
If there is a consideration of reducing the temperature of
the MOSFET then the lower Rds_on device should be chosen
or a different style (D2PAK) which has lower Junction-toAmbient thermal characteristics.
The R6 has a function of dumping high frequency
oscillations. The value of it is not critical and can be in the
range of 5Ω to 20Ω.
With the values shown in the schematic the actual inrush
current will be about 2A, which is within the limits we have
chosen.
Resistor R5 will produce a time constant which prevents
Q1 from turning on when power is initially applied and the
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SC4250
POWER MANAGEMENT
Typical Characteristics
Below are the snap-shots taken at start-up with different loading conditions and during the application of the overcurrent at the output of the circuit.
For all figures, Ch1: VDRAIN; Ch2: VGATE; Ch3: PWRGD; Ch4: VR4 (Input current)
Figure 3. Start-up with no load.
Figure 4. Start-up with 1A load.
Figure 5. Start-up with “over the limit” load.
Figure 6. Over-current/Short circuit.
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SC4250
POWER MANAGEMENT
Typical Characteristics (Cont.)
The following set of snapshots demonstrates effectiveness of SC4250 circuit in the case where connection to the live
back plane is very “bouncy”, which is usually the situation with manual replacements of the power cards.
For all figures, Ch1: VDRAIN; Ch2: VGATE; Ch3: PWRGD (referenced to VDRAIN); Ch4: VR4 (Input current)
Figure 7. Start-up with no load.
Figure 8. Start-up with 1A load.
Figure 9. Start-up with “over the limit” load.
Figure 10. Over-current/Short circuit.
9
SC4250
POWER MANAGEMENT
Evaluation Board Schematic
R7
(opt)
G ND
Copt
0 .1
U1
S C4 2 50 H / L
G ND (rem ote)
1
PWRGD/PWRGD
VCC
8
C1
0 .1
ON/ OFF
2
R1
5 62 k
OV
DRAIN
7
+Vin
R6
1 8k
3
UV
GATE
VEE
SENSE
C4
3 .3nF
C5
1 50
6
C 6(opt)
+Vout
P OWER
0 .1
MODULE
R2
9 .31 k
R3
1 0.2 k
4
5
-V in
-V out
R5
10
C 2(opt)
0 .01
C3
0 .33
Q1
IR F1 3 10
R4
0 .01
-- 48 V
Figure 11
Evaluation Board
Figure 12
10
SC4250
POWER MANAGEMENT
Evaluation Board - Bill of Materials
R ef
Qty
Designator
Value
Description
Footprint
1
1
C1
0.1/100V
Ceramic cap
1210
2
1
C2 (opt.)
0.01
Ceramic cap
0805
3
1
C3
0.33
Ceramic cap
1206S
4
1
C4
0.0033/100V
Ceramic cap
0805
5
1
C5
150/80V
Aluminum cap
CAP-AL-H
6
1
C6 (opt.)
0.1/100V
Ceramic cap
1210
7
1
Q1
IRF1310
MOSFET
D2PAK
8
1
R1
562k
Resistor
0805
9
1
R2
9.31k
Resistor
0805
10
1
R3
10.2k
Resistor
0805
11
1
R4
0.01
Resistor
2010C S
12
1
R5
10
Resistor
0805
13
1
R6
18k
Resistor
0805
14
1
R7
5.1k
Resistor
1206S
15
1
U1
S C 4250
Semtech IC
SO-8
11
SC4250
POWER MANAGEMENT
Outline Drawing - SO-8
A
DIM
D
e
2X E/2
E1 E
1
2
ccc C
2X N/2 TIPS
.053
.069
.004
.010
.049
.065
.012
.020
.007
.010
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
.010
.020
.016 .028 .041
(.041)
8
0
8
.004
.010
.008
A
A1
A2
b
c
D
E1
E
e
h
L
L1
N
01
aaa
bbb
ccc
N
e/2
B
D
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
1.35
1.75
0.10
0.25
1.25
1.65
0.31
0.51
0.17
0.25
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
0.25
0.50
0.40 0.72 1.04
(1.04)
8
0
8
0.10
0.25
0.20
aaa C
h
A2 A
SEATING
PLANE
C
h
A1
bxN
bbb
H
C A-B D
c
GAGE
PLANE
0.25
SEE DETAIL
L
(L1)
A
DETAIL
SIDE VIEW
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MS-012, VARIATION AA.
Minimum Land Pattern - SO-8
X
DIM
(C)
G
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
C
G
P
X
Y
Z
(.205)
.118
.050
.024
.087
.291
(5.20)
3.00
1.27
0.60
2.20
7.40
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
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