AN-595: Understanding Pin Compatibility in the TxDAC® Line of High Speed D/A...

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AN-595
APPLICATION NOTE
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Understanding Pin Compatibility in the TxDAC ® Line of High Speed D/A Converters
by David Carr
INTRODUCTION
The TxDAC product line is comprised of three generations
of high performance, low power CMOS digital-to-analog
converters (DACs). Products are available in pin compatible 8-, 10-, 12-, and 14-bit versions and are specifically
optimized for the transmit signal path of communication
systems. All of the devices share the same interface
options, small outline package, and pinout, providing an
upward or downward component selection path based on
performance, resolution, and cost.
supply requirements, as well as functional options and
bypassing requirements that need to be comprehended
when migrating a design between generations.
FAMILY DESCRIPTIONS
The first family in the TxDAC line was the AD9708/
AD9760/AD9762/AD9764 (AD976x) series. This was the
first CMOS DAC family on the market designed
specifically for communications applications. It offered
flexibility in the allowable supply voltage (2.7 V to 5.5 V),
with better performance than BiCMOS alternatives that
were prevalent at the time.
Pin compatibility to previous generations has been maintained throughout the evolution of the TxDAC product
line (refer to Figures 1–3). There are differences in power
(MSB) DB13 1
28 CLOCK
(MSB) DB13 1
28 CLOCK
28 CLOCK
(MSB) DB13 1
DB12 2
27 DVDD
DB12 2
27 DVDD
DB12 2
27 DVDD
DB11 3
26 DCOM
DB11 3
26 DCOM
DB11 3
26 DCOM
25 NC
DB10 4
25 NC
DB10 4
25 MODE
DB10 4
24 AVDD
DB9 5
23 ICOMP
DB8 6
TOP VIEW 23 RESERVED
DB7 7 (Not to Scale) 22 IOUTA
DB6 8
21 IOUTB
DB6 8
21 IOUTB
DB5 9
20 ACOM
DB5 9
20 ACOM
19 COMP1
DB4 10
19 NC
DB4 10
19 NC
18 FS ADJ
DB3 11
18 FS ADJ
DB3 11
18 FS ADJ
DB2 12
17 REFIO
24 AVDD
DB9 5
23 COMP2
DB8 6
DB6 8
21 IOUTB
DB5 9
20 ACOM
DB4 10
DB3 11
DB9 5
DB8 6
AD9764
TOP VIEW
DB7 7 (Not to Scale) 22 IOUTA
AD9754
TOP VIEW
DB7 7 (Not to Scale) 22 IOUTA
AD9744
24 AVDD
DB2 12
17 REFIO
DB2 12
17 REFIO
DB1 13
16 REFLO
DB1 13
16 REFLO
DB1 13
16 REFLO
(LSB) DB0 14
15 SLEEP
(LSB) DB0 14
15 SLEEP
(LSB) DB0 14
15 SLEEP
NC = NO CONNECT
NC = NO CONNECT
NC = NO CONNECT
Figure 1. AD9764 Pinout
Figure 2. AD9754 Pinout
Figure 3. AD9744 Pinout
TxDAC is a registered trademark of Analog Devices, Inc.
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© Analog Devices, Inc., 2002
Subsequently the AD9750/AD9752/AD9754 family
(AD975x) was introduced, which provided increased
performance over the first generation. The analog supply voltage was restricted (4.5 V to 5.5 V) to achieve the
performance increase. However, the digital supply
maintained the flexibility from the previous generation
to allow for compatibility with numerous logic families.
which was designated as a No Connect (NC) in the earlier devices. This pin has an internal pull-down that
results in the part being placed in the Offset Binary data
mode if left floating. Therefore, it is compatible with
existing AD976x and AD975x designs in which Pin 25 is
unconnected. Table III details the allowable external
connections for the MODE pin and the resultant data format that is selected.
The most recent introduction in the TxDAC line is the
AD9740/AD9742/AD9744 (AD974x series). This family
was designed on an advanced submicron CMOS process
that supports 3.3 V supplies only. The AD974x series
offers the highest performance available in the industrystandard TxDAC pinout.
Table III. MODE Control for AD974x
Power Supply Requirements
Because of the technology advances made in each generation, there are varying requirements for the power
supply voltage. Table I illustrates the requirements for
each generation.
Digital Supply
AD976x
AD975x
AD974x
2.7 V to 5.5 V
4.5 V to 5.5 V
3.0 V to 3.6 V
2.7 V to 5.5 V
2.7 V to 5.5 V
3.0 V to 3.6 V
Table IV. Name and Connection for Pin 19
Table II. Maximum Sample Rate
Maximum fCLOCK
AD976x
AD975x
AD974x
125 MSPS
125 MSPS
165 MSPS
Offset Binary
Offset Binary
Two’s Complement
This pin should be disconnected (floated) on the PCB. It
can also be connected to ground through a capacitor but
should not be connected directly (or resistively) to either
ground or the supply rail. The requirements for these
two pins are detailed in Tables IV and V.
Sample Rate
The AD976x and AD975x families were designed on
a 5 V CMOS process and support a maximum data rate
of 125 MSPS. A more advanced 3 V CMOS process that
supports an update rate of 165 MSPS was used for the
AD974x family. Table II summarizes the supported clock
rate for each family.
Family
Float
DCOM
DVDD
Family
Pin 19 Name
AD976x
AD975x
AD974x
COMP1
NC
NC
Pin 19 Connection
0.1 µF to AVDD
No Internal Connection
No Internal Connection
Table V. Name and Connection for Pin 23
MODE Selection
A MODE pin was added to the AD974x family to allow
either Offset Binary or Two’s Complement data to be
processed. The first two generations supported Offset
Binary only. The MODE function is controlled by Pin 25,
–2–
Family
Pin 23 Name
Pin 23 Connection
AD976x
AD975x
AD974x
COMP2
ICOMP
RESERVED
0.1 µF to ACOM
0.1 µF to ACOM
Float or capacitively
couple to ACOM
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PRINTED IN U.S.A.
Analog Supply
Data Format
COMP1 and COMP2 Pins
The AD976x family contains two internal bias nodes
(COMP1 and COMP2) that must be externally bypassed.
One of the bias pins was eliminated in the AD975x family. Neither of the internal bias points is externally
decoupled in the AD974x family. However, one of the
pins is declared as RESERVED in the AD974x pinout to
support a factory test mode.
Table I. Power Supply Requirements
Family
MODE Pin
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