CYPRESS CY62126EV30

CY62126EV30 MoBL®
1-Mbit (64K x 16) Static RAM
Features
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH).
The input and output pins (IO0 through IO15) are placed in a
high impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE LOW and WE LOW)
• High speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive: –40°C to +125°C
• Wide voltage range: 2.2V–3.6V
• Pin compatible with CY62126DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 4 µA
• Ultra low active power
•
•
•
•
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through
IO15) is written into the location specified on the address pins
(A0 through A15).
— Typical active current: 1.3 mA @ f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description[1]
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64K x 16
RAM Array
IO0–IO7
IO8–IO15
BHE
WE
CE
OE
BLE
A15
A14
A13
A12
A11
COLUMN DECODER
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05486 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2007
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CY62126EV30 MoBL®
Pin Configurations [2]
44-Pin TSOP II
48-Ball VFBGA
Top View
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
IO8
BHE
A3
A4
CE
IO0
B
IO9
IO10
A5
A6
IO1
IO2
C
VSS
IO11
NC
A7
IO3
VCC
D
VCC
IO12
NC
NC
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
Speed
(ns)
Min
Typ[1]
Max
CY62126EV30LL Industrial
2.2
3.0
3.6
CY62126EV30LL Automotive
2.2
3.0
3.6
Operating, ICC (mA)
f = 1 MHz
f = fmax
Standby, ISB2 (µA)
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
45
1.3
2
11
16
1
4
55
1.3
4
11
35
1
30
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05486 Rev. *D
Page 2 of 12
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CY62126EV30 MoBL®
DC Input Voltage[4, 5] ...............−0.3V to 3.6V (VCCmax + 0.3V)
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground
Potential .................................–0.3V to 3.6V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State[4, 5] .................–0.3V to 3.6V (VCCmax + 0.3V)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Device
CY62126EV30LL
Range
Ambient
Temperature
VCC[6]
Industrial
–40°C to +85°C
2.2V to
3.6V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage IOH = –0.1 mA
VOL
Output LOW Voltage
Input HIGH Voltage
VIL
Input LOW
Voltage
Min
Typ[1]
Max
2.0
IOH = –1.0 mA, VCC > 2.70V
VIH
45 ns (Industrial)
55 ns (Automotive)
Min
Typ[1]
Max
2.0
2.4
Unit
V
2.4
V
IOL = 0.1 mA
0.4
0.4
V
IOL = 2.1mA, VCC > 2.70V
0.4
0.4
V
1.8
VCC + 0.3
V
VCC = 2.2V to 2.7V
1.8
VCC + 0.3
VCC = 2.7V to 3.6V
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VCC = 2.2V to 2.7V
–0.3
0.6
–0.3
0.6
V
VCC = 2.7V to 3.6V
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current GND < VI < VCC
–1
+1
–4
+4
µA
IOZ
Output Leakage
Current
–1
+1
–4
+4
µA
ICC
VCC Operating Supply f = fmax = 1/tRC
Current
f = 1 MHz
mA
GND < VO < VCC, Output
Disabled
VCC = VCCmax
IOUT = 0 mA
CMOS levels
11
16
11
35
1.3
2.0
1.3
4.0
ISB1
Automatic CE Power
down Current
—CMOS Inputs
CE > VCC − 0.2V,
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
1
4
1
35
µA
ISB2 [7]
Automatic CE Power
down Current
—CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
1
4
1
30
µA
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05486 Rev. *D
Page 3 of 12
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CY62126EV30 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Test Conditions
VFBGA
Package
TSOP II
Package
Unit
Still Air, soldered on a 4.25 x 1.125 inch,
two-layer printed circuit board
58.85
28.2
°C/W
17.01
3.4
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.2V - 2.7V
2.7V - 3.6V
Unit
R1
16600
1103
Ohms
R2
15400
1554
Ohms
RTH
8000
645
Ohms
VTH
1.2
1.75
Volts
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR[7]
Data Retention Current
tCDR
[8]
tR[9]
Conditions
Min
Typ[1]
Max
1.5
VCC= VDR, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Unit
V
Industrial
3
µA
Automotive
30
µA
Chip Deselect to Data
Retention Time
0
ns
Operation Recovery Time
tRC
ns
Data Retention Waveform
Figure 2. Data Retention Waveform
VCC
VCC(min)
DATA RETENTION MODE
VDR > 1.5V
tCDR
VCC(min)
tR
CE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs.
Document #: 38-05486 Rev. *D
Page 4 of 12
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CY62126EV30 MoBL®
Switching Characteristics
Over the Operating Range [10, 11]
Parameter
45 ns (Industrial)
Description
Min
Max
55 ns (Automotive)
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z [12]
tHZOE
tLZCE
45
OE HIGH to High Z
CE LOW to Low Z
55
45
10
55
10
45
22
5
[12, 13]
10
[12, 13]
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
tDBE
BHE / BLE LOW to Data Valid
tLZBE
BHE / BLE LOW to Low Z
tHZBE
BHE / BLE HIGH to High Z [12, 13]
ns
25
ns
ns
20
18
[12]
55
10
0
ns
ns
5
18
[12]
ns
ns
ns
20
0
ns
ns
45
55
ns
22
25
ns
20
ns
5
5
18
ns
Write Cycle [14]
tWC
Write Cycle Time
45
55
ns
tSCE
CE LOW to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BHE / BLE Pulse Width
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
[12, 13]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z [12]
18
10
20
10
ns
ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
Document #: 38-05486 Rev. *D
Page 5 of 12
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CY62126EV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address transition controlled)[15, 16]
Figure 3. Read Cycle No. 1
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled)[16, 17]
Figure 4. Read Cycle No. 2
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
15. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05486 Rev. *D
Page 6 of 12
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CY62126EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE controlled)[14, 18, 19]
Figure 5. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 20
tHD
DATAIN
tHZOE
Write Cycle No. 2 (CE controlled)[14, 18, 19]
Figure 6. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 20
tHZOE
Notes
18. Data IO is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05486 Rev. *D
Page 7 of 12
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CY62126EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE controlled, OE LOW [19]
Figure 7. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA IO
NOTE 20
tHD
DATAIN
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19]
Figure 8. Write Cycle No. 4
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 20
tSD
tHD
DATAIN
tLZWE
Document #: 38-05486 Rev. *D
Page 8 of 12
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CY62126EV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power Down
Standby (ISB)
X
X
X
H
H
High Z
Output Disabled
Active (ICC)
L
H
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62126EV30LL-45BVXI
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-45ZSXI
51-85087 44-pin Thin Small Outline Package II (Pb-free)
CY62126EV30LL-55BVXE
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-55ZSXE
51-85087 44-pin Thin Small Outline Package II (Pb-free)
Operating
Range
Industrial
Automotive
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05486 Rev. *D
Page 9 of 12
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CY62126EV30 MoBL®
Package Diagrams
Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
Document #: 38-05486 Rev. *D
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 10 of 12
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CY62126EV30 MoBL®
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05486 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62126EV30 MoBL®
Document History Page
Document Title: CY62126EV30 MoBL®, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
202760
See ECN
AJU
New data sheet
*A
300835
See ECN
SYT
Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and
45-ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins
respectively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Changed ISB1, ISB2 (max) from 1 µA to 4 µA
Changed ISB1, ISB2 (Typ) from 0.5 µA to 1 µA
Changed ICCDR (max) from 1.5 µA to 3 µA
Changed the AC Test load Capacitance value from 50 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tLZBE from 6 to 5 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information table.
*C
925501
See ECN
VKN
Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
*D
1045260
See ECN
VKN
Added Automotive information
Updated Ordering Information table
Document #: 38-05486 Rev. *D
Page 12 of 12
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