NB3N200S D

NB3N200S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
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The NB3N200 is a pure 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver. NB3N200S is
TIA/EIA−899 compliant. NB3N200S offers the Type 1 receiver
threshold at 0.0 V.
These devices has a Type−1 receiver that detect the bus state with as
little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. The Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NB3N200S supports Simplex or Half Duplex bus configurations.
1
•
•
•
•
•
NB20x
AYWW
G
NB20x
x
A
Y
WW
G or G
1
= Specific Device Code
= 0, 2, 4, 5
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
• Low−Voltage Differential 30 W to 55 W Line Drivers and Receivers
•
8
SOIC−8
D SUFFIX
CASE 751
Features
•
•
MARKING
DIAGRAM
8
for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC ≤
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• Pb−Free SOIC 8 Package
• These are Pb−Free Devices
Applications
• Low−Power High−Speed Short−Reach Alternative to
•
•
•
•
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Figure 1. Logic Diagrams
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NB3N200S/D
NB3N200S
R
1
8 VCC
RE
2
7 B
DE
3
6 A
D
4
5 GND
SOIC−8
NB3N200S
Figure 2. Pinout Diagrams (Top View)
Table 1. PIN DESCRIPTION SOIC−8
Number
Name
I/O Type
Open Default
Description
1
R
LVCMOS Output
2
RE
LVCMOS Input
High
Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
3
DE
LVCMOS Input
Low
Driver Enable Input Pin (LOW = High Z Output, HIGH = Active)
4
D
LVCMOS Input
5
GND
6
A
M−LVDS Input /
Output
Transceiver Invert Input / Output Pin
7
B
M−LVDS Input /
Output
Transceiver True Input / Output Pin
8
VCC
Receiver Output Pin
Driver Output Pin
Ground Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
Power Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
Table 2. DEVICE FUNCTION TABLE
Inputs
TYPE 1 Receiver (NB3N200)
DRIVER
Output
VID = VA − VB
RE
R
VID w 50 mV
L
H
−50 mV < VID < 50 mV
L
?
VID ≤ −50 mV
L
L
X
H
Z
X
Open
Z
Open
L
?
Input
Enable
Output
D
DE
A/Y
B/Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
Open
Z
Z
X
L
Z
Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
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NB3N200S
Table 3. ATTRIBUTES (Note 1)
Characteristics
Value
Internal Input Pullup Resistor
50 kW
Internal Input Pulldown Resistor
50 kW
ESD
Protection
Human Body Model (JEDEC
Standard 22, Method A114−A)
A, B, Y, Z
All Pins
±6 kV
±2 kV
Machine Model
All Pins
±200 V
Charged –Device Model (JEDEC
Standard 22, Method C101)
All Pins
±1500 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Level 1
UL−94 V−0 @ 0.125 in
28 to 34
Transistor Count
917 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
VCC
Supply Voltage
VIN
Input Voltage
IOUT
Condition 1
Condition 2
Rating
Unit
−0.5 ≤ VCC ≤ 4.0
V
D, DE, RE
−0.5 ≤ VIN ≤ 4.0
V
A, B (200, 204)
−1.8 ≤ VIN ≤ 4.0
A, B (202, 205)
−4.0 ≤ VIN ≤ 6.0
R
Y, Z, A, B
−0.3 ≤ IOUT ≤ 4.0
−1.8 ≤ IOUT ≤ 4.0
V
Output Voltage
TA
Operating Temperature Range, Industrial
−40 to ≤ +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
θJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
190
130
°C/W
°C/W
(Note 3)
SOIC−8
41 to 44
°C/W
265
°C
725
5.8
377
mW
mW/°C
mW
θJC
Thermal Resistance (Junction−to−Case)
Tsol
Wave Solder
PD
Power Dissipation (Continuous)
SOIC−8
TA = 25°C
25°C < TA < 85°C
TA = 85°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (See Notes 4, 5)
Symbol
ICC
VIH
VIL
VBUS
|VID|
Characteristic
Min
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at VCC, RL = 50 W, All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, RL = No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at VCC, RL = 50 W, All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, RL = 50 W, All others open
Input HIGH Voltage
Input LOW Voltage
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
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3
Max
13
1
16
22
4
24
13
Unit
mA
2
GND
−1.4
0.05
DRIVER
Typ
VCC
0.8
3.8
VCC
V
V
V
NB3N200S
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (See Notes 4, 5)
Symbol
Characteristic
Min
Typ
Max
Unit
DRIVER
|VAB| /
|VYZ|
D|VAB| /
D|VYZ|
VOS(SS)
DVOS(SS)
Differential output voltage magnitude (see Figure 4)
480
650
mV
Change in Differential output voltage magnitude between logic states (see Figure 4)
−50
50
mV
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
0.8
−50
1.2
50
V
mV
VOS(PP)
VYOC /
VAOC
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
0
150
2.4
mV
V
VZOC /
VBOC
Maximum steady−state open−circuit output voltage (see Figure 9)
0
2.4
V
VP(H)
VP(L)
IIH
IIL
JIOSJ
IOZ
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) VIH = 2 V
Low−level input current (D, DE) VIL = 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V ≤ (VY or VZ) ≤ 3.8 V, other output at 1.2 V
1.2 VSS
−15
10
10
24
10
V
V
uA
uA
mA
uA
IO(OFF)
Power−off output current (0 V ≤ VCC ≤ 1.5 V)
−1.4 V ≤ (VY or VZ) ≤ 3.8 V, other output at 1.2 V
−10
10
uA
CY / CZ
Output Capacitance VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
−0.2 VSS
0
0
3
CYZ
Differential Output Capacitance VAB = 0.4 sin(30E6pt) V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
CY/Z
Output Capacitance Balance, (CY/CZ)
99
pF
2.5
pF
101
%
RECEIVER
VIT+
Positive−going Differential Input voltage Threshold (See Figure 11 & Table 8)
mV
Type 1
Type 2
VIT−
Negative−going Differential Input voltage Threshold (See Figure 11 & Table 8)
mV
Type 1
Type 2
VHYS
50
150
−50
50
Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
mV
Type 1
Type 2
VOH
VOL
IIH
IIL
IOZ
CA / CB
High−level output voltage (IOH = –8 mA
Low−level output voltage (IOL = 8 mA)
RE High-level input current (VIH = 2 V)
RE Low-level input current (VIL = 0.8 V)
High−impedance state output current (VO = 0 V of 3.6 V)
Input Capacitance VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V using HP4194A
impedance analyzer (or equivalent)
CAB
Differential Input Capacitance VAB = 0.4 sin(30E6πt) V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
CA/B
Input Capacitance Balance, (CA/CB)
25
0
2.4
−10
−10
−10
4
V
V
mA
mA
mA
pF
2.5
pF
101
%
3
99
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0.4
0
0
15
NB3N200S
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (See Notes 4, 5)
Symbol
Characteristic
Typ
(Note
5)
Min
Max
Unit
BUS INPUT AND OUTPUT
IA
Input Current Receiver or Transceiver with Driver Disabled
uA
VA = 3.8 V, VB = 1.2 V
VA = 0.0 V or 2.4 V, VB = 1.2 V
VA = −1.4 V, VB = 1.2 V
IB
IAB
IA(OFF)
IB(OFF)
IAB(OFF)
0
−20
−32
32
20
0
VB = 3.8 V, VA = 1.2 V
VB = 0.0 V or 2.4 V, VA = 1.2 V
VB = −1.4 V, VA = 1.2 V
0
−20
−32
32
20
0
Differential Input Current Receiver or Transceiver with driver disabled (IA−IB)
VA = VB , −1.4 ≤ VA ≤ 3.8 V
−4
4
Input Current Receiver or Transceiver Power Off 0V ≤ VCC ≤ 1.5 and:
VA = 3.8 V, VB = 1.2 V
VA = 0.0 V or 2.4 V, VB = 1.2 V
VA = −1.4 V, VB = 1.2 V
0
−20
−32
32
20
0
Input Current Receiver or Transceiver Power Off 0V ≤ VCC ≤ 1.5 and:
VB = 3.8 V, VA = 1.2 V
VB = 0.0 V or 2.4 V, VA = 1.2 V
VB = −1.4 V, VA = 1.2 V
0
−20
−32
32
20
0
Receiver Input or Transceiver Input/Output Power Off Differential Input Current; (IA−IB)
VA = VB , 0 ≤ VCC ≤ 1.5 V, −1.4 ≤ VA ≤ 3.8 V
−4
4
Input Current Receiver or Transceiver with Driver Disabled
uA
uA
uA
uA
uA
CA
Transceiver Input Capacitance with Driver Disabled VA = 0.4 sin(30E6πt) + 0.5 V using
HP4194A impedance analyzer (or equivalent); VB = 1.2 V
5
pF
CB
Transceiver Input Capacitance with Driver Disabled VB = 0.4 sin(30E6πt) + 0.5 V using
HP4194A impedance analyzer (or equivalent); VA = 1.2 V
5
pF
CAB
Transceiver Differential Input Capacitance with Driver Disabled VA = 0.4 sin(30E6pt) +
0.5 V using HP4194A impedance analyzer (or equivalent);
VB = 1.2 V
CA/B
Transceiver Input Capacitance Balance with Driver Disabled, (CA/CB)
99
3.0
pF
101
%
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. See Figure 3. DC Measurements reference.
5. Typ value at 25°C and 3.3 VCC supply voltage.
Table 6. DRIVER AC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (Note 6)
Symbol
Characteristic
Min
tPLH / tPHL
Propagation Delay (See Figure 7)
tPHZ / tPLZ
Disable Time HIGH or LOW state to High Impedance (See Figure 8)
tPZH / tPZL
Enable Time High Impedance to HIGH or LOW state (See Figure 8)
1.0
tSK(P)
Pulse Skew (|tPLH − tPHL|) (See Figure 7)
tSK(PP)
Device to Device Skew similar path and conditions (See Figure 7)
0
tJIT(PER)
Period Jitter RMS, 100 MHz (Source tr/tf 0.5 ns, 10 and 90 % points, 30k samples. Source jitter de−embedded from Output values ) (See Figure 10)
tJIT(PP)
Peak−to−peak Jitter, 200 Mbps 215−1 PRBS (Source tr/tf 0.5 ns, 10 and 90%
points, 100k samples. Source jitter de−embedded from Output values) (See
Figure 10)
tr / tf
Typ
Differential Output rise and fall times (See Figure 7)
1
Max
Unit
2.4
ns
7
ns
7
ns
150
ps
0.9
ns
3
ps
150
ps
1.6
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Typ value at 25°C and 3.3 VCC supply voltage.
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NB3N200S
Table 7. RECEIVER AC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (Note 7)
Symbol
Characteristic
Min
Typ
Max
Unit
2
4
6
ns
Disable Time HIGH or LOW state to High Impedance (See Figure 13)
10
ns
Enable Time High Impedance to HIGH or LOW state (See Figure 13)
15
ns
tPLH / tPHL
Propagation Delay (See Figure 12)
tPHZ / tPLZ
tPZH / tPZL
tSK(P)
Pulse Skew (|tPLH − tPHL|) (See Figure 12) CL = 5 pF
ps
100
300
Type 1
Type 2
tSK(PP)
Device to Device Skew similar path and conditions (See Figure 12) CL = 5 pF
tJIT(PER)
Period Jitter RMS, 100 MHz (Source: VID = 200 mVpp for 201 and 203, VID =
400 mVpp for 206 and 207, VCM =1 V, tr/tf 0.5 ns, 10 and 90 % points, 30k samples.
Source jitter de−embedded from Output values ) (See Figure 14)
tJIT(PP)
Peak−to−peak Jitter, 200 Mbps 215−1 PRBS (Source tr/tf 0.5 ns, 10% and 90% points,
100k samples. Source jitter de−embedded from Output values) (See Figure 14)
Type 1
Type 2
tr / tf
Differential Output rise and fall times (See Figure 12) CL = 15 pF
7. Typ value at 25°C and 3.3 VCC supply voltage. .
Figure 3. Driver Voltage and Current Definitions
A. All resistors are 1% tolerance.
Figure 4. Differential Output Voltage Test Circuit
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6
4
300
500
1
ns
7
ps
ps
300
450
1
700
800
2.3
ns
NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20% tolerance.
C. R1 and R2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Test Circuit and Definitions for the Driver Common−Mode Output Voltage
Figure 6. Driver Short−Circuit Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 8. Driver Enable and Disable Time Circuit and Definitions
Figure 9. Maximum Steady State Output Voltage
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NB3N200S
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 215−1 PRBS input.
Figure 10. Driver Jitter Measurement Waveforms
Figure 11. Receiver Voltage and Current Definitions
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NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50
±5%. CL is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the
D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 12. Receiver Timing Test Circuit and Waveforms
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NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz, duty cycle = 50
±5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 13. Receiver Enable/Disable Time Test Circuit and Waveforms
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NB3N200S
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 215−1 PRBS input.
Figure 14. Receiver Jitter Measurement Waveforms
Table 8. TYPE−1 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages
Resulting Differential
Input Voltage
Resulting Common−
Mode Input Voltage
VIA
VIB
VID
VIC
Receiver Output
2.400
0.000
2.400
1.200
H
0.000
2.400
–2.400
1.200
L
3.800
3.750
0.050
3.775
H
3.750
3.800
–0.050
3.775
L
–1.350
–1.400
0.050
–1.375
H
–1.400
–1.350
–0.050
–1.375
L
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
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NB3N200S
Figure 15. Equivalent Input and Output Schematic Diagrams
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
Type 2 receivers have their differential input voltage
thresholds offset from zero volts to detect the absence of a
voltage difference. The impact to receiver output by the
offset input can be seen in Table 9 and Figure 16.
The MLVD standard defines a type 1 and type 2 receiver.
Type 1 receivers include no provisions for failsafe and have
their differential input voltage thresholds near zero volts.
Table 9. RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS
Receiver Type
Output Low
Output High
Type 1
–2.4 V ≤ VID ≤ –0.05 V
0.05 V ≤ VID ≤ 2.4 V
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NB3N200S
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
Live Insertion/Glitch−Free Power Up/Down
Figure 17 shows the performance of the receiver output pin,
R (CHANNEL 2), as VCC (CHANNEL 1) is ramped. The
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
operation until VCC has reached a steady state value.
The NB3N200 family of products provides a glitch−free
power up/down feature that prevents the M−LVDS outputs
of the device from turning on during a power up or power
down event. This is especially important in live insertion
applications, when a device is physically connected to an
M−LVDS multipoint bus and VCC is ramping.
While the M−LVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
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NB3N200S
Figure 17. M−LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
Simplex Theory Configurations: Data flow is
unidirectional and Point−to−Point from one Driver to one
Receiver. NB3N200SDG, NB3N202SDG, NB3N204SDG,
and NB3N205SDG devices provide a high signal current
allowing long drive runs and high noise immunity. Single
terminated interconnects yield high amplitude levels.
Parallel terminated interconnects yield typical MLVDS
amplitude levels and minimizes reflections. See Figures 18
and 19. A NB3N200SDG, NB3N202SDG, NB3N204SDG,
and NB3N205SDG can be used as the driver or as a receiver.
Figure 19. Parallel−Terminated Simplex
Figure 18. Point−to−Point
Simplex Single
Termination
Simplex Multidrop Theory Configurations: Data flow is
unidirectional from one Driver with one or more Receivers
and Multiple boards are required. Single terminated
interconnects yield high amplitude levels. Parallel
terminated interconnects yield typical MLVDS amplitude
levels and minimizes reflections. On the Evaluation Test
Board, Headers P1, P2, and P3 may be used as need to
interconnect transceivers to a each other or a bus. See
Figures 20 and 21. A NB3N200SDG, NB3N202SDG,
NB3N204SDG, and NB3N205SDG can be used as the
driver or as a receiver.
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NB3N200S
Figure 20. Multidrop or Distributed Simplex with Single Termination
Figure 21. Multidrop or Distributed Simplex with Double Termination
interconnects yield typical LMVDS amplitude levels and
minimizes reflections. On the Test Board, Headers P1, P2,
and P3 may be used as need to interconnect transceivers to
each other or a bus. See Figure 22. A NB3N202SDG,
NB3N204SDG, and NB3N205SDG can be used as the
driver or as a receiver. Full duplex bus interconnect
configurations are possibe using NB3N202SDG or
NB3N205SDG.
Half
Duplex
Multinode
Multipoint
Theory
Configurations: Data flow is unidirectional and selected
from one of multiple possible Drivers to multiple Receives.
One “Two Node” multipoint connection can be
accomplished with a single evaluation board. More than
Two Nodes requires multiple evaluation test boards. Parallel
terminated interconnects yield typical MLVDS amplitude
levels and minimizes reflections. Parallel terminated
Figure 22. Multinode Multipoint Half Duplex (requires Double Termination)
Figure 23.
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NB3N200S
ORDERING INFORMATION
Receiver
Pin 1 Quadrant
Package
Shipping†
NB3N200SDG
Type 1
Q1
SOIC*8
(Pb−Free)
98 Units / Rail
NB3N200SDR2G
Type 1
Q1
SOIC*8
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N200S
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
SOLDERING FOOTPRINT*
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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