SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES • • • • • • • • • • • • Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates (1) Up to 100 Mbps, Clock Frequencies up to 50 MHz Type-1 Receivers Incorporate 25 mV of Hysteresis (200A, 202A) Type-2 Receivers Provide an Offset(100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (204A, 205A) Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange Power Up/Down Glitch Free Controlled Driver Output Voltage Transition Times for Improved Signal Quality –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V 200-Mbps Devices Available (SN65MLVD201, 203, 206, 207) Bus Pin ESD Protection Exceeds 8 kV Package in 8-Pin SOIC (200A, 204A) and 14-Pin SOIC (202A, 205A) Improved Alternatives to the SN65MLVD200, 202, 204, and 205 APPLICATIONS • • • • • (1) Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485 Backplane or Cabled Multipoint Data and Clock Transmission Cellular Base Stations Central-Office Switches Network Switches and Routers DESCRIPTION The SN65MLVD200A, 202A, 204A, and 205A are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 Ω, and incorporates controlled transition times to allow for stubs off of the backbone transmission line. These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other fault conditions. The SN65MLVD200A, 202A, 204A, and 205A have enhancements over their predecessors. Improved features include better controlled slew rate on the driver output to help minimize reflections while improving overall signal integrity (SI) resulting in better jitter performance. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade. The devices are characterized for operation from –40°C to 85°C. The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the nits bps (bits per second). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–TBD, Texas Instruments Incorporated SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM (POSITIVE LOGIC) SN65MLVD200A, SN65MLVD204A SN65MLVD202A, SN65MLVD205A 3 DE D 4 D DE 2 RE RE 6 1 R 7 5 R B Y 10 4 Z 3 2 A 9 12 11 A B ORDERING INFORMATION PART (1) NUMBER (1) FOOTPRINT RECEIVER TYPE SN65MLVD200AD SN75176 Type 1 PACKAGE MARKING MF200A SM65MLVD202AD SN75ALS180 Type 1 MLVD202A SN65MLVD204AD SN75176 Type 2 MF204A SM65MLVD205AD SN75ALS180 Type 2 MLVD205A Available tape and reeled. To order a tape and reeled part, add the suffix R to the part number (e.g., SN65MLVD200ADR). PACKAGE DISSIPATION RATINGS PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING D(8) 532 mW 4.6 mW/°C 254 mW D(14) 940 mW 8.2 mW/°C 450 mw ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) SN65MLVD200A, 202A, 204A, and 205A Supply voltage range (2), VCC Input voltage range –0.5 V to 4 V D, DE, RE –0.5 V to 4 V A, B (200A, 204A) –1.8 V to 4 V A, B (202A, 205A) Output voltage range Electrostatic discharge –4 V to 6 V R –0.3 V to 4 V Y, Z, A, or B –1.8 V to 4 V Human Body Model (3) Charged-Device Model (4) A, B, Y, and Z ±8 kV All pins ±4 kV All pins Continuous power dissipation Storage temperature range (1) (2) (3) (4) 2 ±1500 V See Dissipation Rating Table –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 RECOMMENDED OPERATING CONDITIONS MIN NOM 3.3 MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V V Voltage at any bus terminal VA, VB, VY or VZ –1.4 3.8 |VID| Magnitude of differential input voltage 0.05 VCC RL Differential load resistance 1/tUI Signaling rate TA Operating free-air temperature 30 –40 V Ω 50 100 Mbps 85 °C DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER ICC PD (1) Supply current TEST CONDITIONS Driver only RE and DE at VCC, RL = 50 Ω, All others open Both disabled RE at VCC, DE at 0 V, RL = No Load, All others open Both enabled RE at 0 V, DE at VCC, RL = 50 Ω, All others open Receiver only RE at 0 V, DE at 0 V, All others open Device power dissipation RL = 50 Ω, Input to D is a 50-MHz 50% duty cycle square wave, DE = high, RE = low, TA = 85°C MIN TYP( (1) ) MAX 13 22 1 4 16 24 4 13 94 UNIT mA mW All typical values are at 25°C and with a 3.3-V supply voltage. Submit Documentation Feedback 3 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS |VAB| or |VYZ| Differential output voltage magnitude ∆|VAB| or ∆|VYZ| Change in differential output voltage magnitude between logic states VOS(SS) Steady-state common-mode output voltage ∆VOS(SS) Change in steady-state common-mode output voltage between logic states VOS(PP) Peak-to-peak common-mode output voltage VY(OC) or VA(OC) Maximum steady-state open-circuit output voltage VZ(OC) or VB(OC) Maximum steady-state open-circuit output voltage VP(H) Voltage overshoot, low-to-high level output VP(L) Voltage overshoot, high-to-low level output IIH High-level input current (D, DE) VIH = 2 V to VCC IIL Low-level input current (D, DE) VIL = GND to 0.8 V |IOS| Differential short-circuit output current magnitude See Figure 4 IOZ High-impedance state output current (driver only) –1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V IO(OFF) Power-off output current –1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V, 0 V ≤ VCC≤ 1.5 V MIN (1) TYP (2) MAX UNIT 480 650 mV –50 50 mV 0.8 1.2 V –50 50 mV 150 mV 0 2.4 V 0 2.4 V 1.2 VSS V 0 10 µA 0 10 µA 24 mA –15 10 µA –10 10 µA See Figure 2 See Figure 3 See Figure 7 See Figure 5 –0.2 VSS V V, (3) CY or CZ Output capacitance VI = 0.4 sin(30E6πt) + 0.5 Other input at 1.2 V, driver disabled CYZ Differential output capacitance VAB = 0.4 sin(30E6πt) V, Driver disabled CY/Z Output capacitance balance, (CY/CZ) (1) (2) (3) 4 3 pF (3) 2.5 0.99 1.01 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) Submit Documentation Feedback pF SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS Type 1 50 Type 2 150 VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold VHYS Differential input voltage hysteresis, (VIT+– VIT–) VOH High-level output voltage IOH = –8 mA VOL Low-level output voltage IOL = 8 mA IIH High-level input current (RE) VIH = 2 V to VCC IIL Low-level input current (RE) VIL = GND to 0.8 V IOZ High-impedance output current VO = 0 V or 3.6 V Input capacitance VI = 0.4 sin(30E6πt) + 0.5 V, (2) Other input at 1.2 V CA or CB CAB Differential input capacitance CA/B Input capacitance balance, (CA/CB) (1) (2) MIN TYP (1) MAX Type 1 See Figure 9, Table 1 and Table 2 Type 2 UNIT mV –50 mV 50 Type 1 25 Type 2 0 mV 2.4 VAB = 0.4 sin(30E6πt) V 0.4 V –10 0 µA –10 0 µA –10 15 µA 3 pF V (2) 2.5 0.99 pF 1.01 All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER Receiver or transceiver with driver disabled input current IA Receiver or transceiver with driver disabled input current IB IAB Receiver or transceiver with driver disabled differential input current (IA– IB) IA(OFF) Receiver or transceiver power-off input current IB(OFF) Receiver or transceiver power-off input current TEST CONDITIONS MIN TYP (1) MAX VA = 3.8 V, VB = 1.2 V, 0 32 VA = 0 V or 2.4 V, VB = 1.2 V –20 20 VA = -1.4 V, VB = 1.2 V –32 0 VB = 3.8 V, VA = 1.2 V 0 32 VB = 0 V or 2.4 V, VA = 1.2 V –20 20 VB = -1.4 V, VA = 1.2 V –32 0 VA = VB, 1.4 ≤ VA ≤ 3.8 V -4 4 VA = 3.8 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 0 32 VA = 0 V or 2.4 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –20 20 VA = -1.4 V, VB= 1.2 V, 0 V ≤ VCC ≤ 1.5 V –32 0 VB = 3.8 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 0 32 VB = 0 V or 2.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –20 20 VB = -1.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –32 0 –4 4 UNIT µA µA µA µA µA IAB(OFF) Receiver input or transceiver power-off differential input current (IA– IB) VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V CA Transceiver with driver disabled input capacitance VA = 0.4 sin (30E6πt) + 0.5 V (2), VB =1.2 V 5 pF CB Transceiver with driver disabled input capacitance VB = 0.4 sin (30E6πt) + 0.5 V (2), VA =1.2 V 5 pF CAB Transceiver with driver disabled differential input capacitance VAB = 0.4 sin (30E6πt)V (2) CA/B Transceiver with driver disabled input capacitance balance, (CA/CB) (1) (2) 3 0.99 µA pF 1.01 All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) Submit Documentation Feedback 5 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 2.5 3.5 ns tpHL Propagation delay time, high-to-low-level output 2 2.5 3.5 ns tr Differential output signal rise time 2 2.6 3.2 ns tf Differential output signal fall time 2 2.6 3.2 ns tsk(p) Pulse skew (|tpHL– tpLH|) 30 150 ps tsk(pp) Part-to-part skew tjit(per) Period jitter, rms (1 standard deviation) (2) 50 MHz clock input (3) tjit(pp) Peak-to-peak jitter (2) (4) 100 Mbps 215-1 PRBS input (5) tPHZ tPLZ tPZH Enable time, high-impedance-to-high-level output tPZL Enable time, high-impedance-to-low-level output (1) (2) (3) (4) (5) See Figure 5 0.9 ns 2 3 ps 55 150 ps Disable time, high-level-to-high-impedance output 4 7 ns Disable time, low-level-to-high-impedance output 4 7 ns 4 7 ns 4 7 ns See Figure 6 All typical values are at 25°C and with a 3.3-V supply voltage. Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 2 3.6 6 ns tPHL Propagation delay time, high-to-low-level output 2 3.6 6 ns tr Output signal rise time 1 2.3 ns tf Output signal fall time tsk(p) Pulse skew (|tpHL– tpLH|) tsk(pp) Part-to-part skew (2) tjit(per) Period jitter, rms (1 standard 2.3 ns Type 1 CL = 15 pF, See Figure 10 100 300 ps Type 2 300 500 ps 1 ns deviation) (3) 50 MHz clock Type 1 input (4) 4 7 ps 200 700 ps 225 800 ps tjit(pp) Peak-to-peak jitter (3) (5) tPHZ Disable time, high-level-to-high-impedance output 6 10 ns tPLZ Disable time, low-level-to-high-impedance output 6 10 ns tPZH Enable time, high-impedance-to-high-level output 10 15 ns tPZL Enable time, high-impedance-to-low-level output 10 15 ns (1) (2) (3) (4) (5) (6) 6 Type 2 100 Mbps 215–1 PRBS input (6) 1 See Figure 11 All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. Submit Documentation Feedback SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC IA or IY A/Y II D IB or IZ VAB or VYZ VA or VY B/Z VI VOS VB or VZ VA + VB 2 or VY + VZ 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A/Y VAB or VYZ D B/Z A. + _ 49.9 Ω -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A/Y C1 1 pF D ≈ 1.3 V B/Z ≈ 0.7 V VOS(PP) B/Z C2 1 pF A/Y R2 24.9 Ω VOS C3 2.5 pF VOS(SS) VOS(SS) A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 1 MHz, duty cycle = 50 ± 5%. B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T. D. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage A/Y IOS 0 V or VCC + B/Z VTest -1 V or 3.4 V - Figure 4. Driver Short-Circuit Test Circuit Submit Documentation Feedback 7 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) A/Y D C1 1 pF C3 0.5 pF R1 Output 50 Ω B/Z C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal R1 24.9 Ω A/Y 0 V or VCC C1 1 pF D B/Z DE C4 Output 0.5 pF C2 1 pF R2 24.9 Ω VCC VCC/2 0V DE tpZH tpHZ ∼ 0.6 V 0.1 V 0V Output With D at VCC Output With D at 0 V C3 2.5 pF tpZL tpLZ 0V -0.1 V ∼ -0.6 V A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz. Figure 6. Driver Enable and Disable Time Circuit and Definitions 8 Submit Documentation Feedback SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) A/Y 0 V or VCC B/Z VA, VB, VY or VZ 1.62 kΩ , ±1% Figure 7. Maximum Steady State Output Voltage VCC CLOCK INPUT VCC/2 0V 1/f0 Period Jitter IDEAL OUTPUT 0 V VA -VB or VY -VZ VCC PRBS INPUT 0V ACTUAL OUTPUT 0 V VA -VB or VY -VZ VCC/2 1/f0 Peak to Peak Jitter VA -VB or VY -VZ OUTPUT 0 V Diff tc(n) tjit(per) = tc(n) -1/f0 VA -VB or VY -VZ tjit(pp) A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input. D. Peak-to-peak jitter is measured using a 100Mbps 215–1 PRBS input. Figure 8. Driver Jitter Measurement Waveforms IA A VID VCM (VA + VB)/2 VA R IO B IB VO VB Figure 9. Receiver Voltage and Current Definitions Submit Documentation Feedback 9 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 Table 1. Type-1 Receiver Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES (1) RESULTING COMMONMODE INPUT VOLTAGE RECEIVER (1)OUTPUT VIA VIB VID VIC 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.425 3.335 0.050 3.4 H 3.375 3.425 –0.050 3.4 L –0.975 –1.025 0.050 –1 H –1.025 –0.975 –0.050 –1 L H H= high level, L = low level, output state assumes receiver is enabled (RE = L) Table 2. Type-2 Receiver Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES (1) RESULTING COMMONMODE INPUT VOLTAGE RECEIVER OUTPUT (1) VIA VIB VID VIC 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.475 3.325 0.150 3.4 H 3.425 3.375 0.050 3.4 L –0.925 –1.075 0.150 –1 H –0.975 –1.025 0.050 –1 L H H= high level, L = low level, output state assumes receiver is enabled (RE = L) VID VA CL VO 15 pF VB VA 1.2 V VB 1.0 V VID 0.2 V 0V -0.2 V tpHL VO tpLH VOH 90% VCC/2 10% tf VOL tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T. B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 10. Receiver Timing Test Circuit and Waveforms 10 Submit Documentation Feedback SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 1.2 V B RL 499 Ω R A Inputs CL RE + _ VO VTEST 15 pF VCC VTEST 1V A VCC RE VCC/2 0V tpZL Output tpLZ VCC VCC/2 VOL +0.5 V VOL R VTEST 0V 1.4 V A VCC RE VCC/2 0V tpZH tpHZ VO VOH VOH -0.5 V VCC/2 0V A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T. C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms Submit Documentation Feedback 11 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 INPUTS VA -VB 0.2 V - Type 1 0.4 V - Type 2 CLOCK INPUT VA -VB 1/f0 VIC 1V Period Jitter IDEAL OUTPUT VOH VA VCC/2 PRBS INPUT VOL 1/f0 VB VOH ACTUAL OUTPUT VCC/2 Peak to Peak Jitter VOH VOL tc(n) tjit(per) = tc(n) -1/f0 OUTPUT V CC/2 VOL tjit(pp) A. All input pulses are supplied by an Agilent 8304A Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input. D. Peak-to-peak jitter is measured using a 100 Mbps 215-1 PRBS input. Figure 12. Receiver Jitter Measurement Waveforms PIN ASSIGNMENTS SN65MLVD200AD (Marked as MF200A) SN65MLVD204AD (Marked as MF204A) (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND SN65MLVD202AD (Marked as MLVD202A) SN65MLVD205AD (Marked as MLVD205A) (TOP VIEW) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 NC - No internal connection 12 Submit Documentation Feedback VCC VCC A B Z Y NC SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 DEVICE FUNCTION TABLES TYPE-1 RECEIVER (200A, 202A) INPUTS TYPE-2 RECEIVER (204A, 205A) OUTPUT INPUTS OUTPUT VID = VA - VB RE R VID = VA - VB RE R VID ≥ 50 mV - 50 mV < VID < 50 mV VID ≤ - 50 mV X X L L L H Open H ? L Z Z VID ≥ 150 mV 50 mV < VID < 150 mV VID ≤ 50 mV X L L L H X Open H ? L Z Z Open Circuit L ? Open Circuit L L DRIVER INPUT ENABLE D L H OPEN X X DE H H H OPEN L OUTPUTS A OR Y B OR Z L H L Z Z H L H Z Z H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS DRIVER OUTPUT DRIVER INPUT AND DRIVER ENABLE RECEIVER ENABLE VCC VCC VCC 360 kΩ 400 Ω 400 Ω D or DE A/Y or B/Z 7V RE 7V 360 kΩ RECEIVER INPUT RECEIVER OUTPUT VCC VCC 100 kΩ 100 kΩ 250 kΩ 10 Ω 250 kΩ A R B 10 Ω 200 kΩ 200 kΩ Submit Documentation Feedback 7V 13 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 30 20 ICC − Supply Current − mA Tx ICC − Supply Current − mA VCC = 3.3 V f = 50 MHz VID = 200 mV VIC = 1 V 25 15 10 Rx VCC = 3.3 V VID = 200 mV VIC = 1 V TA = 25°C 5 20 Tx 15 10 Rx 5 0 0 10 20 30 40 50 −40 f − Frequency − MHz Figure 14. RECEIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE RECEIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 TA = 25°C 60 VCC = 3.6 V 50 VCC = 3.3 V 40 VCC = 3.0 V IOH − Receiver High Level Output Current − mA IOL − Receiver Low Level Output Current − mA 14 85 Figure 13. 70 30 20 10 0 −15 10 35 60 TA − Free-Air Temperature − °C 0 1 2 3 4 TA = 25°C −10 −20 −30 VCC = 3.0 V −40 −50 VCC = 3.3 V −60 −70 VCC = 3.6 V −80 −90 0 1 2 3 VOL − Low Level Output Voltage − V VOH − High Level Output Voltage − V Figure 15. Figure 16. Submit Documentation Feedback 4 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE RECEIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 2.8 4 Receiver Propagation Delay − ns Driver Propagation Delay − ns VCC = 3.3 V f = 1 MHz RL = 50 Ω 2.6 tpHL 2.4 tpLH 2.2 2 VCC = 3.3 V VID = 200 mV VIC = 1 V f = 1 MHz CL = 15 pF 3.80 3.60 tpLH 3.40 3.20 3 −40 −15 10 35 60 −40 85 10 35 60 Figure 17. Figure 18. ADDED DRIVER CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY ADDED DRIVER PEAK-TO-PEAK JITTER vs SIGNALING RATE 85 60 30 VCC = 3.3 V TA = 25°C Input = Clock Added Driver Peak-To-Peak Jitter − ps Added Driver Cycle-To-Cycle Jitter − ps −15 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C 24 tpHL 18 12 6 0 10 20 30 40 50 VCC = 3.3 V TA = 25°C 215-1 PRBS NRZ 52 44 36 28 20 Clock Frequency − MHz Figure 19. 20 40 60 80 Signaling Rate − Mbps 100 Figure 20. Submit Documentation Feedback 15 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) ADDED DRIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE ADDED RECEIVER CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY 72 40 VCC = 3.3 V VIC = 1 V f = 100 Mbps 215-1 PRBS NRZ Added Receiver Cycle-To-Cycle Jitter − ps Added Driver Peak-To-Peak Jitter − ps 80 64 56 48 40 −40 −15 10 35 60 TA − Free-Air Temperature − °C 22 Type-2 VID = 400 mV 16 10 50 ADDED RECEIVER PEAK-TO-PEAK JITTER vs SIGNALING RATE ADDED RECEIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE 300 Type-2 VID = 400 mV VCC = 3.3 V TA = 25C VIC = 1 V 215-1 PRBS NRZ 180 Type-1 VID = 200 mV 120 60 0 VCC = 3.3 V VIC = 1 V 215-1 PRBS NRZ Type-2 VID = 400 mV 240 180 Type-1 VID = 200 mV 120 60 0 20 40 60 80 Signaling Rate − Mbps 100 Figure 23. 16 20 30 40 Clock Frequency − MHz Figure 22. Added Receiver Peak-To-Peak Jitter − ps Added Receiver Peak-To-Peak Jitter − ps 28 10 85 Type-1 VID = 200 mV 34 Figure 21. 300 240 VCC = 3.3 V TA = 25°C VIC = 1 V −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 24. Submit Documentation Feedback 85 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) Vertical Scale = 127.2 mV/div SN65MLVD200A DRIVER OUTPUT EYE PATTERN vs 100 Mbps, 215-1 PRBS, RL = 50 Ω Horizontal Scale = 2 ns/div Figure 25. Vertical Scale = 400 mV/div SN65MLVD200A RECEIVER OUTPUT EYE PATTERN vs 100 Mbps, 215-1 PRBS, cL = 15 pF Horizontal Scale = 2 ns/div Figure 26. Submit Documentation Feedback 17 SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 APPLICATION INFORMATION COMPARISON OF MLVD TO TIA/EIA-485 Receiver Input Threshold (Failsafe) The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in Table 3 and Figure 27. Table 3. Receiver Input Voltage Threshold Requirements RECEIVER TYPE OUTPUT LOW OUTPUT HIGH Type 1 –2.4 V ≤ VID ≤ -0.05 V 0.05 V ≤ VID ≤ 2.4 V Type 2 –2.4 V ≤ VID ≤ 0.05 V 0.15 V ≤ VID ≤ 2.4 V 200 Type 1 Type 2 VID - Differential Input Voltage - mV High 150 100 High 50 0 Low -50 -100 Low Transition Regions Figure 27. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65MLVD200AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD200ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD200ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD200ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD202AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD202ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD202ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD202ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD204AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD204ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD204ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD204ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD205AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD205ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD205ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD205ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 16-Jun-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65MLVD200ADR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1 SN65MLVD202ADR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1 SN65MLVD204ADR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1 SN65MLVD205ADR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65MLVD200ADR D 8 FMX 342.9 336.6 20.6 SN65MLVD202ADR D 14 FMX 342.9 336.6 28.58 SN65MLVD204ADR D 8 FMX 342.9 336.6 20.6 SN65MLVD205ADR D 14 FMX 342.9 336.6 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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