SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES D Backplane or Cabled Multipoint Data and D Low-Voltage Differential 30-Ω to 55-Ω Line D Cellular Base Stations D Central-Office Switches D Network Switches and Routers Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps D Type-1 Receivers Incorporate 25 mV of Hysteresis Clock Transmission DESCRIPTION D Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions D Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange D Power Up/Down Glitch Free D Controlled Driver Output Voltage Transition Times for Improved Signal Quality D –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise D Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V D 100-Mbps Devices Available (SN65MLVD200, 202, 204, 205) APPLICATIONS D Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485 The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M–LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 Ω, and incorporates controlled transition times to allow for stubs off of the backbone transmission line. These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C. LOGIC DIAGRAM (POSITIVE LOGIC) SN65MLVD201, SN65MLVD206 DE D RE 3 D 4 DE 2 1 R SN65MLVD203, SN65MLVD207 RE 6 7 A B 5 10 4 Y Z 3 2 R 9 12 11 A B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002 – 2003, Texas Instruments Incorporated SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER FOOTPRINT RECEIVER TYPE PACKAGE MARKING SN65MLVD201D SN75176 Type 1 MF201 SM65MLVD203D SN75ALS180 Type 1 MLVD203 SN65MLVD206D SN75176 Type 2 MF206 SM65MLVD207D SN75ALS180 Type 2 MLVD207 PACKAGE DISSIPATION RATINGS PACKAGE TA ≤ 25°C POWER RATING D(8) D(14) TA = 85°C POWER RATING 725 mW DERATING FACTOR ABOVE TA = 25°C 5.8 mW/_C 950 mW 7.6 mW/_C 494 mw 377 mW ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) SN65MLVD201, 203, 206, AND 207 Supply voltage range(2), VCC Input In ut voltage range O t t voltage Output lt range Electrostatic discharge –0.5 V to 4 V D, DE, RE –0.5 V to 4 V A, B (201, 206) –1.8 V to 4 V A, B (203, 207) –4 V to 6 V R –0.3 V to 4 V Y, Z, A, or B –1.8 V to 4 V H Human B Body d M Model d l(3) Charged-Device Model(4) ±8 kV A, B, Y, and Z All pins ±2 kV All pins ±1500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114–A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 MAX UNIT 3.6 V V GND VCC 0.8 Voltage at any bus terminal VA, VB, VY or VZ –1.4 3.8 V Magnitude of differential input voltage, VID 0.05 Operating free-air temperature, TA –40 VCC 85 °C Low-level input voltage, VIL 2 V V SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted MIN TYP(1) MAX 13 22 Both enabled RE and DE at VCC, RL = 50 Ω, All others open RE at VCC, DE at 0 V, RL = No Load, All others open 1 4 Both enabled RE at 0 V, DE at VCC, RL = 50 Ω, All others open 16 24 Receiver only RE at 0 V, DE at 0 V, RL = 50 Ω, All others open (1) All typical values are at 25°C and with a 3.3-V supply voltage. 4 13 PARAMETER Driver only ICC Supply current TEST CONDITIONS UNIT mA DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT 480 650 mV –50 50 mV 0.8 1.2 V –50 50 mV 150 mV 0 2.4 V 0 2.4 V 1.2VSS V VAB or VYZ Differential output voltage magnitude ∆VAB or ∆VYZ Change in differential output voltage magnitude between logic states VOS(SS) Steady-state common-mode output voltage ∆VOS(SS) Change in steady-state common-mode output voltage between logic states VOS(PP) VY(OC) or VA(OC) VZ(OC) or VB(OC) Peak-to-peak common-mode output voltage VP(H) Voltage overshoot, low-to-high level output VP(L) Voltage overshoot, high-to-low level output IIH High-level input current (D, DE) VIH = 2 V 0 10 µA IIL Low-level input current (D, DE) VIL = 0.8 V 0 10 µA IOS Differential short-circuit output current magnitude See Figure 4 24 mA IOZ High-impedance state output current (driver only) –1.4 V ≤ VY or VZ ≤ 3.8 V, Other output = 1.2 V –15 10 µA IO(OFF) Power-off output current –1.4 V ≤ VY or VZ ≤ 3.8 V, Other output = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –10 10 µA CY or CZ Output capacitance VI = 0.4 sin(30E6πt) + 0.5 V, (3) Other input at 1.2 V, driver disabled CYZ Differential output capacitance VAB = 0.4 sin(30E6πt) V, (3) Driver disabled CY/Z Output capacitance balance, (CY/CZ) Maximum steady-state open-circuit output voltage Maximum steady-state open-circuit output voltage See Figure 2 See Figure 3 See Figure 7 See Figure 5 –0.2 VSS V 3 pF 2.5 0.99 pF 1.01 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) All typical values are at 25°C and with a 3.3-V supply voltage. (3) HP4194A impedance analyzer (or equivalent) 3 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted(1) PARAMETER TEST CONDITIONS MIN TYP(1) MAX Positive-going differential in input ut voltage threshold Type 1 50 VIT+ Type 2 150 VIT– Negative-going differential in input ut voltage threshold Type 1 See Figure 9 and Table 1 and Type 2 Table 2 Differential in input ut voltage hysteresis, (VIT+ – VIT) Type 1 25 VHYS Type 2 0 VOH High-level output voltage mV 50 VOL Low-level output voltage IOL = 8 mA IIH High-level input current (RE) VIH = 2 V –10 IIL Low-level input current (RE) VIL = 0.8 V IOZ High-impedance output current VO = 0 V or 3.6 V CA or CB Input capacitance mV CAB Differential input capacitance V 0.4 V 0 µA –10 0 µA –10 15 µA VI = 0.4 sin(30E6πt) + 0.5 V,(2) Other input at 1.2 V VAB = 0.4 sin(30E6πt) V(2) CA/B Input capacitance balance, (CA/CB) (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) mV –50 2.4 IOH = –8 mA UNIT 3 pF 2.5 0.99 1.01 MIN TYP(1) MAX pF BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER IA Receiver or transceiver with driver disabled input current IB Receiver or transceiver with driver disabled input current IAB Receiver or transceiver with driver disabled differential input current (IA – IB) Receiver or transceiver power-off input IA(OFF) current IB(OFF) Receiver or transceiver power-off input current Receiver input or transceiver power-off IAB(OFF) differential input current (IA – IB) TEST CONDITIONS VA = 3.8 V, VB = 1.2 V, 0 32 VA = 0 V or 2.4 V, VB = 1.2 V –20 20 VA = –1.4 V, VB = 1.2 V –32 0 VB = 3.8 V, VA = 1.2 V 0 32 VB = 0 V or 2.4 V, VA = 1.2 V –20 20 VB = –1.4 V, VA = 1.2 V –32 0 VA = VB, –1.4 ≤ VA ≤ 3.8 V –4 4 VA = 3.8 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 0 32 VA = 0 V or 2.4 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –20 20 VA = –1.4 V, VB= 1.2 V, 0 V ≤ VCC ≤ 1.5 V –32 0 VB = 3.8 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V 0 32 VB = 0 V or 2.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –20 20 VB = –1.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V –32 0 –4 4 VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V UNIT µA µ µA µ µA µA µ µA µ µA CA Transceiver with driver disabled input capacitance VA = 0.4 sin (30E6πt) + 0.5V(2), VB =1.2 V 5 pF CB Transceiver with driver disabled input capacitance VB = 0.4 sin (30E6πt) + 0.5V(2), VA =1.2 V 5 pF (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) 4 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS (continued) PARAMETER CAB Transceiver with driver disabled differential input capacitance TEST CONDITIONS MIN TYP(1) VAB = 0.4 sin (30E6πt)V (2) Transceiver with driver disabled input capacitance balance, (CA/CB) (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) CA/B MAX 3 0.99 UNIT pF 1.01 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tpHL Propagation delay time, high-to-low-level output 1 1.5 2.4 ns tr Differential output signal rise time 1 1.6 ns tf Differential output signal fall time tsk(p) Pulse skew (|tpHL – tpLH|) tsk(pp) Part-to-part skew tjit(per) Period jitter, rms (1 standard deviation) (2) 100 MHz clock input(3) tjit(pp) Peak-to-peak jitter(2)(5) 200 Mbps 215–1 PRBS input(4) tpHZ See Figure 5 1 1.6 ns 100 ps 1 ns 2 3 ps 30 130 ps 0 Disable time, high-level-to-high-impedance output 7 ns tpLZ Disable time, low-level-to-high–impedance output 7 ns tpZH Enable time, high-impedance-to-high-level output 7 ns 7 ns See Figure 6 tpZL Enable time, high-impedance-to-low-level output (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (3) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (4) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) tpLH Propagation delay time, low-to-high-level output 2 4 tpHL Propagation delay time, high-to-low-level output 2 4 tr Output signal rise time 1 tf Output signal fall time tsk(p) Pulse skew (|tpHL – tpLH|) tsk(pp) Part-to-part skew(2) tjit(per) Period jitter, rms (1 standard deviation) (3) tjit(pp) Peak to peak jitter(3)(6) Peak-to-peak tpHZ Disable time, high-level-to-high-impedance output tpLZ Disable time, low-level-to-high-impedance output tpZH Enable time, high-impedance-to-high-level output UNIT 6 ns 6 ns 2.3 ns 2.3 ns Type 1 100 300 ps Type 2 300 500 ps 1 ns CL = 15 pF,, See Figure g 10 100 MHz clock input(4) Type 1 Type 2 200 Mbps 215–1 1 PRBS input(5) See Figure 11 1 MAX 4 7 ps 300 700 ps 450 800 ps 10 ns 10 ns 15 ns tpZL 15 ns Enable time, high-impedance-to-low-level output (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (5) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). 5 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 PARAMETER MEASUREMENT INFORMATION VCC IA or IY A/Y II D IB or IZ VAB or VYZ VA or VY B/Z VI VOS VB or VZ VA + VB 2 or VY + VZ 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A/Y VAB or VYZ D + _ 49.9 Ω B/Z –1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ NOTE: All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A/Y C1 1 pF D ≈ 1.3 V B/Z ≈ 0.7 V VOS(PP) B/Z C2 1 pF A/Y R2 24.9 Ω VOS C3 2.5 pF VOS(SS) VOS NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T. D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage A/Y 0 V or VCC IOS + B/Z VTest –1 V or 3.4 V – Figure 4. Driver Short-Circuit Test Circuit 6 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 A/Y C1 1 pF D C3 0.5 pF R1 Output 50 Ω B/Z C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal R1 24.9 Ω A/Y 0 V or VCC C1 1 pF D B/Z DE C4 Output 0.5 pF C2 1 pF R2 24.9 Ω VCC VCC/2 0V DE tpZH tpHZ ∼ 0.6 V 0.1 V 0V Output With D at VCC Output With D at 0 V C3 2.5 pF tpZL tpLZ 0V –0.1 V ∼ –0.6 V NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%. C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T. D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 6. Driver Enable and Disable Time Circuit and Definitions 7 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 A/Y 0 V or VCC B/Z 1.62 kΩ , ±1% VA, VB, VY or VZ Figure 7. Maximum Steady State Output Voltage VCC CLOCK INPUT VCC/2 0V 1/f0 Period Jitter IDEAL OUTPUT 0 V VA –VB or VY –VZ VCC PRBS INPUT 0V ACTUAL OUTPUT 0 V VA –VB or VY –VZ VCC/2 1/f0 Peak to Peak Jitter VA –VB or VY –VZ OUTPUT 0 V Diff tc(n) tjit(per) = tc(n)–1/f0 VA –VB or VY –VZ tjit(pp) NOTES:A. B. C. D. All input pulses are supplied by an Agilent 8304A Stimulus System. The measurement is made on a TEK TDS6604 running TDSJIT3 application software Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input. Peak-to-peak jitter is measured using a 200Mbps 215–1 PRBS input. Figure 8. Driver Jitter Measurement Waveforms IA A VID VCM (VA + VB)/2 VA IB R IO B VO VB Figure 9. Receiver Voltage and Current Definitions 8 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 Table 1. Type-1 Receiver Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON– MODE INPUT VOLTAGE RECEIVER OUTPUT VIA 2.400 VIB 0.000 VID 2.400 VIC 1.200 0.000 2.400 –2.400 1.200 L 3.800 3.750 0.050 3.775 H 3.750 3.800 –0.050 3.775 L –1.350 –1.400 0.050 –1.375 H –1.400 –1.350 –0.050 –1.375 : NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L) H L Table 2. Type-2 Receiver Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON– MODE INPUT VOLTAGE RECEIVER OUTPUT VIA 2.400 VIB 0.000 VID 2.400 VIC 1.200 0.000 2.400 –2.400 1.200 L 3.800 3.650 0.150 3.725 H 3.800 3.750 0.050 3.775 L –1.250 –1.400 0.150 –1.325 H –1.350 –1.400 0.050 –1.375 : NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L) H L VID VA CL 15 pF VB VO VA 1.2 V VB 1.0 V VID 0.2 V 0V –0.2 V tpHL VO tpLH VOH VCC/2 VOL 90% 10% tf tr NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T. B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 10. Receiver Timing Test Circuit and Waveforms 9 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 1.2 V B RL 499 Ω R A Inputs RE CL 15 pF VO + _ VCC VTEST 1V A VCC VCC/2 0V RE tpZL Output tpLZ VCC VCC/2 VOL +0.5 V VOL R VTEST 0V 1.4 V A VCC VCC/2 0V RE tpZH VO VTEST tpHZ VOH VOH –0.5 V VCC/2 0V NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T. C. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T. D. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms 10 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 INPUTS VA –VB 0.2 V – Type 1 0.4 V – Type 2 CLOCK INPUT VA –VB 1/f0 VIC 1V Period Jitter IDEAL OUTPUT VOH VA VCC/2 VOL PRBS INPUT 1/f0 VB VOH ACTUAL V OUTPUT CC/2 VOL Peak to Peak Jitter VOH tc(n) tjit(per) = tc(n)–1/f0 OUTPUT V /2 CC VOL tjit(pp) NOTES:A. B. C. D. All input pulses are supplied by an Agilent 8304A Stimulus System. The measurement is made on a TEK TDS6604 running TDSJIT3 application software Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input. Peak-to-peak jitter is measured using a 200 Mbps 215–1 PRBS input. Figure 12. Receiver Jitter Measurement Waveforms PIN ASSIGNMENTS SN65MLVD201D (Marked as MF201) SN65MLVD206D (Marked as MF206) (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND SN65MLVD203D (Marked as MLVD203) SN65MLVD207D (Marked as MLVD207) (TOP VIEW) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC NC – No internal connection 11 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 DEVICE FUNCTION TABLE TYPE-1 RECEIVER (201, 203) INPUTS TYPE-2 RECEIVER (206, 207) OUTPUT INPUTS OUTPUT VID = VA – VB RE R VID = VA – VB RE R VID ≥ 50 mV – 50 mV < VID < 50 mV VID ≤ – 50 mV X X L L L H Open H ? L Z Z VID ≥ 150 mV 50 mV < VID < 150 mV VID ≤ 50 mV X X L L L H Open H ? L Z Z Open Circuit L ? Open Circuit L L DRIVER INPUT ENABLE D L H OPEN X X DE H H H OPEN L OUTPUTS A OR Y B OR Z L H L Z Z H L H Z Z H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS DRIVER OUTPUT DRIVER INPUT AND DRIVER ENABLE RECEIVER ENABLE VCC VCC VCC 360 kΩ 400 Ω 400 Ω D or DE A/Y or B/Z 7V RE 7V 360 kΩ RECEIVER INPUT RECEIVER OUTPUT VCC VCC 100 kΩ 100 kΩ 250 kΩ 10 Ω 250 kΩ A R B 10 Ω 200 kΩ 12 200 kΩ 7V SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 20 20 16 ICC – Supply Current – mA ICC – Supply Current – mA VCC = 3.3 V TA = 25°C Driver 12 8 Receiver 4 16 Driver 12 Receiver 8 4 Receiver VID = 250 mV VIC = 1 V 0 10 30 50 70 90 VCC = 3.3 V TA = 25°C f = 100 MHz 0 110 –50 f – Frequency – MHz –30 –10 10 30 50 TA – Free-Air Temperature – °C Figure 13 60 VCC = 3.6 V 50 VCC = 3.3 V 40 VCC = 3.0 V IOH – Receiver High Level Output Current – mA IOL – Receiver Low Level Output Current – mA 0 TA = 25°C 30 20 10 1 2 3 VOL – Low Level Output Voltage – V Figure 15 90 RECEIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 70 0 70 Figure 14 RECEIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 0 Receiver VID = 250 mV VIC = 1 V 4 TA = 25°C –10 –20 –30 VCC = 3.0 V –40 –50 VCC = 3.3 V –60 –70 VCC = 3.6 V –80 –90 0 1 2 3 4 VOH – High Level Output Voltage – V Figure 16 13 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 2 1.6 Driver Propagation Delay – ns Differential Output Voltage – V 2 1.2 0.8 0.4 VCC = 3.3 V f = 1 MHz 1.8 tpLH 1.6 tpHL 1.4 1.2 VCC = 3.3 V TA = 25°C 0 0 2 8 4 6 IO – Output Current – mA 10 1 –50 12 –30 –10 30 10 50 TA – Free-Air Temperature – °C Figure 17 ADDED DRIVER CYCLE-TO-CYCLE JITTER (PEAK) vs FREQUENCY 45 VCC = 3.3 V VID = 250 mV VIC = 1 V f = 1 MHz Added Driver Cycle-To-Cycle Jitter – pa Receiver Propagation Delay – ns 6 tpHL 4 tpLH 2 VCC = 3.3 V TA = 25°C Input = Clock 36 27 18 9 0 –30 –10 10 30 50 TA – Free-Air Temperature – °C Figure 19 14 90 Figure 18 RECEIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 1 –50 70 70 90 10 30 50 70 f – Frequency – MHz Figure 20 90 110 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 ADDED DRIVER PEAK-TO-PEAK JITTER vs DATA RATE 60 VCC = 3.3 V TA = 25°C Input = PRBS 215–1 Added Driver Peak-To-Peak Jitter – ps Added Driver Peak-To-Peak Jitter – ps 60 50 40 30 20 10 0 25 65 ADDED DRIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE 105 145 185 50 40 30 20 VCC = 3.3 V TA = 25°C Input = PRBS 215–1 f = 200 Mbps 10 0 –50 225 –30 Figure 21 Added Receiver Peak-To-Peak Jitter – ps Added Receiver Cycle-To-Cycle Jitter – ps 400 VIC = 3.0 V 21 VIC = –0.5 V VIC = 1 V 14 7 0 10 30 50 70 f – Frequency – MHz Figure 23 30 50 70 90 ADDED RECEIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE 35 28 10 Figure 22 ADDED RECEIVER CYCLE-TO-CYCLE JITTER vs FREQUENCY VCC = 3.3 V VID = 250 mV TA = 25°C –10 TA – Free-Air Temperature – °C Data Rate – Mbps 90 110 VCC = 3.3 V VID = 250 mV TA = 25°C Pattern = 215–1 320 240 160 80 0 0 30 60 90 120 150 Data Rate – Mbps 180 210 Figure 24 15 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 ADDED RECEIVER PEAK-TO–PEAK JITTER vs FREE-AIR TEMPERATURE SN65MLVD201 DRIVER OUTPUT EYE PATTERN 200 Mbps, 215–1 PRBS, RL = 50 Ω 320 Vertical Scale = 175 mV/div Added Receiver Peak-To-Peak Jitter – ps 400 240 160 80 0 –50 VCC = 3.3 V VID = 250 mV VIC =1 V f =200 Mbps Pattern = 215–1 Horizontal Scale = 1 ns/div –30 –10 30 10 50 TA – Free-Air Temperature – °C 70 90 Figure 25 Figure 26 Vertical Scale = 400 mV/div SN65MLVD201 RECEIVER OUTPUT EYE PATTERN 200 Mbps, 215–1 PRBS, CL = 15 pF Horizontal Scale = 1 ns/div Figure 27 16 SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 APPLICATION INFORMATION COMPARISON OF MLVD TO TIA/EIA-485 Receiver Input Threshold (Failsafe) The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in Table 3 and Figure 28. Table 3. Receiver Input Voltage Threshold Requirements RECEIVER TYPE OUTPUT LOW OUTPUT HIGH Type 1 –2.4 V ≤ VID ≤ –0.05 V 0.05 V ≤ VID ≤ 2.4 V Type 2 –2.4 V ≤ VID ≤ 0.05 V 0.15 V ≤ VID ≤ 2.4 V 200 Type 1 Type 2 VID – Differential Input Voltage – mV High 150 100 High 50 0 Low –50 –100 Low Transition Regions Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region 17 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65MLVD201D ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD201DR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD203D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD203DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD206D ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD206DR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD207D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65MLVD207DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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