MG2040, SZMG2040 ESD Protection Diodes Low Capacitance ESD Protection for High Speed Video Interface The MG2040 ESD protection diode is designed specifically to protect HDMI and Display Port with full functionality ESD protection and back drive current protection for VCC line. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed TMDS lines. Features • • • • • • • Full Function HDMI / Display Port Solution Single Connect, Flow through Routing for TMDS Lines Low Capacitance (0.35 pF Typical, I/O to GND) Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 (±8 kV Contact) UL Flammability Rating of 94 V−0 SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM 18 1 UDFN18 CASE 517CP 2040MG G 2040 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping MG2040MUTAG UDFN18 (Pb−Free) 3000 / Tape & Reel SZMG2040MUTAG UDFN18 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications • HDMI • Display Port MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±15 ±15 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 4 1 Publication Order Number: MG2040/D MG2040, SZMG2040 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 15 Center Pins, Pin 12, 14, 16, 18 Note: Common GND – Only Minimum of 1 GND connection required = Figure 1. Pin Schematic I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 18 GND GND 17 I/O 16 GND GND 15 I/O 14 GND GND 13 I/O 12 GND Figure 2. Pin Configuration Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground. Only minimum of one pin needs to be connected to ground for functionality of all pins. http://onsemi.com 2 Pin 17 MG2040, SZMG2040 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions Min Typ Max Unit 5.0 V I/O Pin to GND (Note 1) IT = 1 mA, I/O Pin to GND 5.5 V Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 1.0 mA Clamping Voltage (Note 1) VC IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 3) See Figures 8 through 11 VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 11.4 15.3 −4.6 −8.1 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 0.15 0.20 VR = 0 V, f = 1 MHz between I/O Pins and GND 0.35 0.42 VR = 0 V, f = 1 MHz between I/O Pins 0.02 VR = 0 V, f = 1 MHz between I/O Pins and GND 0.04 DCJ Junction Capacitance Difference See Figures 3 and 4 V pF pF 1. Surge current waveform per Figure 7. 2. For test procedure see Figures 5 and 6 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 90 0 80 −10 60 VOLTAGE (V) VOLTAGE (V) 70 50 40 30 −20 −30 20 10 −40 0 −10 −20 0 20 40 60 80 TIME (ns) 100 120 −50 −20 140 Figure 3. IEC61000−4−2 +8 KV Contact Clamping Voltage 0 20 40 60 80 TIME (ns) 100 120 Figure 4. IEC61000−4−2 −8 KV Contact Clamping Voltage http://onsemi.com 3 140 MG2040, SZMG2040 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 7. 8 X 20 ms Pulse Waveform http://onsemi.com 4 80 22 −22 20 −20 18 −18 16 −16 CURRENT (A) CURRENT (A) MG2040, SZMG2040 14 12 10 8 −14 −12 −10 −8 6 −6 4 −4 2 −2 0 0 2 4 6 8 10 12 14 16 0 0 18 −2 −4 −6 −8 −10 −12 −14 VOLTAGE (V) VOLTAGE (V) Figure 8. Positive TLP I−V Curve Figure 9. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 10. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 11 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 10 MW IM −18 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable −16 VM DUT VC Oscilloscope Figure 10. Simplified Schematic of a Typical TLP System Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 5 MG2040, SZMG2040 Without ESD With MG2040 Figure 12. HDMI1.4 Eye Diagram with and without MG2040. 3.4 Gb/s, 400 mVPP S21 INSERTION LOSS (dB) 4 2 MG2040 IO−GND 0 −2 −4 −6 −8 −10 1.E+06 1.E+07 1.E+08 1.E+09 FREQUENCY (Hz) Figure 13. MG2040 Insertion Loss http://onsemi.com 6 1.E+10 MG2040, SZMG2040 HDMI Type−A Connector MG2040 D2+ GND D2− D1+ GND D1− D0+ GND D0− CLK+ GND CLK− CEC N/C (or HEC_DAT – HDMI1.4) SCL SDA GND 5V HPD (and HEC_DAT – HDMI1.4) Black = Top layer Red = other layer Figure 14. HDMI Layout Diagram http://onsemi.com 7 MG2040, SZMG2040 PACKAGE DIMENSIONS UDFN18, 5.5x1.5, 0.5P/0.75P CASE 517CP ISSUE A D PIN ONE REFERENCE 0.10 C 2X ÉÉ 0.10 C 2X L2 A B L E D3 DETAIL A OPTIONAL CONSTRUCTION TOP VIEW A DETAIL B 0.05 C DETAIL C ÉÉ ÉÉ ÇÇ EXPOSED Cu (A3) A1 0.10 C MOLD CMPD DIM A A1 A3 b D D2 D3 E E2 eA eB eC L L2 DETAIL B NOTE 4 DETAIL A D3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. EXPOSED ENDS OF TERMINALS ARE ELECTRICALLY ACTIVE. C SIDE VIEW D2 eA 1 DETAIL C OPTIONAL CONSTRUCTION SEATING PLANE 11 18 NOTE 5 E2 L 12 18X eB eC b 0.10 M C A B 0.05 M C RECOMMENDED SOLDERING FOOTPRINT* END VIEW NOTE 3 6X BOTTOM VIEW 3X 6X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 5.50 BSC 0.35 0.45 0.10 REF 1.50 BSC 0.35 0.45 0.50 BSC 0.75 BSC 1.50 BSC 0.20 0.40 0.10 REF 0.13 3X 0.50 0.45 0.75 PITCH 0.13 0.50 18X 0.50 1.80 1 17X 0.50 PITCH 0.30 1.50 PITCH NOTE: CENTER PADS OPTIONAL DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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