NCP59749 D

NCP59749
3.0 A, Dual-Rail Very
Low‐Dropout Linear
Regulator with
Programmable Soft‐Start
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The NCP59749 is dual−rail very low dropout voltage regulator that
is capable of providing an output current in excess of 3.0 A with a
dropout voltage of 120 mV typ. at full load current. The devices are
stable with ceramic and any other type of output capacitor ≥ 2.2 mF.
This series contains adjustable output voltage version with output
voltage down to 0.8 V. Internal protection features consist of built−in
thermal shutdown and output current limiting protection.
User−programmable Soft−Start and Power Good pins are available.
The NCP59749 is available in QFN20 5x5 package.
QFN20
CASE 485DB
NC
NC
OUT
Output Current in Excess of 3.0 A
VIN Range: 0.8 V to 5.5 V
VBIAS Range: 2.7 V to 5.5 V
Output Voltage Range: 0.8 V to 3.6 V
Dropout Voltage: 120 mV at 3 A
Programmable Soft Start
Open Drain Power Good Output
Fast Transient Response
Stable with Any Type of Output Capacitor ≥ 2.2 mF
Current Limit and Thermal Shutdown Protection
These are Pb−Free Devices
5
4
3
2
1
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB
GND
SS
NC
NC
EN
11 12 13 14 15
GND
•
•
•
•
•
•
•
•
•
•
•
NC
Features
IN
PIN CONNECTIONS
QFN20, 5x5, 0.65P
MARKING DIAGRAM
1
Applications
• Consumer and Industrial Equipment Point of Load Regulation
• FPGA, DSP and Logic Power Supplies
• Switching Power Supply Post Regulation
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
QFN20
XXXXX = Specific Device Code
A
= Assembly Location
L/WL
= Wafer Lot
Y/YY
= Year
W/WW = Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
NCP59749
Figure 1. Typical Application Schematic
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
March, 2014 − Rev. 0
1
Publication Order Number:
NCP59749/D
NCP59749
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Name
QFN−20
Description
IN
5−8
EN
11
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode. This pin must not be left floating.
SS
15
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left
floating, the regulator output soft-start ramp time is typically 200 ms.
BIAS
10
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
9
Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT
exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this
threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kW to 1 MW should be
connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
FB
16
This pin is the feedback connection to the center tap of an external resistor divider network that sets the
output voltage. This pin must not be left floating.
OUT
1, 18−20
Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 mF, ceramic) is needed from
this pin to ground to assure stability.
NC
GND
PAD/TAB
Unregulated input to the device.
2−4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better thermal contact to the
top-side plane.
12
Ground
Should be soldered to the ground plane for increased thermal performance
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NCP59749
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Input Voltage Range
VIN
−0.3 to +6
V
Input Voltage Range
VBIAS
−0.3 to +6
V
Enable Voltage Range
VEN
−0.3 to +6
V
Power-Good Voltage Range
VPG
−0.3 to +6
V
PG Sink Current
IPG
0 to +1.5
mA
SS Pin Voltage Range
VSS
−0.3 to +6
V
Feedback Pin Voltage Range
VFB
−0.3 to +6
V
Output Voltage Range
VOUT
−0.3 to (VIN + 0.3) ≤ 6
V
Maximum Output Current
IOUT
Internally Limited
PD
See Thermal Characteristics Table and Formula
Output Short Circuit Duration
Indefinite
Continuous Total Power Dissipation
Maximum Junction Temperature
TJMAX
+125
°C
Storage Junction Temperature Range
TSTG
−55 to +150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22-A114
ESD Machine Model tested per EIA/JESD22-A115
Latch-up Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient (Note 5)
RqJA
30.5
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 6)
RqJC
4.1
°C/W
Thermal Characteristics, QFN20, 5x5, 0.65P package
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
− This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
− JEDEC51.7 guidelines.
− The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated.
− Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7)
Symbol
Min
Max
Unit
Input Voltage
VIN
VOUT + VDO
5.5
V
Bias Voltage
VBIAS
2.7
5.5
V
TJ
−40
125
°C
Rating
Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCP59749
Table 5. ELECTRICAL CHARACTERISTICS
(At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 mF, CSS = 1 nF, CIN = COUT = 10 mF, IOUT = 50 mA, VBIAS = 5.0 V, TJ = −40°C to
+125°C, unless otherwise noted. Typical values are at TJ = +25°C.)
Symbol
VIN
Parameter
Test Conditions
Input Voltage Range
Min
Typ
VOUT +VDO
Unit
5.5
V
VBIAS
Bias Pin Voltage Range
5.5
V
UVLO
Undervoltage Lock-out
VBIAS rising
Hysteresis
1.2
1.6
0.4
1.9
V
VREF
Internal Reference (Adj.)
TJ = +25°C
0.798
0.802
0.806
V
VOUT
Output Voltage Range
VIN = 5 V, IOUT = 3.0 A
VREF
3.6
V
Accuracy (Note 1)
VOUT + 2.2 V < VBIAS < 5.5 V,
50 mA < lOUT < 3.0 A
±0.5
+2
%
VOUT/VIN
Line Regulation
VOUT (NOM) + 0.3 < VIN < 5.5 V
0.03
%/V
VOUT/IOUT
Load Regulation
50mA < IOUT < 3.0 A
0.09
%/A
VIN Dropout Voltage (Note 2)
IOUT = 3.0 A,
VBIAS - VOUT (NOM) ≥ 3.25 V (Note 3)
120
280
mV
VBIAS Dropout Voltage (Note 2)
IOUT = 3.0 A, VIN = VBIAS
1.31
1.75
V
Current Limit
VOUT = 80% x VOUT (NOM)
4.6
6.0
A
1
2
mA
1
50
mA
0.15
1
VDO
ICL
IBIAS
Bias Pin Current
ISHDN
Shutdown Supply Current (IGND)
IFB
PSRR
2.7
Max
Power-supply Rejection
(VBIAS to VOUT)
3.8
VEN ≤ 0.4 V
Feedback Pin Current
Power-supply Rejection
(VIN to VOUT)
-2
-1
1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
60
300 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
30
1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
50
300 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V
30
mA
dB
dB
Noise
Output Noise Voltage
100 Hz to 100 kHz, lOUT = 3 A
tSTRT
Minimum Startup Time
RLOAD for IOUT = 1.0 A, CSS = open
200
ms
Soft-start Charging Current
VSS = 0.4 V
0.44
mA
ISS
25 x VOUT
VEN, HI
Enable Input High Level
1.1
0
VEN, LO
Enable Input Low Level
VEN, HYS
Enable Pin Hysteresis
VEN, DG
Enable Pin Deglitch Time
5.5
0.4
50
Enable Pin Current
VEN = 5 V
VIT
PG Trip Threshold
VOUT decreasing
VHYS
PG Trip Hysteresis
85
PG Output Low Voltage
IPG = 1 mA (Sinking), VOUT < VIT
IPG, LKG
PG Leakage Current
VPG = 5.25 V, VOUT > VIT
Thermal Shutdown Temperature
Shutdown, temperature increasing
Reset, temperature decreasing
V
ms
0.1
1
mA
90
94
%VOUT
3
VPG, LO
V
mV
20
IEN
TSD
mVRMS
0.1
+165
+140
%VOUT
0.3
V
1
mA
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Adjustable devices tested at VREF; external resistor tolerance is not taken into account.
2. Dropout is defined as the voltage from the input to VOUT when VOUT is 3% below nominal.
3. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
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NCP59749
TYPICAL CHARACTERISTICS
0.20
0.5
0.15
0.4
0.10
−40°C
+125°C
0.05
0
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
+25°C
−0.05
−0.10
−0.15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
−0.1
−0.3
1.5
2.0
2.5
3.0
3.5
Figure 3. VIN Line Regulation
Figure 4. VBIAS Line Regulation
0.3
0.2
CHANGE IN VOUT (%)
0.4
+125°C
0.1
+25°C
0
−0.1
−0.2
−0.3
−40°C
10
20
30
40
50
+125°C
0.1
+25°C
0
−0.1
−0.2
−0.3
−40°C
0
0.5
1.0
1.5
2.0
2.5
IOUT, OUTPUT CURRENT (mA)
IOUT, OUTPUT CURRENT (A)
Figure 5. Load Regulation
Figure 6. Load Regulation
100
+125°C
80
+25°C
60
−40°C
40
20
1.0
1.5
2.0
2.5
3.0
3.0
500
450
IOUT = 3 A
400
350
300
250
200
+25°C
150
+125°C
100
50
0
−40°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT, OUTPUT CURRENT (A)
VBIAS − VOUT (V)
Figure 7. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 8. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
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4.0
0.2
−0.4
−0.5
120
0.5
1.0
VBIAS − VOUT (V)
0.3
0
0.5
VIN − VOUT (V)
0.4
0
+25°C
−0.2
0.5
0
+125°C
−40°C
0.1
0.5
−0.4
−0.5
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
0
0.2
−0.4
−0.5
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
CHANGE IN VOUT (%)
−0.20
0.3
4.5
NCP59749
TYPICAL CHARACTERISTICS
VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
1400
200
180
IOUT = 0.5 A
1300
160
1200
140
−40°C
120
+25°C
100
60
40
20
0
0.5
1.0
1.5
+25°C
1000
+125°C
80
−40°C
1100
2.0
2.5
3.0
3.5
4.0
4.5
VBIAS − VOUT (V)
+125°C
900
800
700
600
0
2000
1800
1800
−40°C
1000
800
−40°C
1000
800
600
400
400
200
200
0
0
0.5
1.5
1.0
2.0
2.5
3.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
IOUT, OUTPUT CURRENT (A)
VBIAS (V)
Figure 11. BIAS Pin Current vs. IOUT and
Temperature TJ
Figure 12. BIAS Pin Current vs. VBIAS and
Temperature TJ
0.500
5.5
VPG,LO, L−LEVEL PG VOLTAGE (V)
1.0
0.475
0.450
ISS (mA)
3.0
+125°C
1200
600
0
2.5
+25°C
1400
IBIAS (mA)
1200
IBIAS (mA)
1600
+25°C
+125°C
2.0
Figure 10. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
2000
1400
1.5
1.0
IOUT, OUTPUT CURRENT (A)
Figure 9. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
1600
0.5
0.425
0.400
0.375
0.350
0.325
0.300
−50
−25
0
25
50
75
100
125
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (°C)
IPG, PG PIN CURRENT (mA)
Figure 13. Soft Start Charging Current ISS vs.
Temperature TJ
Figure 14. L−level PG Voltage vs. Current
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12
NCP59749
TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
ICL, CURRENT LIMIT (A)
6.0
+25°C
−40°C
5.0
+125°C
4.0
3.0
2.0
1.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VBIAS − VOUT (V)
Figure 15. Current Limit vs. (VBIAS − VOUT)
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5.0
NCP59749
APPLICATIONS INFORMATION
example), the recommended CIN and CBIAS value is 1 mF or
greater. Ceramic or other low ESR capacitors are
recommended. For the best performance all the capacitors
should be connected to the NCP59749 respective pins
directly in the device PCB copper layer, not through vias
having not negligible impedance.
The NCP59749 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from VIN voltage. All the low current internal
controll circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike a PMOS topology
devices, the output capacitor has reduced impact on loop
stability. Vin to Vout operating voltage difference can be
very low compared with standard PMOS regulators in very
low Vin applications.
The NCP59749 offers programmable smooth monotonic
start-up. The controlled voltage rising limits the inrush
current what is advantageous in applications with large
capacitive loads. The Voltage Controlled Soft Start timing is
programmable by external Css capacitor value.
The Enable (EN) input is equipped with internal
hysteresis and deglitch filter.
Open Drain type Power Good (PG) output is available for
Vout monitoring and sequencing of other devices.
NCP59749 is a Adjustable linear regulator. The required
Output voltage can be adjusted by two external resistors.
Typical application schematics is shown in Figure 16.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS.
Output Noise
When the NCP59749 device reaches the end of the
Soft−Start cycle, the Soft Start capacitor is switched to serve
as a Noise filtering capacitor.
Output Voltage Adjust
The output voltage can be adjusted from 0.8 V to 3.6 V
using resistors divider between the output and the FB input.
Recommended resistor values for frequently used voltages
can be found in the Table 6.
NCP59749
V OUT + 0.8
Programmable Soft−Start
The Soft-Start ramp time depends on the Soft Start
charging current ISS, Soft-Start capacitor value CSS and
internal reference voltage VREF.
The Soft –Start time can be calculated using following
equations:
tss = CSS x (VREF / ISS) [s, F,V,A]
or in more practical units
tSS = CSS x 0.8V / 0.44 = CSS x 1.82
where
tss = Soft−Start time in miliseconds
CSS = Soft−Start capacitor value in nano Farads
Capacitor values for frequently used Soft-Start times can be
found in the Table 7.
The maximal recommended value of CSS capacitor is
15 nF. For higher CSS values the capacitor full discharging
before new Soft-Start cycle is not guaranteed.
ǒ1 ) R 1ńR 2Ǔ
Figure 16. Typical Application Schematics
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percents specified in the Electrical Characteristics table.
VBIAS is high enough, specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Input and Output Capacitors
The device is designed to be stable for all available types
and values of output capacitors ≥ 2.2 mF. The device is also
stable with multiple capacitors in parallel, which can be of
any type or value.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
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NCP59749
Table 6. RESISTOR VALUES FOR PROGRAMMING
THE OUTPUT VOLTAGE
Table 7. CAPACITOR VALUES FOR PROGRAMMING
THE SOFT−START TIME
VOUT (V)
R1 (kW)
R2 (kW)
Soft−Start Time
CSS
0.8
Short
Open
0.2 ms
Open
0.9
0.619
4.99
0.5 ms
270 pF
NOTE:
1.0
1.13
4.53
1 ms
560 pF
1.05
1.37
4.33
5 ms
2.7 nF
1.1
1.87
4.99
10 ms
5.6 nF
1.2
2.49
4.99
18 ms
10 nF
1.5
4.12
4.75
1.8
3.57
2.87
2.5
3.57
1.69
3.3
3.57
1.15
VOUT = 0.8 x (1 + R1/R2)
Resistors in the table are standard 1% types
Table 8. ORDERING INFORMATION
Device
NCP59749MN2ADJTBG
Output Current
Output
Voltage
Junction Temp.
Range
Package
Shipping
3.0 A
ADJ
−40°C to +125°C
QFN20
3000 / Tape & Reel
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NCP59749
PACKAGE DIMENSIONS
QFN20 5x5, 0.65P
CASE 485DB
ISSUE O
PIN ONE
REFERENCE
ÉÉ
ÉÉ
A B
D
L
L1
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
0.15 C
0.15 C
0.10 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. OPTIONAL FEATURES.
L
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
TOP VIEW
A
(A3)
DETAIL B
DETAIL B
0.08 C
A1
NOTE 5
NOTE 4
ALTERNATE
CONSTRUCTION
C
SIDE VIEW
0.10
DETAIL A
6
D2
M
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.25
0.35
5.00 BSC
3.05
3.25
5.00 BSC
3.05
3.25
0.65 BSC
0.45
0.65
−−−
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
C A B
L
20X
0.10
M
5.30
3.30
C A B
20X
0.78
11
E2
1
16
e
BOTTOM VIEW
3.30
20X
b
0.10
M
C A B
0.05
M
C
NOTE 3
PACKAGE
OUTLINE
5.30
0.65
PITCH
20X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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