MX25L8036E MX25L8036E DATASHEET P/N: PM1571 1 REV. 1.1, JUN. 13, 2012 MX25L8036E Contents FEATURES................................................................................................................................................................... 5 GENERAL........................................................................................................................................................... 5 PERFORMANCE................................................................................................................................................ 5 SOFTWARE FEATURES.................................................................................................................................... 5 HARDWARE FEATURES.................................................................................................................................... 6 GENERAL DESCRIPTION.......................................................................................................................................... 7 Table 1. Additional Feature Comparison............................................................................................................. 7 PIN CONFIGURATIONS .............................................................................................................................................. 8 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. Protected Area Sizes........................................................................................................................... 11 Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11 Memory Organization................................................................................................................................................ 12 Table 4. Memory Organization (8Mb)................................................................................................................ 12 DEVICE OPERATION................................................................................................................................................. 13 Figure 1. Serial Modes Supported.................................................................................................................... 13 COMMAND DESCRIPTION........................................................................................................................................ 14 Table 5. Command Set...................................................................................................................................... 14 (1) Write Enable (WREN).................................................................................................................................. 15 (2) Write Disable (WRDI)................................................................................................................................... 15 (3) Read Identification (RDID)........................................................................................................................... 15 (4) Read Status Register (RDSR)..................................................................................................................... 16 (5) Write Status Register (WRSR)..................................................................................................................... 17 Table 6. Protection Modes................................................................................................................................. 17 (6) Read Data Bytes (READ)............................................................................................................................ 18 (7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 18 (8) Dual Output Read Mode (DREAD).............................................................................................................. 18 (9) 2 x I/O Read Mode (2READ)....................................................................................................................... 19 (10) 4 x I/O Read Mode (4READ)..................................................................................................................... 19 (11) Sector Erase (SE)...................................................................................................................................... 20 (12) Block Erase (BE)....................................................................................................................................... 20 (13) Chip Erase (CE)......................................................................................................................................... 20 (14) Page Program (PP)................................................................................................................................... 21 (15) 4 x I/O Page Program (4PP)...................................................................................................................... 21 (16) Deep Power-down (DP)............................................................................................................................. 21 (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 22 (18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 22 P/N: PM1571 2 REV. 1.1, JUN. 13, 2012 MX25L8036E Table 7. ID Definitions ...................................................................................................................................... 22 (19) Enter Secured OTP (ENSO)...................................................................................................................... 23 (20) Exit Secured OTP (EXSO)......................................................................................................................... 23 (21) Read Security Register (RDSCUR)........................................................................................................... 23 Table 8. Security Register Definition................................................................................................................. 23 (22) Write Security Register (WRSCUR)........................................................................................................... 24 POWER-ON STATE.................................................................................................................................................... 25 ELECTRICAL SPECIFICATIONS............................................................................................................................... 26 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 26 Figure 2. Maximum Negative Overshoot Waveform......................................................................................... 26 CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 26 Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 26 Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 27 Figure 5. OUTPUT LOADING.......................................................................................................................... 27 Table 9. DC CHARACTERISTICS ................................................................................................................... 28 Table 10. AC CHARACTERISTICS .................................................................................................................. 29 Timing Analysis......................................................................................................................................................... 30 Figure 6. Serial Input Timing............................................................................................................................. 30 Figure 7. Output Timing..................................................................................................................................... 30 Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1.................................................. 31 Figure 9. Write Enable (WREN) Sequence (Command 06).............................................................................. 31 Figure 10. Write Disable (WRDI) Sequence (Command 04)............................................................................. 31 Figure 11. Read Identification (RDID) Sequence (Command 9F)..................................................................... 32 Figure 12. Read Status Register (RDSR) Sequence (Command 05)............................................................... 32 Figure 13. Write Status Register (WRSR) Sequence (Command 01)............................................................. 32 Figure 14. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 33 Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 33 Figure 16. Dual Read Mode Sequence (Command 3B)................................................................................... 34 Figure 17. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 34 Figure 18. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 35 Figure 19. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 36 Figure 20. Sector Erase (SE) Sequence (Command 20)................................................................................. 37 Figure 21. Block Erase (BE) Sequence (Command D8).................................................................................. 37 Figure 22. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 37 Figure 23. Page Program (PP) Sequence (Command 02).............................................................................. 38 Figure 24. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 38 Figure 25. Deep Power-down (DP) Sequence (Command B9)....................................................................... 39 Figure 26. Read Electronic Signature (RES) Sequence (Command AB)......................................................... 39 Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 40 Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)......... 40 P/N: PM1571 3 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 29. Power-up Timing.............................................................................................................................. 41 Table 11. Power-Up Timing............................................................................................................................... 41 INITIAL DELIVERY STATE............................................................................................................................... 41 OPERATING CONDITIONS........................................................................................................................................ 42 Figure 30. AC Timing at Device Power-Up........................................................................................................ 42 Figure 31. Power-Down Sequence................................................................................................................... 43 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 44 DATA RETENTION..................................................................................................................................................... 44 LATCH-UP CHARACTERISTICS............................................................................................................................... 44 ORDERING INFORMATION....................................................................................................................................... 45 PART NAME DESCRIPTION...................................................................................................................................... 46 PACKAGE INFORMATION......................................................................................................................................... 47 REVISION HISTORY .................................................................................................................................................. 48 P/N: PM1571 4 REV. 1.1, JUN. 13, 2012 MX25L8036E 8M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 8M:8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O read mode) structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read - 1 I/O: 133MHz with 8 dummy cycles - 2 I/O: 108MHz with 4 dummy cycles for 2READ instruction; 133MHz with 8 dummy cycles for DREAD instruction - 4 I/O: 133MHz with 6 dummy cycles - Fast access time: 133MHz serial clock - Serial clock of two I/O read mode : 108MHz (2READ); 133MHz (DREAD) - Serial clock of four I/O read mode : 133MHz, which is equivalent to 532MHz - Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 3s(typ.) /chip • Low Power Consumption - Low active read current: 35mA(max.) at 133MHz, and 10mA(max.) at 50MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (typ.) ; 50uA (max.) - Deep power-down current: 3uA (typ.) ; 20uA (max.) • Minimum 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4K-bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID P/N: PM1571 5 REV. 1.1, JUN. 13, 2012 MX25L8036E - All REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (200mil) - All devices are RoHS Compliant P/N: PM1571 6 REV. 1.1, JUN. 13, 2012 MX25L8036E GENERAL DESCRIPTION The MX25L8036E are 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is in two or four I/O read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. The MX25L8036E feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin, and SIO3 pin for address/dummy bits input and data output. The MX25L8036E provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Secured OTP and Block Protection, please see security feature and write status register section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC current. The MX25L8036E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Feature Comparison Additional Features Part Name MX25L8036E P/N: PM1571 Protection and Security Read Performance Flexible Block Protection (BP0-BP3) 4K-bit secured OTP 2 I/O Read 4 I/O Read V V V V Identifier RES REMS REMS2 REMS4 RDID (command: (command: (command: (command: (command: AB hex) 90 hex) EF hex) DF hex) 9F hex) 13 (hex) 7 C2 13 (hex) C2 13 (hex) C2 13 (hex) (if ADD=0) (if ADD=0) (if ADD=0) C2 20 14 (hex) REV. 1.1, JUN. 13, 2012 MX25L8036E PIN CONFIGURATIONS PIN DESCRIPTION 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 SYMBOL CS# 8 7 6 5 VCC NC/SIO3 SCLK SI/SIO0 SI/SIO0 SO/SIO1 SCLK WP#/SIO2 NC/SIO3 VCC GND P/N: PM1571 8 DESCRIPTION Chip Select Serial Data Input (for 1 x I/O) / Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Serial Data Output (for 1 x I/O) Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Clock Input Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) NC pin (Not connect) or Serial Data Input & Output (for 4xI/O read mode) + 3.3V Power Supply Ground REV. 1.1, JUN. 13, 2012 MX25L8036E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 NC/SIO3 SCLK Mode Logic State Machine HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1571 Sense Amplifier 9 REV. 1.1, JUN. 13, 2012 MX25L8036E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Page Program (4PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the QE bit is set, the feature of HPM will be disabled. P/N: PM1571 10 REV. 1.1, JUN. 13, 2012 MX25L8036E Table 2. Protected Area Sizes BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status bit BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 8Mb 0 (none) 1 (1block, 1/16 area, block#15) 2 (2blocks, 1/8 area, block#14-15) 3 (4blocks, 1/4 area, block#12-15) 4 (8blocks, 1/2 area, block#8-15) 5 (16blocks, all) 6 (16blocks, all) 7 (16blocks, all) 8 (16blocks, all) 9 (16blocks, all) 10 (16blocks, all) 11 (8blocks, 1/2 area, block#0-7) 12 (12blocks, 3/4 area, block#0-11) 13 (14blocks, 7/8 area, block#0-13) 14 (15block, 15/16 area, block#0-14) 15 (16blocks, all) II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1571 11 Customer Lock Determined by customer REV. 1.1, JUN. 13, 2012 MX25L8036E Memory Organization Table 4. Memory Organization (8Mb) Block 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P/N: PM1571 Sector 255 : 240 239 : 224 223 : 208 207 : 192 191 : 176 175 : 160 159 : 144 143 : 128 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 2 1 0 Address Range 0FF000h 0FFFFFh : : 0F0000h 0F0FFFh 0EF000h 0EFFFFh : : 0E0000h 0E0FFFh 0DF000h 0DFFFFh : : 0D0000h 0D0FFFh 0CF000h 0CFFFFh : : 0C0000h 0C0FFFh 0BF000h 0BFFFFh : : 0B0000h 0B0FFFh 0AF000h 0AFFFFh : : 0A0000h 0A0FFFh 09F000h 09FFFFh : : 090000h 090FFFh 08F000h 08FFFFh : : 080000h 080FFFh 07F000h 07FFFFh : : 070000h 070FFFh 06F000h 06FFFFh : : 060000h 060FFFh 05F000h 05FFFFh : : 050000h 050FFFh 04F000h 04FFFFh : : 040000h 040FFFh 03F000h 03FFFFh : : 030000h 030FFFh 02F000h 02FFFFh : : 020000h 020FFFh 01F000h 01FFFFh : : 010000h 010FFFh 00F000h 00FFFFh : : 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh 12 REV. 1.1, JUN. 13, 2012 MX25L8036E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5.For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS, REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO, and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1571 13 REV. 1.1, JUN. 13, 2012 MX25L8036E COMMAND DESCRIPTION Table 5. Command Set COMMAND (byte) WREN (write enable) WRDI (write disable) 1st byte 06 (hex) 04 (hex) 2nd byte 3rd byte 4th byte 5th byte Action sets the resets the outputs to read out to write new n bytes (WEL) write (WEL) write JEDEC the values values to read out enable latch enable latch ID: 1-byte of the status the status until CS# bit bit manufactregister register goes high urer ID & 2-byte device ID 4READ 4PP COMMAND (4 x I/O read (quad page (byte) command) program) 1st byte 2nd byte 3rd byte 4th byte Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action RDID RDSR WRSR (read READ (read status (write status identifica(read data) register) register) tion) 9F (hex) 05 (hex) 01 (hex) 03 (hex) AD1 Values (A23-A16) AD2 (A15-A8) AD3 (A7-A0) EB (hex) ADD(4) & Dummy (4) Dummy (4) SE (sector erase) BE (block erase) 38 (hex) 20 (hex) D8 (hex) AD1 AD1 AD1 FAST READ (fast read data) 0B (hex) 2READ (2 DREAD (1I x I/O read 2O read command) command) Note1 3B (hex) BB (hex) AD1 AD1 ADD(2) AD2 AD2 ADD(2) & Dummy (2) AD3 AD3 Dummy Dummy n bytes n bytes n bytes read out read out by read out by until CS# Dual output 2xI/O until goes high until CS# CS# goes goes high high CE (chip erase) PP (Page program) DP (Deep power down) RES (read electronic ID) 60 or C7 (hex) RDP (Release from deep power down) 02 (hex) B9 (hex) AB (hex) AB (hex) AD1 x AD2 AD2 AD2 x AD3 AD3 AD3 x n bytes quad input to erase the to erase the to erase to program enters deep release to read read out by to program selected selected whole chip the selected power down from deep out 1-byte 4 x I/O until the selected sector block page mode power down device ID CS# goes page mode high REMS (read electronic manufacturer & device ID) 90 (hex) x x ADD (Note 2) output the manufacturer ID & device ID REMS2 REMS4 ENSO (enter EXSO RDSCUR WRSCUR (read ID for (read ID for secured (exit secured (read security (write security 2x I/O mode) 4x I/O mode) OTP) OTP) register) register) Release Read Enhanced EF (hex) DF (hex) B1 (hex) C1 (hex) 2B (hex) 2F (hex) FFh (hex) x x x x x x ADD ADD x (Note 2) (Note 2) output the output the to enter to exit the 4K- to read value to set the All these manufacturer manufacturer the 4K-bit bit secured of security lock-down bit commands ID & device ID & device secured OTP OTP mode register as "1" (once FFh,00h,AAh ID ID mode lock-down, or 55h will cannot be escape the updated) performance enhance mode Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. P/N: PM1571 14 REV. 1.1, JUN. 13, 2012 MX25L8036E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (Please refer to Figure 9) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. (Please refer to Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Quad Page Program (4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to "Table 7. ID Definitions") The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1571 15 REV. 1.1, JUN. 13, 2012 MX25L8036E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (Please refer to Figure 12) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. If the program/erase command is applied to a protected memory area, the array data will not be affected and WEL bit will be reset. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP# or is set to "1" to enable Quad SIO2 and SIO3. Once the system goes into Quad I/O mode, the feature of HPM will be disable. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, which is set to "0" (factory default). The SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 SRWD (status register write protect) bit6 QE (Quad Enable) bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) 1=Quad 1=status Enable register write (note 1) (note 1) (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit bit Factory Factory Factory Factory Factory default=0 default=0 default=0 default=0 default=0 Note 1: Please refer to the "Table 2. Protected Area Sizes". P/N: PM1571 16 bit2 BP0 (level of protected block) (note 1) Non-volatile bit Factory default=0 bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Factory default=0 Factory default=0 REV. 1.1, JUN. 13, 2012 MX25L8036E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (Please refer to Figure 13) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 6. Protection Modes Mode Status register condition WP# and SRWD bit status Memory Software protection mode (SPM) Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. Hardware protection mode (HPM) The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. P/N: PM1571 17 REV. 1.1, JUN. 13, 2012 MX25L8036E Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the QE bit is set, the feature of HPM will be disabled. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 14) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Dual Output Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on SIO0→ 8-bit dummy cycle on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS# to high at any time during data out (Please refer to Figure 16). P/N: PM1571 18 REV. 1.1, JUN. 13, 2012 MX25L8036E While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→data out interleave on SIO1 & SIO0→to end 2READ operation can use CS# to high at any time during data out (Please refer to Figure 17). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 18). Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4 READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (Please refer to Figure 19). In the performance-enhancing mode (Note of Figure 19), P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. And afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1571 19 REV. 1.1, JUN. 13, 2012 MX25L8036E (11) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→sending SE instruction code→ 3-byte address on SI →CS# goes high. (Please refer to Figure 20) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (12) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of address byte been latchedin); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→sending BE instruction code→ 3-byte address on SI →CS# goes high. (Please refer to Figure 21) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (13) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary( the eighth bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→CS# goes high. (Please refer to Figure 22) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set to "0". P/N: PM1571 20 REV. 1.1, JUN. 13, 2012 MX25L8036E (14) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 23) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (15) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→at least 1-byte on data on SIO[3:0]→CS# goes high. (Please refer to Figure 24) (16) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please refer to Figure 25) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction P/N: PM1571 21 REV. 1.1, JUN. 13, 2012 MX25L8036E code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in "Table 10. AC CHARACTERISTICS". Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 26, Figure 27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. (18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS4 instruction is recommended to use for 4 I/O identification. The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 28. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 7. ID Definitions RDID Command manufacturer ID C2 memory type 20 electronic ID 13 device ID 13 RES Command REMS/REMS2/REMS4/ Command P/N: PM1571 manufacturer ID C2 22 memory density 14 REV. 1.1, JUN. 13, 2012 MX25L8036E (19) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP mode→CS# goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. (20) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP mode→ CS# goes high. (21) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction→Security Register data out on SO→ CS# goes high. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, array access is not allowed. Table 8. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x LDSO (indicate if lock-down Secured OTP indicator bit reserved reserved reserved reserved reserved reserved volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit P/N: PM1571 23 0 = not lock-down 0 = non-factory 1 = lock-down lock (cannot 1 = factory program/erase lock OTP) non-volatile bit non-volatile bit REV. 1.1, JUN. 13, 2012 MX25L8036E (22) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction→CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1571 24 REV. 1.1, JUN. 13, 2012 MX25L8036E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) P/N: PM1571 25 REV. 1.1, JUN. 13, 2012 MX25L8036E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2.Specifications contained within the following tables are subject to change. 3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3. Figure 3. Maximum Positive Overshoot Waveform Figure 2. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns Max. Unit Conditions Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1571 Min. Typ. 26 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.7VCC 0.3VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 5. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=10pF Including jig capacitance P/N: PM1571 27 REV. 1.1, JUN. 13, 2012 MX25L8036E Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Parameter Notes Min. Typ. Max. Units Test Conditions ILI Input Load Current 1 ±2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ±2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 20 50 uA VIN = VCC or GND, CS# = VCC ISB2 Deep Power-down Current 3 20 uA VIN = VCC or GND, CS# = VCC 35 mA f=133MHz, fT=133MHz(Dual output read) fQ=133MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 25 mA fT=108MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 10 mA f=50MHz, SCLK=0.1VCC/0.9VCC, SO=Open 20 mA 20 mA 1 20 mA Erase in Progress, CS#=VCC 1 20 mA Erase in Progress, CS#=VCC -0.5 0.3VCC V 0.7VCC VCC+0.4 V 0.4 V IOL = 1.6mA V IOH = -100uA ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 1 VCC-0.2 Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2.Typical value is calculated by simulation. 3. It is measured under checkboard pattern. P/N: PM1571 28 REV. 1.1, JUN. 13, 2012 MX25L8036E Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter Clock Frequency for the following instructions: fSCLK fC FAST_READ, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR fRSCLK fR Clock Frequency for READ instructions 2READ fT Clock Frequency fTSCLK DREAD fQ Clock Frequency for 4READ instructions f4PP Clock Frequency for 4PP (Quad page program) 133MHz 108MHz (2READ) tCH(1) tCLH Clock High Time Normal Read 4PP 133MHz 108MHz (2READ) tCL(1) tCLL Clock Low Time Normal Read 4PP tCLCH(2) Clock Rise Time (3) (peak to peak) tCHCL(2) Clock Fall Time (3) (peak to peak) tSLCH tCSS CS# Active Setup Time (relative to SCLK) tCHSL CS# Not Active Hold Time (relative to SCLK) tDVCH tDSU Data In Setup Time tCHDX tDH Data In Hold Time tCHSH CS# Active Hold Time (relative to SCLK) tSHCH CS# Not Active Setup Time (relative to SCLK) Read tSHSL(3) tCSH CS# Deselect Time Write/Erase/Program 2.7V-3.6V tSHQZ(2) tDIS Output Disable Time 3.0V-3.6V tCLQV tV Clock Low to Output Valid (Loading: 10pF) tCLQX tHO Output Hold Time tWHSL Write Protect Setup Time tSHWL Write Protect Hold Time tDP(2) CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature tRES1(2) Read tRES2(2) CS# High to Standby Mode with Electronic Signature Read tW Write Status Register Cycle Time tBP Byte-Program tPP Page Program Cycle Time tSE Sector Erase Cycle Time tBE Block Erase Cycle Time tCE Chip Erase Cycle Time Min. Typ. D.C. 3.3 4.5 9 14 3.3 4.5 9 14 0.1 0.1 3 3 2 2 3 3 15 50 Max. Unit 133 MHz 50 108 133 133 33 10 MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us 20 us 20 100 300 3 300 2.2 15 us ms us ms ms s s 9 9 6.5 1 20 100 40 9 0.7 60 0.4 3 Notes: 1. tCH + tCL must be greater than or equal to 1/f (fC or fT or fQ or fR or f4PP). 2. Value guaranteed by characterization, not 100% tested in production. 3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Test condition is shown as Figure 4, 5. P/N: PM1571 29 REV. 1.1, JUN. 13, 2012 MX25L8036E Timing Analysis Figure 6. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 7. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM1571 tSHQZ ADDR.LSB IN 30 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI High-Z SO Figure 9. Write Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO P/N: PM1571 04 High-Z 31 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 11. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 Device Identification 0 15 14 13 MSB 3 2 1 0 MSB Figure 12. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 13. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI SO P/N: PM1571 Status Register In 01 7 6 5 4 3 2 1 0 MSB High-Z 32 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 14. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command 24-Bit Address 23 22 21 03 SI 3 2 1 0 MSB Data Out 1 High-Z SO 7 6 5 4 3 Data Out 2 2 1 0 7 MSB Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 P/N: PM1571 4 3 2 1 0 7 MSB MSB 33 6 5 4 3 2 1 0 7 MSB REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 16. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 39 40 41 42 43 30 31 32 SCLK 8 Bit Instruction SO/SIO1 address bit23, bit22, ...bit1, bit0 3B(hex) SI/SIO0 8 dummy cycle 24 BIT Address dummy High Impedance Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... Figure 17. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 26 27 9 10 11 SCLK 8 Bit Instruction SI/SIO0 SO/SIO1 BB(hex) High Impedance 12 BIT Address 4 dummy cycle Data Output address bit22, bit20, bit18...bit0 P2 P0 data bit6, bit4, bit2...bit0, bit6, bit4.... address bit23, bit21, bit19...bit1 P3 P1 data bit7, bit5, bit3...bit1, bit7, bit5.... Note: 1. SI/SIO0 or SO/SIO1 should be kept "00" or "11" in the first 2 dummy cycles. In other words, P2=P0 or P3=P1 is necessary. P/N: PM1571 34 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 18. 4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction SI/SIO0 SO/SIO1 WP#/SIO2 NC/SIO3 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EB(hex) Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will enter the performance enhance mode. P/N: PM1571 35 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 19. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction 6 Address cycles WP#/SIO2 NC/SIO3 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EB(hex) SI/SIO0 SO/SIO1 Performance enhance indicator (Note) CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... SCLK 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output SI/SIO0 address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... SO/SIO1 address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... WP#/SIO2 address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... NC/SIO3 address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF P/N: PM1571 36 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 20. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Note: SE command is 20(hex). Figure 21. Block Erase (BE) Sequence (Command D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 D8 2 1 0 MSB Note: BE command is D8(hex). Figure 22. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). P/N: PM1571 37 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 23. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 7 SI 6 5 4 3 2 Data Byte 3 0 1 7 MSB 6 5 4 3 2 Data Byte 256 1 7 0 MSB 6 5 4 3 2 MSB Figure 24. 4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Command 20 16 12 8 4 0 4 0 4 0 4 0 4 0 SO/SIO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 WP#/SIO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 NC/SIO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 SI/SIO0 P/N: PM1571 Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 6 Address cycle 38 38 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 25. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power-down Mode Stand-by Mode Figure 26. Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI AB tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1571 39 Stand-by Mode REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI AB High-Z SO Stand-by Mode Deep Power-down Mode Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO X 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Instruction is either 90(hex) or EF(hex) or DF(hex). P/N: PM1571 40 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 29. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 11. Power-Up Timing Symbol Parameter Min. tVSL(1) VCC(min) to CS# low 300 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1571 41 REV. 1.1, JUN. 13, 2012 MX25L8036E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 30 and Figure 31 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figure is ignored, the device will not operate correctly. During power-up and power down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 30. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tCHSH tSHCH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes : 1.Sampled, not 100% tested. 2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 10. AC CHARACTERISTICS". P/N: PM1571 42 REV. 1.1, JUN. 13, 2012 MX25L8036E Figure 31. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1571 43 REV. 1.1, JUN. 13, 2012 MX25L8036E ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 100 ms Sector Erase Cycle Time 60 300 ms Block Erase Cycle Time 0.4 2.2 s Chip Erase Cycle Time 3 15 s Byte Program Time (via page program command) 9 300 us 0.7 3 ms Page Program Cycle Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC JESD-47 & JESD22-A117 standard. DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1571 44 REV. 1.1, JUN. 13, 2012 MX25L8036E ORDERING INFORMATION PART NO. MX25L8036EM2I-08G P/N: PM1571 CLOCK (MHz) TEMPERATURE PACKAGE Remark 133 -40°C~85°C 8-SOP (200mil) RoHS Compliant 45 REV. 1.1, JUN. 13, 2012 MX25L8036E PART NAME DESCRIPTION MX 25 L 8036E M2 I 08 G OPTION: G: RoHS Compliant SPEED: 08: 133MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 200mil 8-SOP DENSITY & MODE: 8036E: 8Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1571 46 REV. 1.1, JUN. 13, 2012 MX25L8036E PACKAGE INFORMATION P/N: PM1571 47 REV. 1.1, JUN. 13, 2012 MX25L8036E REVISION HISTORY Revision No. 1.0 1.1 P/N: PM1571 Description 1. Removed "Advanced Information" 2. Modified EPN 3. Modified address range from xxx010~xxxFFF to xxx010~xxx1FF 4. Modified Figure 20. Sector Erase (SE) Sequence (Command 20) 1. Modified tSLCH, tCHSL, tCHDX, tCHSH, tSHCH time 2. Modified description for RoHS compliance 48 Page Date P1 MAR/30/2010 P45,46 P11 P37 P29JUN/13/2012 P6,45,46 REV. 1.1, JUN. 13, 2012 MX25L8036E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2010~2012. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 49