Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
TDA1517ATW
8 W BTL or 2 × 4 W SE power
amplifier
Product specification
Supersedes data of 2001 Feb 14
2001 Apr 17
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
FEATURES
• Electrostatic discharge protection
• Requires very few external components
• Thermal protection
• Flexibility in use: mono Bridge-Tied Load (BTL) and
stereo Single-Ended (SE); it should be noted that in
stereo applications the outputs of both amplifiers are in
opposite phase
• Reverse polarity safe
• Capable of handling high energy on outputs (VP = 0 V)
• No switch-on/switch-off plop
• Low thermal resistance.
• High output power
• Low offset voltage at output (important for BTL)
GENERAL DESCRIPTION
• Fixed gain
The TDA1517ATW is an integrated class-AB output
amplifier contained in a plastic heatsink thin shrink small
outline package (HTSSOP20). The device is primarily
developed for multimedia applications.
• Good ripple rejection
• Mode select switch (operating, mute and standby)
• AC and DC short-circuit safe to ground and VP
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
supply voltage
6
12
18
V
IORM
repetitive peak output current
−
−
2.5
A
Iq(tot)
total quiescent current
−
40
80
mA
Istb
standby current
−
0.1
100
μA
THD = 10%; RL = 4 Ω
−
4
−
W
SE application
Po
output power
SVRR
supply voltage ripple rejection
RS = 0 Ω
46
−
−
dB
αcs
channel separation
RS = 10 kΩ
40
55
−
dB
Vn(o)
noise output voltage
RS = 0 Ω
−
50
−
μV
⎪Zi⎪
input impedance
50
−
−
kΩ
BTL application
Po
output power
THD = 10%; RL = 8 Ω
−
8
−
W
SVRR
supply voltage ripple rejection
RS = 0 Ω
50
−
−
dB
⎪ΔVOO⎪
output offset voltage
−
−
150
mV
Vn(o)(offset)
noise output offset voltage
−
70
−
μV
⎪Zi⎪
input impedance
25
−
−
kΩ
RS = 0 Ω
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TDA1517ATW
HTSSOP20
2001 Apr 17
DESCRIPTION
plastic thermal enhanced thin shrink small outline package;
20 leads; body width 4.4 mm; exposed die pad
2
VERSION
SOT527-1
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
BLOCK DIAGRAM
VP1
handbook, full pagewidth
15
non-inverting
input 1
3
mute switch
+
60
kΩ
VP2
16
Cm
8
−
OUT1a
VA
9
+
2
kΩ
power stage
18 kΩ
VP
TDA1517ATW
17
standby
switch
1
2
6
7
14
19
20
VA
mute
switch
15 kΩ
x1
SVRR
OUT1b
−
+
+
−
5
15 kΩ
MODE
not
connected
standby
reference
voltage
mute
reference
voltage
18 kΩ
2
kΩ
inverting
input 2
−
12
+
VA
18
60
kΩ
13
−
+
mute switch
input
reference
voltage
OUT2b
Cm
power stage
4
10
SGND
PGND1
Fig.1 Block diagram.
2001 Apr 17
OUT2a
3
11
PGND2
MGU303
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
PINNING
SYMBOL
PIN
DESCRIPTION
n.c.
1
not connected
n.c.
2
not connected
IN1+
3
non-inverting input 1
SGND
4
signal ground
SVRR
5
supply voltage ripple rejection
n.c.
6
not connected
n.c.
7
not connected
SGND 4
OUT1a
8
output 1a
SVRR 5
OUT1b
9
output 1b
n.c. 6
15 VP1
PGND1
10
power ground 1
n.c. 7
14 n.c.
PGND2
11
power ground 2
OUT1a 8
13 OUT2b
OUT2a
12
output 2a
OUT1b 9
12 OUT2a
OUT2b
13
output 2b
n.c.
14
not connected
PGND1 10
11 PGND2
VP1
15
supply voltage 1
VP2
16
supply voltage 2
MODE
17
mode select switch
IN2−
18
inverting input 2
n.c.
19
not connected
n.c.
20
not connected
handbook, halfpage
n.c. 1
20 n.c.
n.c. 2
19 n.c.
IN1+ 3
18 IN2−
17 MODE
TDA1517ATW
16 VP2
MGU302
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The TDA1517ATW contains two identical amplifiers with differential input stages. This device can be used for Bridge-Tied
Load (BTL) or Single-Ended (SE) applications. The gain of each amplifier is fixed at 20 dB. A special feature of this
device is the mode select switch. Since this pin has a very low input current (<40 μA), a low cost supply switch can be
used. With this switch the TDA1517ATW can be switched into three modes:
• Standby: low supply current
• Mute: input signal suppressed
• Operating: normal on condition.
2001 Apr 17
4
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT.
VP
supply voltage
−
18
V
VPSC
AC and DC short-circuit-safe voltage
−
18
V
Vrp
reverse polarity voltage
ERGo
energy handling capability at outputs
IOSM
−
6
V
−
200
mJ
non-repetitive peak output current
−
4
A
IORM
repetitive peak output current
−
2.5
A
Ptot
total power dissipation
−
5
W
Tvj
virtual junction temperature
−
150
°C
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
VP = 0 V
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
−
−
tbf
DC CHARACTERISTICS
VP = 12 V; Tamb = 25 °C; measured in Fig.3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VP
supply voltage
note 1
6.0
12
18
V
Iq
quiescent current
RL = ∞
−
40
80
mA
8.5
−
VP
V
Operating condition
VMODE(oper)
mode switch voltage level
IMODE(oper)
mode switch current
−
15
40
μA
VO
DC output voltage
−
5.7
−
V
⎪ΔVOO⎪
DC output offset voltage
−
−
150
mV
3.3
−
6.4
V
VMODE = 12 V
Mute condition
VMODE(mute) mode switch voltage level
VO
DC output voltage
−
5.7
−
V
⎪ΔVOO⎪
DC output offset voltage
−
−
150
mV
Standby condition
VMODE(stb)
mode switch voltage level
0
−
2
V
Istb
standby current
−
0.1
100
μA
Note
1. The circuit is DC adjusted at VP = 6 to 18 V and AC operating at VP = 8.5 to 18 V.
2001 Apr 17
5
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
AC CHARACTERISTICS
VP = 12 V; f = 1 kHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SE application; note 1
Po
output power
note 2
THD = 1%
2.5
3.3
−
W
THD = 10%
3
4
−
W
THD
total harmonic distortion
Po = 1 W
−
0.1
−
%
fro(L)
low frequency roll-off
−1 dB; note 3
−
25
−
Hz
fro(H)
high frequency roll off
−1 dB
20
−
−
kHz
GV
voltage gain
19
20
21
dB
⎪ΔGV⎪
channel balance
−
−
1
dB
SVRR
supply voltage ripple rejection
on
46
−
−
dB
mute
46
−
−
dB
note 4
80
−
−
dB
50
60
75
kΩ
on; RS = 0 Ω
−
50
−
μV
on; RS = 10 kΩ
−
70
100
μV
mute; note 6
−
50
−
μV
standby
⎪Zi⎪
input impedance
Vn(o)(rms)
noise output voltage (RMS value)
note 5
αcs
channel separation
RS = 10 kΩ
40
55
−
dB
Vo(mote)
output voltage in mute
note 7
−
−
2
mV
THD = 1%
5
6.6
−
W
THD = 10%
6.5
8.0
−
W
BTL application; note 8
PO
output power
note 2
THD
total harmonic distortion
Po = 1 W
−
0.03
−
%
fro(L)
low frequency roll-off
−1 dB; note 3
−
25
−
Hz
fro(H)
high frequency roll off
−1 dB
20
−
−
kHz
25
26
27
dB
on
50
−
−
dB
mute
50
−
−
dB
GV
voltage gain
SVRR
supply voltage ripple rejection
note 4
standby
⎪Zi⎪
input impedance
Vn(o)(rms)
noise output voltage (RMS value)
Vo(mute)
2001 Apr 17
output voltage in mute
80
−
−
dB
25
30
38
kΩ
note 5
on; RS = 0 Ω
−
70
−
μV
on; RS = 10 kΩ
−
100
200
μV
mute; note 6
−
60
−
μV
note 7
−
−
2
mV
6
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
Notes to the characteristics
1. RL = 4 Ω, measured in Fig.4.
2. Output power is measured directly at the output pins of the IC.
3. Frequency response externally fixed.
4. Vripple = Vripple(max) = 2 V (p-p); RS = 0 Ω.
5. Noise voltage measured in a bandwidth of 20 Hz to 20 kHz.
6. Noise output voltage independent of RS.
7. Vi = Vi(max) = 1 V (RMS).
8. RL = 8 Ω, measured in Fig.3.
APPLICATION INFORMATION
VCC
1000
μF
handbook, full pagewidth
100
nF
15
TDA1517ATW
16
3
8
Ri
60 kΩ
A
+OUT
9
470 nF
RL
8Ω
+IN1
12
Ri
60 kΩ
VCC
B
−OUT
13
18
10 kΩ
MODE 17
μc1
MICROCONTROLLER
μc2
μc1 μc2
0
On
0
1
Mute
0
0
Standby 1
8.2
kΩ
5
STANDBY/
MUTE LOGIC
VCC
SHORT CIRCUIT
AND
TEMPERATURE
PROTECTION
15 kΩ
15 kΩ
input
reference
voltage
4
10
SGND
Fig.3 BTL application block diagram.
2001 Apr 17
7
11
PGND
MGU304
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
VCC
handbook, full pagewidth
100
nF
15
TDA1517ATW
1000
μF
16
3
8
220 nF
IN1+
220 nF
IN2−
Ri
60 kΩ
A
Ri
60 kΩ
B
9
1000 μF
+OUT
18
12
VCC
13
1000 μF
−OUT
10 kΩ
MODE 17
μc1
MICROCONTROLLER
μc2
8.2
kΩ
100
μF
RL
4Ω
5
STANDBY/
MUTE LOGIC
VCC
SHORT CIRCUIT
AND
TEMPERATURE
PROTECTION
15 kΩ
15 kΩ
μc1 μc2
0
On
0
1
Mute
0
0
Standby 1
RL
4Ω
input
reference
voltage
4
10
SGND
11
PGND
MGU305
Fig.4 SE application block diagram.
Test conditions
Proper supply bypassing is critical for low noise
performance and high power supply rejection. The
respective capacitor locations should be as close as
possible to the device and grounded to the power ground.
Decoupling the power supply also prevents unwanted
oscillations. For suppressing higher frequency transients
(spikes) on the supply line a capacitor with low ESR
(typical 0.1 μF) has to be placed as close as possible to the
device. For suppressing lower frequency noise and ripple
signals, a large electrolytic capacitor (e.g. 1000 μF or
greater) must be placed close to the IC.
Tamb = 25 °C; unless otherwise specified: VP = 12 V, BTL
application, f = 1 kHz, RL = 8 Ω, fixed gain = 26 dB, audio
band-pass: 22 Hz to 22 kHz. In the figures as a function of
frequency a band-pass of 10 Hz to 80 kHz was applied.
The BTL application block diagram is shown in Fig.3. The
PCB layout [which accommodates both the mono (BTL)
and stereo (single-ended) application] is shown in Fig.6.
Printed-Circuit Board (PCB) layout and grounding
For high system performance levels certain grounding
techniques are imperative. The input reference grounds
have to be tied to their respective source grounds and
must have separate traces from the power ground traces;
this will separate the large (output) signal currents from
interfering with the small AC input signals. The small signal
ground traces should be located physically as far as
possible from the power ground traces. Supply and output
traces should be as wide as possible for delivering
maximum output power.
2001 Apr 17
In single-ended (stereo) application a bypass capacitor
connected to pin SVR reduces the noise and ripple on the
midrail voltage. For good THD and noise performance a
low ESR capacitor is recommended.
Input configuration
It should be noted that the DC level of the input pins is
approximately 2.1 V; a coupling capacitor is therefore
necessary.
8
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
The formula for the cut-off frequency at the input is as
1
follows: f IC = -----------------------------2 × π × Ri Ci
Average listening level without any distortion yields:
P tot
5
P ALL = ---------------- = --------------- = 315 mW
factor
15.85
1
thus f IC = ------------------------------------------------------------------------------ = 11 Hz
–3
–9
2 × π × 30 × 10 × 470 × 10
The power dissipation can be derived from Fig.11 for 0 dB
and 12 dB headroom.
As can be seen it is not necessary to use high capacitor
values for the input; so the delay during switch-on, which
is necessary for charging the input capacitors, can be
minimized. This results in a good low frequency response
and good switch-on behaviour.
Table 1
RATING
HEADROOM
POWER
DISSIPATION
0 dB
12 dB
3.5 W
2.0 W
Po = 5 W
(THD = 0.1%)
In stereo applications (single-ended) coupling capacitors
on both input and output are necessary. It should be noted
that the outputs of both amplifiers are in opposite phase.
Thus for the average listening level (music power) a power
dissipation of 2.0 W can be used for the thermal PCB
calculation; see Section “Thermal behaviour (PCB design
considerations)”.
Built-in protection circuits
The IC contains two types of protection circuits:
• Short-circuits the outputs to ground, the supply to
ground and across the load: short-circuit is detected and
controlled by a SOAR protection circuit
Mode pin
For the 3 functional modes: standby, mute and operate,
the MODE pin can be driven by a 3-state logic output
stage, e.g. a microcontroller with some extra components
for DC-level shifting; see Fig.10 for the respective
DC levels.
• Thermal shut-down protection: the junction temperature
is measured by a temperature sensor. Thermal foldback
is activated at a junction temperature of >150 °C.
• Standby mode is activated by a low DC level between
0 and 2 V. The power consumption of the IC will be
reduced to <0.12 mW.
Output power
The output power as a function of supply voltage has been
measured on the output pins and at THD = 10%. The
maximum output power is limited by the maximum
allowable power dissipation and the maximum available
output current, 2.5 A repetitive peak current.
• Mute mode is activated by a DC level between
3.3 and 6.4 V. The outputs of the amplifier will be muted
(no audio output); however the amplifier is DC biased
and the DC level of the output pins stays at half the
supply voltage. The input coupling capacitors are
charged when in mute mode to avoid pop-noise.
Supply voltage ripple rejection
• The IC will be in the operating condition when the
voltage at pin MODE is between 8.5 V and VCC.
The SVRR has been measured without an electrolytic
capacitor on pin 5 and at a bandwidth of 10 Hz to 80 kHz.
The curves for operating and mute condition (respectively)
were measured with Rsource = 0 Ω. Only in single-ended
applications is an electrolytic capacitor (e.g. 100 μF) on
pin 5 necessary to improve the SVRR behaviour.
Switch-on/switch-off
To avoid audible plops during switch-on and switch-off of
the supply voltage, the MODE pin has to be set in standby
condition (VCC level) before the voltage is applied
(switch-on) or removed (switch-off). The input and SVRR
capacitors are smoothly charged during mute mode.
Headroom
A typical music CD requires at least 12 dB (is factor 15.85)
dynamic headroom (compared with the average power
output) for passing the loudest portions without distortion.
The following calculation can be made for this application
at VP = 12 V and RL = 8 Ω: Po at THD = 0.1% is
approximately 5 W (see Fig.7).
2001 Apr 17
Power rating
The turn-on and turn-off time can be influenced by an
RC-circuit connected to the MODE pin. Switching the
device or the MODE pin rapidly on and off may cause ‘click
and pop’ noise. This can be prevented by proper timing on
the MODE pin. Further improvement in the BTL application
can be obtained by connecting an electrolytic capacitor
(e.g. 100 μF) between the SVRR pin and signal ground.
9
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
The thermal vias (0.3 mm ∅) in the ‘thermal land’ should
not use web construction techniques, because those will
have high thermal resistance; continuous connection
completely around the via-hole is recommended.
Thermal behaviour (PCB design considerations)
The typical thermal resistance [Rth(j-a)] of the IC in the
HTSSOP20 package is 37 K/W if the IC is soldered on a
printed-circuit board with double sided 35 μm copper with
a minimum area of approximately 30 cm2. The actual
usable thermal resistance depends strongly on the
mounting method of the device on the printed-circuit
board, the soldering method and the area and thickness of
the copper on the printed-circuit board.
For a maximum ambient temperature of 60 °C the
following calculation can be made: for the application at
VP = 12 V and RL = 8 Ω the (ALL-) music power
dissipation approximately 2.0 W;
Tj(max) = Tamb + P × Rth(j-a) = 60 °C + 2.0 × 37 = 134 °C.
Note: the above calculation holds for application at
‘average listening level’ music output signals. Applying (or
testing) with sine wave signals will produce approximately
twice the music power dissipation; at worst case condition
this can activate the maximum temperature protection.
The bottom ‘heat-spreader’ of the IC has to be soldered
efficiently on the ‘thermal land’ of the copper area of the
printed-circuit board using the re-flow solder technique.
A number of thermal vias in the ‘thermal land’ provide a
thermal path to the opposite copper site of the
printed-circuit board. The size of the surface layers should
be as large as needed to dissipate the heat.
handbook, full pagewidth
TDA1517ATW
60
K/W
50
ON-BOARD-COOLING
COPPER DESIGN
40
CU-LAYER 1
Rth(j-a)
30
L
L
20
Rth(j-p)
CU-LAYER 2-4
10
0
0
1
2
3
4
number of 35 μm copper layers
MGU306
Rth(j-p) curve is given for practical calculation purpose.
L = 30 mm plus vias
Fig.5 Thermal resistance of the HTSSOP20 mounted on printed-circuit board.
2001 Apr 17
10
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
handbook, full pagewidth
top view
top copper layout
top view
bottom copper layout
+VP
TDA
1517ATW
1000 μF
25 V
100 nF
220 nF
IN1
IN2
Std By
100 μF/16 V
On
1000 μF
16 V
sept −2000
+ OUT1
− OUT2
MGU312
top view
component layout
For BTL applications the two 1000 μF/16 V capacitors must be replaced by 0 Ω jumpers.
Fig.6 Printed-circuit board layout for BTL and SE application.
2001 Apr 17
11
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
Typical performance characteristics for BTL
application at VP = 12 V and RL = 8 Ω
MGU307
10
MGU308
10
handbook, halfpage
handbook, halfpage
THD
(%)
THD
(%)
1
1
10−1
10−1
10−2
10−2
10−1
1
10−2
10−2
10
Po (W)
10−1
1
102
10
f (kHz)
Fig.7 THD as a function of Po.
Fig.8 THD as a function of frequency.
MGU309
0
Po = 1 W
MGU310
10
Vo
(V)
handbook, halfpage
handbook, halfpage
SVRR
(dB)
1
−20
10−1
−40
10−2
−60
10−3
mute
−80
10−2
10−1
10−4
1
102
10
f (kHz)
Fig.9 SVRR as a function of frequency.
2001 Apr 17
0
2
4
6
8
10
12
VMODE (V)
Fig.10 Vo as a function of VMODE.
12
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
MGU311
6
MGU323
12
handbook, halfpage
handbook, halfpage
Po
(W)
P
(W)
5
10
VP = 12 V
RL = 8 Ω
4
8
3
RL = 4 Ω
6
VP = 15 V
RL = 16 Ω
2
8Ω
16 Ω
4
1
2
0
0
2
4
6
8
0
10
6
Po (W)
Fig.11 Power dissipation as a function of Po.
2001 Apr 17
8
10
12
14
18
16
VP (V)
Fig.12 Po as a function of VP.
13
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
PACKAGE OUTLINE
HTSSOP20: plastic thermal enhanced thin shrink small outline package; 20 leads;
body width 4.4 mm; exposed die pad
SOT527-1
E
D
A
X
c
y
HE
exposed die pad side
v M A
Dh
Z
11
20
(A 3)
A2
Eh
pin 1 index
A
A1
θ
Lp
L
1
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
Dh
E(2)
Eh
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.20
0.09
6.6
6.4
4.3
4.1
4.5
4.3
3.1
2.9
0.65
6.6
6.2
1
0.75
0.50
0.2
0.13
0.1
0.5
0.2
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT527-1
2001 Apr 17
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-04-07
05-11-02
MO-153
14
o
NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2001 Apr 17
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NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2001 Apr 17
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NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
TDA1517ATW
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2001 Apr 17
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NXP Semiconductors
Product specification
8 W BTL or 2 × 4 W SE power amplifier
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2001 Apr 17
TDA1517ATW
18
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version. The Ordering information was modified accordingly.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp19
Date of release: 2001 Apr 17
Document order number:
9397 750 08264