NTD4904N D

NTD4904N
Power MOSFET
30 V, 79 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
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RDS(on) MAX
V(BR)DSS
Applications
3.7 mW @ 10 V
30 V
• CPU Power Delivery
• DC−DC Converters
ID MAX
79 A
5.5 mW @ 4.5 V
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
TA = 25°C
Unit
VDSS
30
V
VGS
"20
V
ID
17.8
A
TA = 100°C
PD
2.6
W
Continuous Drain
Current (RqJA) (Note
2)
TA = 25°C
ID
13
A
Continuous Drain
Current (RqJC)
(Note 1)
tp=10ms
Current Limited by Package
TA = 25°C
PD
1.4
W
TC = 25°C
ID
79
A
PD
52
W
TA = 25°C
IDM
316
A
TA = 25°C
IDmaxPkg
90
A
TJ, Tstg
−55 to
175
°C
Source Current (Body Diode)
IS
47
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
L = 0.1 mH, IL(pk) = 37 A, RG = 25 W)
EAS
68.4
mJ
TL
260
°C
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
1 2
1
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
2 3
1
2
3
CASE 369AD
CASE 369D
IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
56
TC = 25°C
Operating Junction and Storage Temperature
4
3
9.2
TC = 100°C
Power Dissipation
(RqJC) (Note 1)
Pulsed Drain Current
TA = 100°C
4
4
TA = 25°C
Power Dissipation
(RqJA) (Note 2)
S
12.6
Power Dissipation
(RqJA) (Note 1)
Steady
State
N−Channel
G
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
4
Drain
AYWW
49
04NG
Gate−to−Source Voltage
Continuous Drain
Current (RqJA)
(Note 1)
Value
AYWW
49
04NG
Drain−to−Source Voltage
Symbol
AYWW
49
04NG
Parameter
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
A
Y
WW
4904N
G
= Assembly Location
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 2
1
Publication Order Number:
NTD4904N/D
NTD4904N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
RqJC
2.9
°C/W
Junction−to−Case (Drain)
Junction−to−Tab (Drain)
RqJC−TAB
4.3
Junction−to−Ambient − Steady State (Note 1)
RqJA
57
Junction−to−Ambient − Steady State (Note 2)
RqJA
108
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
15
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
"100
nA
2.2
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
gFS
1.6
4.0
VGS = 10 V
VGS = 4.5 V
Forward Transconductance
1.0
ID = 30 A
3.0
ID = 15 A
3.0
ID = 30 A
4.0
ID = 15 A
4.0
VDS = 1.5 V, ID = 30 A
mV/°C
3.7
mW
5.5
76
S
3052
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
23
Total Gate Charge
QG(TOT)
16.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz,
VDS = 15 V
VGS = 4.5 V, VDS = 15 V,
ID = 30 A
976
nC
4.4
8.2
3.0
VGS = 10 V, VDS = 15 V,
ID = 30 A
41
nC
15.3
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
19.8
23.4
tf
7.5
td(on)
10.3
tr
td(off)
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20
28.7
8.0
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
ns
NTD4904N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TJ = 25°C
0.84
1.1
V
TJ = 125°C
0.7
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
ns
40.4
VGS = 0 V, dIs/dt= 100 A/ms,
IS = 30 A
20.5
19.9
QRR
35
nC
Source Inductance (Note 5)
LS
2.48
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK (Note 5)
LD
Gate Inductance (Note 5)
LG
4.9
Gate Resistance
RG
1.0
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
2.0
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Assume terminal length of 110 mils.
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3
NTD4904N
TYPICAL PERFORMANCE CURVES
ID, DRAIN CURRENT (AMPS)
3.6 V
3.4 V
3.8 V to 6 V
3.2 V
3.0 V
2.8 V
2.6 V
2.4 V
0
1
2
4
3
5
TJ = 25°C
TJ = −55°C
2.5
3
3.5
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.010
0.008
0.006
0.004
3
4
6
5
7
8
10
9
0.006
TJ = 25°C
0.005
VGS = 4.5 V
0.004
VGS = 10 V
0.003
0.002
20
40
60
80
100
120
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
2.2
2.0
TJ = 125°C
2
ID = 30 A
TJ = 25°C
0.002
VDS ≥ 10 V
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.012
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 150°C
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
130
TJ = 25°C
10 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
1.6
1.4
1.2
1.0
1000
TJ = 125°C
100
TJ = 85°C
0.8
0.6
−50 −25
10
0
25
50
75
100
125
150
175
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
30
NTD4904N
TYPICAL PERFORMANCE CURVES
C, CAPACITANCE (pF)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
3600
TJ = 25°C
VGS = 0 V
Ciss
3200
2800
2400
2000
1600
Coss
1200
800
400
Crss
0
0
5
10
15
20
25
30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
11
10
9
8
7
6
VGS
5
QGS
4
3
2
VDD = 15 V
VGS = 10 V
ID = 30 A
TJ = 25°C
0
15
20
25
10
30
35
QG, TOTAL GATE CHARGE (nC)
5
40
45
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
VDD = 15 V
ID = 15 A
VGS = 10 V
IS, SOURCE CURRENT (AMPS)
1000
td(off)
tf
100
tr
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
25
20
15
TJ = 125°C
10
5
TJ = 25°C
0
0.4
1
100
100 ms
VGS = 10 V
SINGLE PULSE
TC = 25°C
1
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
10
0.6
0.7
0.8
0.9
1.0
Figure 10. Diode Forward Voltage vs. Current
1000
100
0.5
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
I D, DRAIN CURRENT (AMPS)
QGD
1
0
Figure 7. Capacitance Variation
t, TIME (ns)
QT
70
ID = 37 A
60
50
40
30
20
10
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4904N
TYPICAL PERFORMANCE CURVES
100
R(t) (C/W)
10
50% (DUTY CYCLE)
20%
10%
5.0%
2.0%
1.0
1.0%
0.1
SINGLE PULSE
0.01
PSi TAB-A
0.001
0.000001
0.0001
0.00001
0.001
0.01
1.0
0.1
10
100
1000
PULSE TIME (s)
Figure 13. FET Thermal Response
110
VDS = 1.5 V
100
90
80
GFS (S)
70
60
50
40
30
20
10
0
0
10
20
30
40
50 60
ID (A)
70
80
90
100
Figure 14. GFS vs ID
ORDERING INFORMATION
Package
Shipping†
NTD4904NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4904N−1G
IPAK
(Pb−Free)
75 Units / Rail
NTD4904N−35G
IPAK Trimmed Lead
(Pb−Free)
75 Units / Rail
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NTD4904N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD4904N
PACKAGE DIMENSIONS
C
B
V
IPAK (STRAIGHT LEAD DPAK)
CASE 369D
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
M
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
3 PL
0.13 (0.005)
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
T
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD
ISSUE B
E
A
E3
L2
E2
A1
D2
D
L1
L
T
SEATING
PLANE
NOTES:
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
A1
b1
2X
e
A2
3X
E2
b
0.13
M
T
D2
DIM
A
A1
A2
b
b1
D
D2
E
E2
E3
e
L
L1
L2
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.60
0.87
1.10
0.69
0.89
0.77
1.10
5.97
6.22
4.80
−−−
6.35
6.73
4.57
5.45
4.45
5.46
2.28 BSC
3.40
3.60
−−−
2.10
0.89
1.27
OPTIONAL
CONSTRUCTION
ON Semiconductor and
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For additional information, please contact your local
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NTD4904N/D