NTD4959N Power MOSFET 30 V, 58 A, Single N−Channel, DPAK/IPAK Features Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS Applications • CPU Power Delivery • DC−DC Converters • Low Side Switching RDS(on) MAX 9.0 mW @ 10 V 30 V D Value Unit VDSS 30 V VGS "20 V ID 11.5 A S 4 Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C PD 2.0 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 9.0 A Power Dissipation (RqJA) (Note 2) TA = 85°C Steady State Continuous Drain Current (RqJC) (Note 1) TC = 25°C Power Dissipation (RqJC) (Note 1) TC = 25°C Pulsed Drain Current 9.0 TA = 85°C TA = 25°C 7.0 PD ID TC = 85°C tp=10ms Current Limited by Package 1.3 W A 58 45 52 TA = 25°C IDM 130 A TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C Source Current (Body Diode) 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AD CASE 369D IPAK IPAK (Straight Lead) (Straight Lead DPAK) W IS 43 A dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 13.5 A, RG = 25 W) EAS 91.0 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Drain to Source dV/dt 4 4 1 2 PD Operating Junction and Storage Temperature N−Channel G Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW 49 59NG Gate−to−Source Voltage Symbol YWW 49 59NG Drain−to−Source Voltage 58 A 14 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX 4 Drain YWW 49 59NG • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4959N G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 1 1 Publication Order Number: NTD4959N/D NTD4959N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 2.9 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 74 Junction−to−Ambient − Steady State (Note 2) RqJA 116 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 25 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 5.7 VGS = 10 to 11.5 V ID = 30 A 7.0 ID = 15 A 7.0 VGS = 4.5 V ID = 30 A 12 ID = 15 A 11 VDS = 15 V, ID = 15 A mV/°C 9.0 mW 14 9.0 S 1456 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge VGS = 0 V, f = 1.0 MHz, VDS = 12 V 200 11 VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 315 13 nC 2.5 4.8 5.0 VGS = 11.5 V, VDS = 15 V, ID = 30 A 25 nC 12.3 ns SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 21.3 15.1 tf 5.3 td(on) 7.0 tr td(off) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 22.7 25.3 2.8 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4959N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.95 1.2 V TJ = 125°C 0.83 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 19.5 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 10.7 8.8 QRR 9.2 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 2.4 PACKAGE PARASITIC VALUES TA = 25°C http://onsemi.com 3 1.88 W NTD4959N TYPICAL PERFORMANCE CURVES 100 6V 6.5 V 5.5 V 120 TJ = 25°C 5V 90 80 VDS ≥ 10 V 4.5 V 70 60 4.2 V 50 40 4V 3.8 V 30 20 3.6 V 3.4 V 3.2 V 0 1 3 2 4 60 40 5 TJ = 125°C TJ = 25°C 20 TJ = −55°C 0 2 1 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 80 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.045 0 100 0 3 4 5 6 7 8 9 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 10 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 7V 0.020 TJ = 25°C 0.015 VGS = 4.5 V 0.010 VGS = 11.5 V 0.005 0 10 15 20 25 30 35 40 45 50 55 60 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100,000 2.0 VGS = 0 V ID = 30 A VGS = 10 V TJ = 175°C 10,000 IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 110 ID, DRAIN CURRENT (AMPS) 120 1.5 1.0 0.5 −50 −25 1000 TJ = 125°C 100 10 0 25 50 75 100 125 150 175 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 25 NTD4959N TYPICAL PERFORMANCE CURVES VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) TJ = 25°C Ciss 2000 Ciss 1500 Crss 1000 500 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 20 12 11 10 9 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) 2500 25 8 7 6 5 3 ID = 30 A 2 0 V < VGS < 11.5 V 1 TJ = 25°C 0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation IS, SOURCE CURRENT (AMPS) t, TIME (ns) 30 VDD = 15 V ID = 30 A VGS = 11.5 V 100 td(off) tr 10 1 td(on) tf 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 15 10 5 0 0.5 100 100 ms 1 0.1 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 10 ms VGS = 20 V SINGLE PULSE TC = 25°C 0.8 0.9 0.6 0.7 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage vs. Current 1000 10 TJ = 25°C 20 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 Q2 Q1 4 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 QT 120 ID = 15 A 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4959N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 0.1 1 100 10 PULSE WIDTH (ms) 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4959NT4G DPAK (Pb−Free) 2500 Tape & Reel NTD4959N−1G IPAK (Pb−Free) 75 Units/Rail NTD4959N−35G IPAK Trimmed Lead (3.5 " 0.15 mm) (Pb−Free) 75 Units/Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4959N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B A E b3 c2 B D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 3 Z H DETAIL A DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4959N PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O A E E3 L2 E2 A1 D2 D L1 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 L T SEATING PLANE A1 b1 2X e A2 3X b 0.13 M E2 T D2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 OPTIONAL CONSTRUCTION IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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