NTD4959NH Power MOSFET 30 V, 58 A, Single N−Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS Applications RDS(on) MAX 9.0 mW @ 10 V 30 V • CPU Power Delivery • DC−DC Converters • Low Side Switching ID MAX 58 A 12.5 mW @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS "20 V ID 11.5 A Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C PD 2.0 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 9.0 A 9.0 TA = 85°C 7.0 TA = 25°C PD 1.3 W Continuous Drain Current (RqJC) (Note 1) TC = 25°C ID 58 A Power Dissipation (RqJC) (Note 1) TC = 25°C PD 52 W TA = 25°C IDM 130 A TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C IS 43 A dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 15 A, RG = 25 W) EAS 112.5 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Pulsed Drain Current TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt 45 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4 4 1 2 1 3 DPAK CASE 369AA (Bent Lead) STYLE 2 2 3 3 IPAK IPAK CASE 369AD CASE 369D (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 49 59NHG Steady State S YWW 49 59NHG Power Dissipation (RqJA) (Note 2) TA = 85°C N−Channel G YWW 49 59NHG Parameter 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y = Year WW = Work Week 4959NH= Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 0 1 Publication Order Number: NTD4959NH/D NTD4959NH THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 2.9 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 74 Junction−to−Ambient − Steady State (Note 2) RqJA 116 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 25 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 2.1 5.7 VGS = 10 to 11.5 V ID = 30 A 7.0 ID = 15 A 7.0 VGS = 4.5 V ID = 30 A 10.45 ID = 15 A 9.95 VDS = 15 V, ID = 15 A mV/°C 9.0 mW 12.5 9.0 S CHARGES AND CAPACITANCES Input Capacitance Ciss 2155 331 447 190 294 12.5 15 VGS = 4.5 V, VDS = 15 V, ID = 30 A 2.4 3.6 5.3 7.9 5.1 7.7 VGS = 11.5 V, VDS = 15 V, ID = 30 A 29.3 44 nC 12.0 18 ns 20 30 14 21 tf 5.0 7.5 td(on) 7.0 10.4 18 27 Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge pF 1596 VGS = 0 V, f = 1.0 MHz, VDS = 12 V QGD QG(TOT) nC SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 22 33 3.0 4.6 ns NTD4959NH ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.95 1.2 V TJ = 125°C 0.83 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 15.6 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 10.6 5.0 QRR 7.5 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.75 PACKAGE PARASITIC VALUES TA = 25°C http://onsemi.com 3 1.88 W NTD4959NH TYPICAL PERFORMANCE CURVES 5.5 V to 10 V ID, DRAIN CURRENT (AMPS) 90 80 TJ = 25°C 80 70 60 4V 50 3.8 V 40 3.6 V 30 3.4 V 20 3.2 V 3V 10 0 1 4 3 2 5 0.012 0.011 0.010 0.009 0.008 0.007 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 TJ = 125°C 20 TJ = 25°C 10 TJ = −55°C 2 1 3 4 5 0.020 TJ = 25°C 0.018 0.016 0.014 VGS = 4.5 V 0.012 0.010 0.008 VGS = 11.5 V 0.006 0.004 0.002 0 10 15 20 25 30 35 40 45 50 55 60 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 30 Figure 2. Transfer Characteristics 0.013 1.6 1.5 1.4 40 Figure 1. On−Region Characteristics 0.014 1.8 1.7 50 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID = 30 A TJ = 25°C 3.5 60 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.015 0.006 VDS ≥ 10 V 70 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 4.5 V ID, DRAIN CURRENT (AMPS) 100 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 −50 −25 0 25 50 75 100 125 150 175 VGS = 0 V 1000 TJ = 150°C 100 TJ = 125°C 10 1 0.1 TJ = 25°C 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 30 NTD4959NH C, CAPACITANCE (pF) 2000 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES TJ = 25°C Ciss 1500 1000 500 0 Coss Crss 0 5 10 15 20 25 30 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 12 QT 10 VGS 8 6 Qgs 4 2 0 0 Figure 7. Capacitance Variation IS, SOURCE CURRENT (AMPS) t, TIME (ns) 10 td(on) tf 1 VDD = 15 V ID = 30 A VGS = 11.5 V 10 RG, GATE RESISTANCE (OHMS) 15 10 5 10 ms 100 ms 10 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage vs. Current VGS = 20 V SINGLE PULSE TC = 25°C 100 TJ = 25°C 20 0 0.5 100 10 ms dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 30 VGS = 0 V 25 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) 30 tr td(off) 1000 5 VDD = 15 V 0 V ≤ VGS ≤ 11.5 V ID = 30 A TJ = 25°C Figure 8. Gate−to−Source Voltage vs. Total Charge 100 1 Qgd 120 ID = 15 A 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4959NH TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 1 10 100 PULSE WIDTH (ms) 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4959NHT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4959NH−1G IPAK (Pb−Free) 75 Units / Rail NTD4959NH−35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4959NH PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369AA−01 ISSUE A −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 A S 1 2 3 DIM A B C D E F H J L R S U V Z Z H U F J L D 2 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD4959NH PACKAGE DIMENSIONS IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B C B V E R 4 1 2 DIM A B C D E F G H J K R S V Z Z A S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3 −T− SEATING PLANE K J F D G H M T 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O A E E3 L2 D2 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. L T SEATING PLANE E2 A1 D L1 A1 b1 2X e A2 3X b 0.13 M MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− E2 T D2 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 OPTIONAL CONSTRUCTION ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD4959NH/D