IRF3305 Data Sheet (268 KB, EN)

PD - 95758A
IRF3305PbF
Features
l Designed to support Linear Gate Drive
Applications
l 175°C Operating Temperature
l Low Thermal Resistance Junction - Case
l Rugged Process Technology and Design
l Fully Avalanche Rated
l Lead-Free
HEXFET® Power MOSFET
D
VDSS = 55V
RDS(on) = 8.0mΩ
G
ID = 75A
S
Description
This HEXFET Power MOSFET utilizes a rugged
planar process technology and device design,
which greatly improves the Safe Operating Area
(SOA) of the device. These features, coupled
with 175°C junction operating temperature and
"low thermal resistance of 0.45C/W"
TO-220AB
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
140
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
IDM
75
560
PD @TC = 25°C Power Dissipation
330
W
2.2
± 20
W/°C
V
470
mJ
99
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
d
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
c
IAR
Avalanche Current
EAR
TJ
Repetitive Avalanche Energy
TSTG
Storage Temperature Range
g
h
860
See Fig.12a, 12b, 15, 16
Mounting Torque, 6-32 or M3 screw
-55 to + 175
°C
300 (1.6mm from case )
y
i
Parameter
Junction-to-Case
RθCS
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
RθJA
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i
y
10 lbf in (1.1N m)
Thermal Resistance
RθJC
A
mJ
Operating Junction and
Soldering Temperature, for 10 seconds
A
Typ.
Max.
–––
0.45
0.50
–––
–––
62
Units
°C/W
1
07/23/10
IRF3305PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
gfs
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
IGSS
Min. Typ. Max. Units
V
V/°C
mΩ
V
S
µA
Conditions
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
55
–––
–––
2.0
41
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.055
–––
–––
–––
–––
–––
–––
–––
100
21
45
16
88
43
34
4.5
–––
–––
8.0
4.0
–––
25
250
200
-200
150
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
3650
1230
450
4720
930
1490
–––
–––
–––
–––
–––
–––
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 44V
nA
nC
ns
nH
pF
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 75A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 75A
VDS = 55V, VGS = 0V
VDS = 55V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
ID = 75A
VDS = 44V
VGS = 10V
VDD = 28V
ID = 75A
RG = 2.6 Ω
VGS = 10V
Between lead,
e
e
e
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
75
ISM
(Body Diode)
Pulsed Source Current
–––
–––
560
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
57
130
1.3
86
190
c
Conditions
MOSFET symbol
A
V
ns
nC
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V
TJ = 25°C, IF = 75A, VDD = 28V
di/dt = 100A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
„ Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
‚ Limited by TJmax, starting TJ = 25°C, L = 0.17mH … Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 75A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
† This value determined from sample failure population. 100%
ƒ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
tested to this value in production.
„ Coss eff. is a fixed capacitance that gives the
‡ Rθ is measured at TJ of approximately 90°C.
same charging time as Coss while VDS is rising
from 0 to 80% VDSS .
 Repetitive rating; pulse width limited by
2
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IRF3305PbF
1000
BOTTOM
TOP
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 175°C
10
10
0.1
1
10
100
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
80
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current(Α)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100.0
TJ = 175°C
10.0
TJ = 25°C
1.0
VDS = 25V
≤ 60µs PULSE WIDTH
TJ = 25°C
60
TJ = 175°C
40
20
VDS = 10V
380µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8.0
0
0
20
40
60
80
100
120
140
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRF3305PbF
7000
VGS, Gate-to-Source Voltage (V)
6000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
5000
Ciss
4000
3000
Coss
2000
1000
ID= 75A
16
12
8
4
Crss
0
0
1
10
0
100
80
1000.0
10000
ID, Drain-to-Source Current (A)
TJ = 175°C
100.0
10.0
TJ = 25°C
1.0
1000
100
100µsec
10
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
DC
0.1
0.1
0.4
0.8
1.2
1.6
160
OPERATION IN THIS AREA
LIMITED BY R DS(on)
VGS = 0V
0.0
120
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
ISD, Reverse Drain Current (A)
40
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 44V
VDS= 28V
2.4
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3305PbF
140
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.5
LIMITED BY PACKAGE
ID , Drain Current (A)
120
100
80
60
40
20
0
25
50
75
100
125
150
ID = 75A
VGS = 10V
2.0
1.5
1.0
0.5
175
-60 -40 -20
TC , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
1
Thermal Response ( ZthJC )
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
τJ
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
Ci= τi/Ri
Ci i/Ri
0.001
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
0.1758 0.00045
0.228
0.004565
0.0457
0.01858
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
DRIVER
L
VDS
D.U.T
RG
20V
VGS
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
IRF3305PbF
2000
I D
18A
26A
BOTTOM 75A
TOP
1600
1200
800
400
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
VGS(th) Gate threshold Voltage (V)
10 V
ID = 5.0A
ID = 1.0A
ID = 250µA
3.5
3.0
2.5
2.0
1.5
VCC
1.0
-75 -50 -25
0
25
50
75
100 125 150 175
TJ , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF3305PbF
Avalanche Current (A)
10000
Duty Cycle = Single Pulse
1000
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
100
0.05
0.10
10
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
500
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
400
300
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF3305PbF
D.U.T
Driver Gate Drive
ƒ
+
‚
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF3305PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
ASS EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line position
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB package is not recommended for Surface Mount Application
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
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9