Family Characteristics for MECL 10H and MECL 10K

TND309
General Information for
MECL 10H and MECL 10K
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APPLICATION NOTE
High–Speed Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MECL Products . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MECL Family Comparison . . . . . . . . . . . . . . . . . . 3
Basic Design Considerations . . . . . . . . . . . . . . . . 4
Definitions of Symbols & Abbreviations . . . . . . . 6
Pin Conversion Tables . . . . . . . . . . . . . . . . . . . . . 9
MECL Positive and Negative Logic . . . . . . . . . . 10
Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Characteristics . . . . . . . . . . . . . . . . . . .
Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Parameters . . . . . . . . . . . . . . . . . . . . .
Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing MECL 10H and 10K . . . . . . . . . . . . . . . .
 Semiconductor Components Industries, LLC, 2002
June, 2002 – Rev. 1
Operational Data . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Design Considerations . . . . . . . . . . . . . .
Thermal Management . . . . . . . . . . . . . . . . . . . . .
Optimizing Reliability . . . . . . . . . . . . . . . . . . . . . .
Thermal Effects on Noise Margin . . . . . . . . . . .
Mounting and Heatsink . . . . . . . . . . . . . . . . . . . .
Circuit Interconnects . . . . . . . . . . . . . . . . . . . . . .
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Publication Order Number:
TND309/D
TND309
HIGH–SPEED LOGIC
High speed logic is used whenever improved system
performance would increase a product’s market value. For
a given system design, high–speed logic is the most direct
way to improve system performance and Emitter–Coupled
Logic (ECL) is one of today’s fastest forms of digital logic.
Emitter– coupled logic offers both the logic speed and logic
features to meet the market demands for higher performance
systems.
increasing the speed in critical timing areas. Also, many
MECL 10H devices are pin out/functional duplications of
the MECL 10K series devices. The emphasis of this family
will be placed on more powerful logic functions having
more complexity and greater performance. With 1.0 ns
propagation delays and 25 mW per gate, MECL 10H is one
of the best speed–power families of any ECL logic family
available today.
MECL Products
ON Semiconductor (formerly a division of Motorola SPS),
introduced the original monolithic emitter–coupled logic
family with MECL I (1962) and followed this with MECL II
(1966). These two families are now obsolete and have given
way to the MECL III (MC1600 series), MECL 10K,
PLL (MC12000 series) and the new MECL 10H families.
Chronologically the third family introduced, MECL III
(1968) is a higher power, higher speed logic. Typical 1.0 ns
edge speeds and propagation delays along with greater than
500 MHz flip–flop toggle rates, make MECL III useful for
high–speed test and communications equipment. Also, this
family is used in the high–speed sections and critical timing
delays of larger systems. For more general purpose
applications, however, trends in large high–speed systems
showed the need for an easy–to–use logic family with
propagation delays on the order of 2.0 ns. To match this
requirement, the MECL 10,000 Series was introduced in
1971.
An important feature of MECL 10K is its compatibility
with MECL III to facilitate using both families in the same
system. A second important feature is its significant power
economy – MECL 10K gates use less than one–half the
power of MECL III.
The MECL 10H product family was introduced in 1981.
This latest MECL family features 100% improvements in
propagation delay and clock speeds while maintaining
power supply currents equal to MECL 10K. MECL 10H is
voltage compensated allowing guaranteed DC and
switching parameters over a ±5% power supply range. Noise
margins have been improved by 75% over the MECL 10K
series.
Compatibility with MECL 10K and MECL III is a key
element in allowing users to enhance existing systems by
MECL at +5.0 V (PECL – Positive ECL)
Any single supply ECL device is also a PECL device,
making the PECL portfolio as large as the existing ECL one.
(Note: The dual supply translator devices cannot operate at
+5.0 V and ground and cannot be considered PECL devices.)
ECL devices in the PECL mode, must have the
input/output DC specifications adjusted for proper
operation. ECL levels (DC) are referenced from the VCC
level. To calculate the PECL DC specifications, ECL levels
are added to the new VCC.
Example:
PECL VOH = New VCC + ECL VOH, 5.0 V +
(–0.81 V) = 4.190 V and is the max VOH level at 25°C
for a PECL device. Follow the same procedure to
calculate all input/output DC specifications for a
device used in a PECL mode. The VTT supply used to
sink the parallel termination currents is also
referenced from the VCC supply and is VCC – 2.0 V.
The PECL VTT supply = +5.0 V – 2.0 V = +3.0 V and
should track the VCC supply one–to–one for specified
operation.
Since ECL is referenced from the VCC rail, any noise on the
VCC supply will be reflected on the output waveshape at a
one–to–one ratio. Therefore, noise should be kept as low as
possible for best operation. Devices in a PECL system
cannot have VCC vary more than 5% to assure proper AC
operation. See ON Semiconductor Application Note
AN1406/D “Designing With PECL (ECL at +5.0 V)” for
more details.
AC performance in the PECL mode is equal to the AC
performance in the ECL mode, if the pitfalls set forth in
Application Note (AN1406/D) are avoided.
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TND309
MECL FAMILY COMPARISONS
Table 1. General Characteristics
MECL 10K
Feature
1. Gate Propagation Delay
2. Output Edge Speed*
3. Flip–Flop Toggle Speed
4. Gate Power
5. Speed Power Product
MECL 10H
10,100 Series
10,200 Series
1.0 ns
1.0 ns
250 MHz min
25 mW
25 pJ
2.0 ns
3.5 ns
125 MHz min
25 mW
50 pJ
1.5 ns
2.5 ns
200 MHz min
25 mW
37 pJ
*Output edge speed: MECL 10K/10H measured 20% to 80%.
Table 2. Operating Temperature Range
Ambient
Temperature Range
MECL 10H
0° to 75°C
MC10H100 Series
–30°C to +85°C
MECL 10K
MC10100 Series
MC10200 Series
MECL IN PERSPECTIVE
In evaluating any logic line, speed and power
requirements are the obvious primary considerations.
Table 1 and Table 2 provide the basic parameters of the
MECL 10H, MECL 10K, and MECL III families. But these
provide only the start of any comparative analysis, as there
are a number of other important features that make MECL
highly desirable for system implementation. Among these:
Complementary Outputs cause a function and its
complement to appear simultaneously at the device outputs,
without the use of external inverters. It reduces package
count by eliminating the need for associated invert functions
and, at the same time, cuts system power requirements and
reduces timing differential problems arising from the time
delays introduced by inverters.
High Input Impedance and Low Output Impedance
permit large fan out and versatile drive characteristics.
Insignificant Power Supply Noise Generation, due to
differential amplifier design which eliminates current spikes
even during signal transition period.
Nearly Constant Power Supply Current Drain
simplifies power–supply design and reduces costs.
Low Cross–Talk due to low–current switching in signal
path and small (typically 850 mV) voltage swing, and to
relatively long rise and fall times.
Wide Variety of Functions, including complex functions
facilitated by low power dissipation (particularly in
MECL 10H and MECL 10K series). A basic MECL 10K
gate consumes less than 8.0 mW in on–chip power in some
complex functions.
Wide Performance Flexibility due to differential
amplifier design which permits MECL circuits to be used as
linear as well as digital circuits.
Transmission Line Drive Capability is afforded by the
open emitter outputs of MECL devices. No “Line Drivers”
are listed in MECL families, because every device is a line
driver.
Wire–ORing reduces the number of logic devices
required in a design by producing additional OR gate
functions with only an interconnection.
Twisted Pair Drive Capability permits MECL circuits to
drive twisted–pair transmission lines as long as 1000 feet.
Wire–Wrap Capability is possible with the MECL 10K
family because of the slow rise and fall time characteristic
of the circuits.
Open Emitter–Follower Outputs are used for MECL
outputs to simplify signal line drive. The outputs match any
line impedance and the absence of internal pulldown
resistors saves power.
Input Pulldown Resistors of approximately 50 k
permit unused inputs to remain unconnected for easier
circuit board layout.
MECL APPLICATIONS
ON Semiconductor’s MECL product lines are designed
for a wide range of systems needs. Within the computer
market, MECL 10K is used in systems ranging from special
purpose peripheral controllers to large mainframe
computers. Big growth areas in this market include disk and
communication channel controllers for larger systems and
high performance minicomputers.
The industrial market primarily uses MECL for high
performance test systems such as IC or PC board testers.
However, the high bandwidths of MECL 10H and
MECL 10K are required for many frequency synthesizer
systems using high speed phase lock loop networks. MECL
has continued to grow in the industrial market through
complex medical electronic products and high performance
process control systems.
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TND309
BASIC CONSIDERATIONS FOR HIGH–SPEED
LOGIC DESIGN
High–speed operation involves only four considerations
that differ significantly from operation at low and medium
speeds:
1. Time delays through interconnect wiring, which
may have been ignored in medium–speed systems,
become highly important at state–of–the–art speeds.
2. The possibility of distorted waveforms due to
reflections on signal lines increases with edge speed.
3. The possibility of “crosstalk” between adjacent
signal leads is proportionately increased in
high–speed systems.
4. Electrical noise generation and pick–up are more
detrimental at higher speeds.
In general, these four characteristics are speed– and
frequency–dependent, and are virtually independent of the
type of logic employed. The merit of a particular logic
family is measured by how well it compensates for these
deleterious effects in system applications.
The interconnect–wiring time delays can be reduced only
by reducing the length of the interconnecting lines. At logic
speeds of two nanoseconds, an equivalent “gate delay” is
introduced by every foot of interconnecting wiring.
Obviously, for functions interconnected within a single
monolithic chip, the time delays of signals travelling from
one function to another are insignificant. But for a great
many externally interconnected parts, this can soon add up
to an appreciable delay time. Hence, the greater the number
of functions per chip, the higher the system speed. MECL
circuits, particularly those of the MECL 10K and
MECL 10H Series are designed with a propensity toward
complex functions to enhance overall system speed.
Waveform distortion due to line reflections also becomes
troublesome principally at state–of–the–art speeds. At slow
and medium speeds, reflections on interconnecting lines are
not usually a serious problem. At higher speeds, however,
line lengths can approach the wavelength of the signal and
improperly terminated lines can result in reflections that will
cause false triggering (see Figures 1 and 2). The solution, as
in RF technology, is to employ “transmission–line”
practices and properly terminate each signal line with its
characteristic impedance at the end of its run. The
low–impedance, emitter–follower outputs of MECL circuits
facilitate transmission–line practices without upsetting the
voltage levels of the system.
The increased affinity for crosstalk in high–speed circuits
is the result of very steep leading and trailing edges (fast rise
and fall times) of the high–speed signal. These steep
wavefronts are rich in harmonics that couple readily to
adjacent circuits. In the design of MECL 10K and
MECL 10H, the rise and fall times have been deliberately
slowed. This reduces the affinity for crosstalk without
compromising other important performance parameters.
From the above, it is evident that the MECL logic line is
not simply capable of operating at high speed, but has been
specifically designed to reduce the problems that are
normally associated with high–speed operation.
= 8″
= 8″
A
A
ZO = 50 RE
RL = Zo
VEE
VTT = - 2 VDC
HIGH
HIGH
RECEIVING GATE
INPUT A
RECEIVING GATE
INPUT A
LOW
LOW
Figure 1. Unterminated Transmission Line
(No Ground Plane Used)
Figure 2. Properly Terminated Transmission Line
(Ground Plane Added)
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TND309
GATE CIRCUIT
DIFFERENTIAL
AMPLIFIER
BIAS
NETWORK
GATE TRANSFER CURVES
COMPLEMENTARY
OUTPUTS
VCC2 (GND)
-0.800
Output Voltage (Volts)
MULTIPLE
INPUTS
VCC1 (GND)
OR
NOR
Q1
Q2
Q3
Q4
Q5
B
C
D
-1.200
VBB -1.29 V
-1.600
LOW
(-1.75 V TYP.)
-1.800
-1.400 -1.200
INPUT VOLTAGE
(VOLTS)
VBB ≅
-1.29 V
A
HIGH
(-0.90 V TYP.)
A
B
C
D
VEE ( -5.2 V)
INPUTS
A+B+C+D
A+B+C+D
GATE SYMBOL
Figure 3. MECL 10K Gate Structure and Switching Behavior
CIRCUIT DESCRIPTION
The typical MECL 10K circuit, Figure 3, consists of a
differential–amplifier input circuit, a temperature and
voltage compensated bias network, and emitter–follower
outputs to restore dc levels and provide buffering for
transmission line driving. High fan–out operation is possible
because of the high input impedance of the differential
amplifier input and the low output impedance of the emitter
follower outputs. Power–supply noise is virtually
eliminated by the nearly constant current drain of the
differential amplifier, even during the transition period.
Basic gate design provides for simultaneous output of both
the OR function and its complement, the NOR function. The
design of the MECL 10H gate is unchanged, with two
exceptions. The bias network has been replaced with a
voltage regulator, and the differential amplifier source
resistor has been replaced with a constant current source.
(See Technical Data section on page 12 for additional
MECL 10H information.)
Power–Supply Connections – Any of the power supply
levels, VTT, VCC, or VEE may be used as ground; however,
the use of the VCC node as ground results in best noise
immunity. In such a case: VCC = 0, VTT = –2.0 V,
VEE = –5.2 V.
System Logic Specifications – The output logic swing of
0.85 V, as shown by the typical transfer characteristics
curve, varies from a LOW state of VOL = –1.75 V to a HIGH
state of VOH = –0.9 V with respect to ground.
Positive logic is used when reference is made to logical
“0’s” or “1’s.” Then
“0” = –1.75 V = LOW
typical
“1” = –0.9 V = HIGH
Circuit Operation – Beginning with all logic inputs
LOW (nominal –1.75 V), assume that Q1 through Q4 are cut
off because their P–N base–emitter junctions are not
conducting, and the forward–biased Q5 is conducting.
Under these conditions, with the base of Q5 held at –1.29 V
by the VBB network, its emitter will be one diode drop
(0.8 V) more negative than its base, or –2.09 V. (The 0.8 V
differential is a characteristic of this P–N junction.) The
base–to–emitter differential across Q1 – Q4 is then the
difference between the common emitter voltage (–2.09 V)
and the LOW logic level (–1.75 V) or 0.34 V. This is less than
the threshold voltage of Q1 through Q4 so that these
transistors will remain cut off.
When any one (or all) of the logic inputs are shifted
upward from the –1.75 V LOW state to the –0.9 V HIGH
state, the base voltage of that transistor increases beyond the
threshold point and the transistor turns on. When this
happens, the voltage at the common–emitter point rises from
–2.09 V to –1.7 (one diode drop below the –0.9 V base
voltage of the input transistor), and since the base voltage of
the fixed–bias transistor (Q5) is held at –1.29 V, the
base–emitter voltage Q5 cannot sustain conduction. Hence,
this transistor is cut off.
This action is reversible, so that when the input signal(s)
return to the LOW state, Q1 – Q4 are again turned off and
Q5 again becomes forward biased. The collector voltages
resulting from the switching action of Q1 – Q4 and Q5 are
transferred through the output emitter–follower to the
output terminal. Note that the differential action of the
switching transistors (one section being off when the other
is on) furnishes simultaneous complementary signals at the
output. This action also maintains constant power supply
current drain.
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TND309
DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS
Current:
ICC
ICBO
ICCH
ICCL
IE
IF
Iin
IINH
IINL
IL
IOH
IOL
IOS
Iout
IOZL
IOZH
IR
IR′
ISC
Voltage:
Total power supply current drawn from the
positive supply by a MECL unit under test.
Leakage current from input transistor on MECL
devices without pulldown resistors when test
voltage is applied.
Current drain from VCC power supply with all
inputs at logic HIGH level.
Current drain from VCC power supply with all
inputs at logic LOW level.
Total power supply current drawn from a MECL
test unit by the negative power supply.
Forward diode current drawn from an input of a
saturated logic–to–MECL translator when that
input is at 0.4 V.
Current into the input of the test unit when a
maximum logic HIGH (VIH max) is applied at that
input.
HIGH level input current into a node with a
specified HIGH level (VIH max) logic voltage
applied to that node. (Same as Iin for positive
logic.)
LOW level input current, into a node with a
specified LOW level (VIL min) logic voltage
applied to that node.
Load current that is drawn from a MECL circuit
output when measuring the output HIGH level
voltage.
HIGH level output current: the current flowing
into the output, at a specified HIGH level output
voltage.
LOW level output current: the current flowing
into the output, at a specified LOW level output
voltage.
Output short circuit current.
Output current (from a device or circuit, under
such conditions mentioned in context).
Output off current LOW – The current flowing out
of a disabled 3–state output with a specified
LOW output voltage applied.
Output off current HIGH – The current flowing
into a disabled 3–state output with a specified
HIGH output.
Reverse current drawn from a transistor input of
a test unit when VEE is applied to that input.
Reverse current leakage into an input of a
saturated logic MECL/PECL translator when
that input is at VCC.
Short–circuit current drawn from a translator
saturating output when that output is at ground
potential.
VBB
VBE
VCB
VCC
VCC1
VCC2
VCMR
VEE
VF
VIH
VIH max
VIHA
VIHA min
VIH min
VIL
VIL max
VILA
VILA max
VIL min
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Reference bias supply voltage.
Base–to–emitter voltage drop of a transistor at
specified collector and base currents.
Collector–to–base voltage drop of a transistor at
specified collector and base currents.
General term for the most positive power supply
voltage to a MECL device (usually ground,
except for translator and interface circuits).
Most positive power supply voltage (output
devices). (Usually ground for MECL devices.)
Most positive power supply voltage (current
switches and bias driver). (Usually ground for
MECL devices.)
The CMR range is referenced to the most
positive side of the differential input signal.
Normal operation is obtained if the HIGH level
falls within the specified range and the
peak-to-peak voltage lies between VPPmin and
1.0 V. The lower end of the CMR range varies
1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –5.2 V. Note for PECL
operation, the VCMR(min) will be fixed at 5.0 V –
|VCMR(min)|.
Most negative power supply voltage for a circuit
(usually –5.2 V for MECL devices).
Input voltage for measuring IF on TTL interface
circuits.
Input logic HIGH voltage level (nominal value).
Maximum HIGH level input voltage: The most
positive (least negative) value of high–level
input voltage, for which operation of the logic
element within specification limits is guaranteed.
Input logic HIGH threshold voltage level.
Minimum input logic HIGH level (threshold)
voltage for which performance is specified.
Minimum HIGH level input voltage: The least
positive (most negative) value of HIGH level
input voltage for which operation of the logic
element within specification limits is guaranteed.
Input logic LOW voltage level (nominal value).
Maximum LOW level input voltage: The most
positive (least negative) value of LOW level
input voltage for which operation of the logic
element within specification limits is guaranteed.
Input logic LOW threshold voltage level.
Maximum input logic LOW level (threshold)
voltage for which performance is specified.
Minimum LOW level input voltage: The least
positive (most negative) value of LOW level
input voltage for which operation of the logic
element within specification limits is guaranteed.
TND309
DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS (continued)
Voltage (continued):
Temperature:
tAA
Vin
Vmax
Tstg
VOH
VOHA
VOHA min
VOH max
VOH min
VOL
VOLA
VOLA max
VOL max
VOL min
VTT
Address Access Time
Input voltage (to a circuit or device).
Maximum (most positive) supply voltage,
permitted under a specified set of conditions.
Output logic HIGH voltage level: The voltage
level at an output terminal for a specified output
current, with the specified conditions applied to
establish a HIGH level at the output.
Output logic HIGH threshold voltage level.
Minimum output HIGH threshold voltage level
for which performance is specified.
Maximum output HIGH or high–level voltage for
given inputs.
Minimum output HIGH or high–level voltage for
given inputs.
Output logic LOW voltage level: The voltage
level at the output terminal for a specified output
current, with the specified conditions applied to
establish a LOW level at the output.
Output logic LOW threshold voltage level.
Maximum output LOW threshold voltage level
for which performance is specified.
Maximum output LOW level voltage for given
inputs.
Minimum output LOW level voltage for given
inputs.
Line load–resistor terminating voltage for
outputs from a MECL device.
TJ
TA
JA
JC
lfpm
CA
Miscellaneous:
eg
TPin
TPout
D.U.T.
Cin
Cout
Zout
PD
RL
RT
Rp
Time Parameters:
t+
t–
tr
tf
t+–
t–+
t pd
t x±y±
t x+
t x–
f Tog
f shift
Maximum temperature at which device may be
stored without damage or performance
degradation.
Junction (or die) temperature of an integrated
circuit device.
Ambient (environment) temperature existing in
the immediate vicinity of an integrated circuit
device package.
Thermal resistance of an IC package, junction to
ambient.
Thermal resistance of an IC package, junction to
case.
Linear feet per minute.
Thermal resistance of an IC package, case to
ambient.
Waveform rise time (LOW to HIGH), 10% to
90%, or 20% to 80%, as specified.
Waveform fall time (HIGH to LOW), 90% to 10%,
or 80% to 20%, as specified.
Same as t+.
Same as t–.
Propagation Delay, see Figure 9 on page 15.
Propagation Delay, see Figure 9 on page 15.
Propagation delay, input to output from the 50%
point of the input waveform at pin x (falling edge
noted by – or rising edge noted by +) to the 50%
point of the output waveform at pin y (falling edge
noted by – or rising edge noted by +). (Cf
Figure 9 on page 15.)
Output waveform rise time as measured from
10% to 90% or 20% to 80% points on waveform
(whichever is specified) at pin x with input
conditions as specified.
Output waveform fall time as measured from
90% to 10% or 80% to 20% points on waveform
(whichever is specified) at pin x, with input
conditions as specified.
Toggle frequency of a flip–flop or counter device.
Shift rate for a shift register.
P.U.T.
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Signal generator inputs to a test circuit.
Test point at input of unit under test.
Test point at output of unit under test.
Device under test.
Input capacitance.
Output capacitance.
Output impedance.
The total DC power applied to a device, not
including any power delivered from the device to
a load.
Load Resistance.
Terminating (load) resistor.
An input pull–down resistor (i.e., connected to
the most negative voltage).
Pin under test.
TND309
MECL LOGIC SURFACE MOUNT
TAPE AND REEL
ON Semiconductor has now added the convenience of
Tape and Reel packaging for our growing family of standard
Integrated Circuit products. The packaging fully conforms
to the latest EIA RS-481A specification. The antistatic
embossed tape provides a secure cavity sealed with a
peel-back cover tape.
WHY SURFACE MOUNT?
Surface Mount Technology is now being utilized to offer
answers to many problems that have been created in the use
of insertion technology.
Limitations have been reached with insertion packages
and PC board technology. Surface Mount Technology offers
the opportunity to continue to advance the State-of-the-Art
designs that cannot be accomplished with Insertion
Technology.
Surface Mount Packages allow more optimum device
performance with the smaller Surface Mount configuration.
Internal lead lengths, parasitic capacitance and inductance
that placed limitations on chip performance have been
reduced.
The lower profile of Surface Mount Packages allows more
boards to be utilized in a given amount of space. They are
stacked closer together and utilize less total volume than
insertion populated PC boards.
Printed circuit costs are lowered with the reduction of the
number of board layers required. The elimination or
reduction of the number of plated through holes in the board,
contribute significantly to lower PC board prices.
Surface Mount assembly does not require the preparation
of components that are common on insertion technology
lines. Surface Mount components are sent directly to the
assembly line, eliminating an intermediate step.
Automatic placement equipment is available that can
place Surface Mount components at the rate of a few
thousand per hour to hundreds of thousands of components
per hour.
Surface Mount Technology is cost effective, allowing the
manufacturer the opportunity to produce smaller units and
offer increased functions with the same size product.
GENERAL INFORMATION
• Reel Size
13 inch (330 mm) Suffix: R2
• Tape Width
16 mm
• Units/Reel
1000
MECHANICAL POLARIZATION
TYPICAL
PIN 1
VIEW
FROM
TAPE
SIDE
LINEAR DIRECTION
OF TRAVEL
ORDERING INFORMATION
• Minimum Lot Size/Device Type = 3000 Pieces.
• No Partial Reel Counts Available.
• To order devices which are to be delivered in Tape and
Reel, add the appropriate suffix to the device number
being ordered.
Example:
MECL AVAILABILITY IN SURFACE MOUNT
ON Semiconductor is now offering MECL 10K and
MECL 10H in the PLCC (Plastic Leaded Chip Carrier)
packages.
MECL in PLCC may be ordered in conventional plastic
rails or on Tape and Reel. Refer to the Tape and Reel section
for ordering details.
ORDERING CODE
SHIPMENT METHOD
MC10101FN
MC10101FNR2
MC10H101FN
MC10H101FNR2
MC12015D
MC12015DR2
Rails
13 inch Tape and Reel
Rails
13 inch Tape and Reel
Rails
13 inch Tape and Reel
DUAL-IN-LINE PACKAGE TO
PLCC PIN CONVERSION DATA
The following tables give the equivalent I/O pinouts of
Dual-In-Line (DIL) packages and Plastic Leaded Chip
Carrier (PLCC) packages.
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PIN CONVERSION TABLES
8–Pin DIL to 20–Pin PLCC
8 PIN DIL
1
2
3
4
5
6
7
8
20 PIN PLCC
2
5
7
10
12
15
17
20
14–Pin DIL to 20–Pin PLCC
14 PIN DIL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20 PIN PLCC
2
3
4
6
8
9
10
12
13
14
16
18
19
20
16–Pin DIL to 20–Pin PLCC
16 PIN DIL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20 PIN PLCC
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
20–Pin DIL to 20–Pin PLCC
20 PIN DIL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
20 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24–Pin DIL to 28–Pin PLCC
24 PIN DIL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28 PIN PLCC
2
3
4
5
6
7
9
10
11
12
13
14
16
17
18
19
20
21
23
24
25
26
27
28
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MECL POSITIVE AND NEGATIVE LOGIC
INTRODUCTION
The increasing popularity and use of emitter coupled logic
has created a dilemma for some logic designers. Saturated
logic families such as TTL have traditionally been designed
with the NAND function as the basic logic function,
however, the basic ECL logic function is the NOR function
(positive logic). Therefore, the designer may either design
ECL systems with positive logic using the NOR, or design
with negative logic using the NAND. Which is the more
convenient? On the one hand the designer is familiar with
positive logic levels and definitions, and on the other hand,
he is familiar with implementing systems using NAND
functions. Perhaps a presentation of the basic definitions and
characteristics of positive and negative logic will clarify the
situation and eliminate misunderstanding.
VCC = gnd
C
A
VBB = -1.29 volts
B
VEE = -5.2 volts
Table 3.
INPUTS
A
B
LO LO
LO HI
HI LO
HI
HI
Table 4.
NEGATIVE LOGIC
INPUTS
A
B
1
1
1
0
0
1
0
0
A
B
OUTPUT
C
HI
LO
LO
LO
HI = -0.9 volts
LO = -1.7 volts
OUTPUT
C
0
1
1
1
Table 5.
POSITIVE LOGIC
INPUTS
A
B
0
0
0
1
1
0
1
1
C=AB
OUTPUT
C
1
0
0
0
C=A+B
A
C
B
C
Figure 4. Basic MECL Gate Circuit and Logic Function
in Positive and Negative Nomenclature
Circuit diagrams external to ON Semiconductor products are included as a means of illustrating typical semiconductor applications;
consequently, complete information sufficient for construction purposes is not necessarily given. The information in this Technical Note
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of
ON Semiconductor or others.
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C = A • B; that is, the circuit performs the NAND function.
Table 5 translates the equivalent positive logic function into
C = A + B, the NOR function.
Similar comparisons could be made for other positive
logic functions. As an example, the positive OR function
translates to the negative AND function. Table 6 shows a
comparison of several common logic functions.
Any function available in a logic family may be expressed
in terms of positive or negative logic, bearing in mind
the definition of logic levels. The choice of logic definition,
as previously stated, is dependent on the designer.
ON Semiconductor provides both positive and negative
logic symbols on data sheets for the popular MECL 10,000
logic series.
LOGIC EQUIVALENCIES
Binary logic must have two states to represent the binary
1 and 0. With ECL the typical states are a high level of –0.9
volts and a low level of –1.7 volts. Two choices are possible
then to represent the binary 1 and 0. Positive logic defines
the 1 or “true” state as the most positive voltage level,
whereas negative logic defines the most negative voltage
level as the 1 or “true” state. Because of the difference in
definition of states, the basic ECL gate is a NOR function in
positive logic and is a NAND function in negative logic.
Figure 4 more clearly shows the above comparison of
functions. Table 3 lists the output voltage level as a function
of input voltage levels of the MECL gate circuit shown.
Table 4 translates the voltage levels into the appropriate
negative logic levels which show the function to be
Table 6. Comparative Positive and Negative Logic Functions
POSITIVE LOGIC
INPUTS
A
B
AND
OR
NAND
NOR
EXOR
EXNOR
LO
LO
HI
HI
LO
HI
LO
HI
LO
LO
LO
HI
LO
HI
HI
HI
HI
HI
HI
LO
HI
LO
LO
LO
LO
HI
HI
LO
HI
LO
LO
HI
A
B
OR
AND
NOR
NAND
EXNOR
EXOR
INPUTS
NEGATIVE LOGIC
REFERENCE
Y. Chu, Digital Computer Design Fundamentals
New York, McGraw–Hill, 1962.
SUMMARY
Conversion from one logic form to another or the use of
a particular logic form need not be a complicated process. If
the designer uses the logic form with which he is familiar
and bears in mind the previously mentioned definition of
levels, problems arising from definition of logic functions
should be minimized.
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TECHNICAL DATA
GENERAL CHARACTERISTICS AND
SPECIFICATIONS
In subsequent sections of this document, the important
MECL parameters are identified and characterized, and
complete data provided for each of the functions. To make
this data as useful as possible, and to avoid a great deal of
repetition, the data that is common to all functional blocks
in a line is not repeated on each individual sheet. Rather,
these common characteristics, as well as the application
information that applies to each family, are discussed.
In general, the common characteristics of major
importance are:
Maximum Ratings, including both DC and AC
characteristics and temperature limits;
Transfer Characteristics, which define logic levels and
switching thresholds;
DC Parameters, such as output levels, threshold levels,
and forcing functions.
AC Parameters, such as propagation delays, rise and fall
times and other time dependent characteristics.
In addition, this document will discuss general layout and
design guides that will help the designer in building and
testing systems with MECL circuits.
MAXIMUM RATINGS
The limit parameters beyond which the life of the devices
may be impaired are given in Table 7. In addition, Table 8
provides certain limits which, if exceeded, will not damage
the devices, but could degrade the performance below that
of the guaranteed specifications.
Table 7. Limits Beyond which Device Life may be Impaired
Characteristic
Symbol
Unit
MECL 10H
MECL 10K
Power Supply
VEE
Vdc
–8.0 to 0
–8.0 to 0
Input Voltage (VCC = 0)
Vin
Vdc
0 to VEE
0 to VEE
Output Source Current Continuous
Iout
mAdc
50
50
Output Source Current Surge
Iout
mAdc
100
100
Storage Temperature
Tstg
°C
–65 to +150
–65 to +150
Junction Temperature Ceramic Package (Note 1)
TJ
°C
165
165
Junction Temperature Plastic Package (Note 2)
TJ
°C
140
140
1. Maximum TJ may be exceeded ( 250°C) for short periods of time ( 240 hours) without significant reduction in device life.
2. For long term ( 10 yrs.) max TJ of 110°C required. Max TJ may be exceeded ( 175°C) for short periods of time ( 240 hours) without
significant reduction in device life.
Table 8. Limits Beyond which Performance may be Degraded
Characteristic
Symbol
Unit
MECL 10H
MECL 10K
TA
°C
0 to +75
–30 to +85
VEE
Vdc
–4.94 to –5.46
–4.68 to –5.72
(Note 4)
50 to –2.0 Vdc
50 to –2.0 Vdc
Operating Temperature Range Commercial (Note 3)
Supply Voltage (VCC = 0)
Output Drive Commercial
–
3. With airflow 500 lfpm.
4. Functionality only. Data sheet limits are specified for –5.2 V ± 0.010 V.
5. Except MC1648 which has an internal output pulldown resistor.
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MECL TRANSFER CURVES and SPECIFICATION TEST POINTS
Gate Output
(measured test limits)
VOHA min
VOH max
-1.850
-1.475
-0.810
-0.810
-1.105
VOH min
OR
NOR
VOLA max
VOL max
VOL min
Test Conditions: 25C
VEE = -5.2 V
50 matched
inputs and outputs
-0.960
-0.980
-1.630
-1.650
-1.850
VIL min
Gate Input
(Applied test voltage)
VILA max
VIHA min
-1.95
VOH max
High
State
-1.48
-0.810
-0.810
-1.13
VOH min
-0.980
OR
NOR
VOL max
Low
State
VOL min
VIH max
-1.950
VIL min
Figure 5. MECL 10K
Low
State
VIH max
VIL max
Gate Input
(Applied test voltage)
VBB ≈ - 1.29V
(Switching Threshold)
-1.630
High
State
VIH min
VBB ≈ -1.29 V
(Switching Threshold)
Figure 6. MECL 10H
MECL TRANSFER CURVES
For MECL logic gates, the dual (complementary) outputs
must be represented by two transfer curves: one to describe
the OR switching action and one to describe the NOR
switching action. Typical transfer curves and associated data
for the MECL 10K/10H family are shown in Figure 5 and
Figure 6, respectively.
It is not necessary to measure transfer curves at all points
of the curves. To guarantee correct operation it is sufficient
merely to measure two sets of min/max logic level
parameters.
The first set is obtained for 10K by applying test voltages,
VIL min and VIH max (sequentially) to the gate inputs, and
measuring the OR and NOR output levels to make sure they
are between VOL max and VOL min, and VOH max and VOH min
specifications.
The second set of logic level parameters relates to the
switching thresholds. This set of data is distinguished by an
“A” in symbol subscripts. A test voltage, VILA max, is
applied to the gate and the NOR and OR outputs are
measured to see that they are above the VOHA min and below
the VOLA max levels, respectively. Similar checks are made
using the test input voltage VIHA min.
The result of these specifications insures that:
a . The switching threshold (≈ VBB) falls within the
darkest rectangle; i.e. switching does not begin
outside this rectangle;
b . Quiescent logic levels fall in the lightest shaded
ranges;
c . Guaranteed noise immunity is met.
As shown in Figure 7, MECL 10K outputs rise with
increasing ambient temperature. All circuits in each family
have the same worst–case output level specifications
regardless of power dissipation or junction temperature
differences to reduce loss of noise margin due to thermal
differences.
85°C
OUTPUT VOLTAGE
(VOLTS)
-0.950
85°C
25°C
-30°C
25°C
OR OUTPUT
-30°C
-1.350
85°C
85°C
25°C
-1.750
NOR OUTPUT
25°C
-30°C
-1.6
-30°C
-1.4
-1.2
-1.0
INPUT VOLTAGE (VOLTS)
Figure 7. Typical Transfer Characteristics as a
Function of Temperature (MECL 10K)
All of these specifications assume –5.2 V power supply
operation. Operation at other power–supply voltages is
possible, but will result in further transfer curve changes.
Table 9 gives rate of change of output voltages as a function
of power supply.
Table 9. Typical Level Change Rates/1.0 V
Voltage
MECL 10H
MECL 10K
VOH/VEE
0.008
0.016
VOL/VEE
0.020
0.250
VBB/VEE
0.010
0.148
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NOISE MARGIN
“Noise margin” is a measure of logic circuit’s resistance
to undesired switching. MECL noise margin is defined in
terms of the specification points surrounding the switching
threshold. The critical parameters of interest here are those
designated with the “A” subscript (VOHA min, VOLA max,
VIHA min, VILA max) in the transfer characteristic curves.
MECL 10H is specified and tested with:
VOHA min = VOH min
VOLA max = VOL max
VIHA min = VIH min
and
VILA max = VIL max
Guaranteed noise margin (NM) is defined as follows:
NMHIGH LEVEL = VOHA min – VIHA min
NMLOW LEVEL = VILA max – VOLA max
To see how noise margin is computed, assume a MECL
gate drives a similar MECL gate, Figure 8.
At a gate input (point B) equal to VILA max, MECL gate
#2 can begin to enter the shaded transition region.
This is a “worst case” condition, since the VOLA max
specification point guarantees that no device can enter the
transition region before an input equal to VILA max is reached.
Clearly then, VILA max is one critical point for noise margin
computation, since it is the edge of the transition region.
To find the other critical voltage, consider the output from
MECL gate #1 (point A). What is the most positive value
possible for this voltage (considering worst case
specifications)? From Figure 8 it can be observed that the
VOLA max specification insures that the LOW state OR
output from gate #1 can be no greater than VOLA max.
Note that VOLA max is more negative than VILA max. Thus,
with VOLA max at the input to gate #2, the transition region
is not yet reached. (The input voltage to gate #2 is still to the
left of VILA max on the transfer curve.)
In order to ever run the chance of switching gate #2, we
would need an additional voltage, to move the input from
VOLA max to VILA max. This constitutes the “safety factor”
known as noise margin. It can be calculated as the magnitude
of the difference between the two specification voltages, or
for the MECL 10K levels shown:
NMLOW
– VILA max – VOLA max
– –1.475 V – (–1.630 V)
– 155 mV.
Similarly, for the HIGH state:
NMHIGH
– VOHA min – VIHA min
– –0.980 V – (–1.105 V)
– 125 mV
Analogous results are obtained when considering the
“NOR” transfer data.
Note that these noise margins are absolute worst case
conditions. The lessor of the two noise margins is that for the
HIGH state, 125 mV. This then, constitutes the guaranteed
margin against signal undershoot, and power or thermal
disturbances.
As shown in the table, typical noise margins are usually
better than guaranteed – by about 75 mV. For MECL 10H the
“noise margin” is 150 mV for NM low and NM high.
Noise margin is a dc specification that can be calculated,
since it is defined by specification points tabulated on
MECL data sheets. However, by itself, this specification
does not give a complete picture regarding the noise
immunity of a system built with a particular set of circuits.
Overall system noise immunity involves not only
noise–margin specifications, but also other circuit–related
factors that determine how difficult it is to apply a noise
signal of sufficient magnitude and duration to cause the
circuit to propagate a false logic state. In general, then, noise
immunity involves line impedances, circuit output
impedances, and propagation delay in addition to
noise–margin specifications. This subject to discussed in
greater detail in the MECL System Design Handbook,
HB205/D.
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-1.475
GATE
OUTPUT
-0.980
VOLA MAX
VILA MAX
VIHA MIN
A
Table 10. Noise Margin Computations
Guaranteed
Worst–Case DC
Noise Margin
(V)
Typical DC
Noise Margin
(V)
MECL 10H
0.150
0.270
MECL 10K
0.125
0.210
C
B
VOLA MAX *
* VOHA min = VOH min, VOLA max = VOL max,
VIHA min = VIH min and
VILA max = VIL max for MECL 10H.
LOW
STATE
VBB (SWITCHING THRESHOLD)
#1
VILA MAX *
V LowNoise
Margin
-1.630
GATE
INPUT
VIHA MIN *
HIGH
STATE
OR
VOHA MIN
VOHA MIN *
V HighNoise
Margin
-1.105
Family
#2
Specification Points for Determining Noise Margin
Figure 8. MECL Noise Margin Data
AC OR SWITCHING PARAMETERS
Time–dependent specifications are those that define the
effects of the circuit on a specified input signal, as it travels
through the circuit. They include the time delay involved in
changing the output level from one logic state to another. In
addition, they include the time required for the output of a
circuit to respond to the input signal, designated as
OVERSHOOT
UNDERSHOOT
propagation delay, MECL waveform and propagation delay
terminologies are depicted in Figure 9. Specific rise, fall,
and propagation delay times are given on the data sheet for
each specific functional block, but like the transfer
characteristics, ac parameters are temperature and voltage
dependent. Typical variations for MECL 10K are given in
the curves of Figures 10 through 13.
HIGH LEVEL
VIHA
50%
VILA
UNDERSHOOT
50%
VIN
VBB
LOW LEVEL
T- -*
VOUT OR
MECL WAVEFORM TERMINOLOGY
T- +*
80%
20%
VOUT
T-
VOUT NOR
T+
T- = TF
T++ *
50%
T+ -*
50%
*TPD = T - + T + +
T+ = TR
MECL Propagation Delay
MECL 10K and MECL 10H Rise and Fall Times
Figure 9. Typical Logic Waveforms
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2.5
2.5
50 LOAD TO -2.0 V
2.4
OR
2.3
+85°C
25°C
-30°C
t++ PROPAGATION DELAY (ns)
t- - PROPAGATION DELAY (ns)
2.6
2.2
2.1
2.0
NOR
1.9
85°C
25°C
-30°C
1.8
1.7
1.6
2.4
25°C
2.1
2.0
-30°C
85°C
25°C
-30°C
OR
1.9
1.8
1.7
1.6
-3.6
3.9
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
1.5
-6.8
3.5
85°C
4.8
25°C
-30°C
4.6
3.4
3.3
3.1
3.0
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
4.4
85°C
25°C
-30°C
NOR
4.2
4.0
3.8
OR
-3.6
-6.8
50 LOAD TO -2.0 V
5.0
t+, RISE TIME
3.6
3.2
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
5.2
NOR
3.7
-3.6
Figure 11. Typical Propagation Delay t++ vs.
VEE and Temperature (MECL 10K)
50 LOAD TO -2.0 V
3.8
t–, FALL TIME (ns)
85°C
NOR
2.2
Figure 10. Typical Propagation Delay t– – vs.
VEE and Temperature (MECL 10K)
2.9
50 LOAD TO -2.0 V
2.3
OR
85°C
25°C
-30°C
3.6
85°C
25°C
-30°C
-6.8
3.4
3.2
Figure 12. Typical Fall Time (90% to 10%) vs.
Temperature and Supply Voltage (MECL 10K)
-3.6
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
-6.8
Figure 13. Typical Fall Time (10% to 90%) vs.
Temperature and Supply Voltage (MECL 10K)
THOLD
SETUP AND HOLD TIMES
Setup and hold times are two AC parameters which can
easily be confused unless clearly defined. For MECL logic
devices, tsetup is the minimum time (50% – 50%) before the
positive transition of the clock pulse (C) that information
must be present at the Data input (D) to insure proper
operation of the device. The thold is defined similarly as the
minimum time after the positive transition of the clock pulse
(C) that the information must remain unchanged at the Data
input (D) to insure proper operation. Setup and hold
waveforms for logic devices are shown in Figure 14.
D
C
50%
50%
50%
TSETUP
Q
Q
Figure 14. Setup and Hold Waveforms for MECL
Logic Devices
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TESTING MECL 10H AND MECL 10K
MECL III. In addition, the generator voltage must have an
offset to give MECL signal swings of ≈ ±400 mV about a
threshold of ≈ +0.7 V when VCC = +2.0 and VEE = –3.2 V
for AC testing of logic devices.
The power supplies are shifted +2.0 V, so that the device
under test has only one resistor value to load into the
precision 50 ohm input impedance of the sampling
oscilloscope. Use of this technique yields a close correlation
between ON Semiconductor and customer testing. Unused
outputs are loaded with a 50 ohm resistor (100 ohm for
MC105XX devices) to ground. The positive supply (VCC)
should be decoupled from the test board by RF type 25 F
capacitors to ground. The VCC pins are bypassed to ground
with 0.1 F, as is the VEE pin.
Additional information on testing MECL 10K and
understanding data sheets is found in Application Note
AN701/D and the MECL System Design Handbook,
HB205/D.
To obtain results correlating with ON Semiconductor
circuit specifications certain test techniques must be used. A
schematic of a typical gate test circuit is shown in Figure 15.
This test circuit is the standard ac test configuration for most
MECL devices. (Exceptions are shown with device
specification.)
A solid ground plane is used in the test setup, and
capacitors bypass VCC1, VCC2, and VEE pins to ground. All
power leads and signal leads are kept as short as possible.
The sampling scope interface runs directly to the 50 ohm
inputs of Channel A and B via 50 ohm coaxial cable.
Equal–length coaxial cables must be used between the test
set and the A and B scope inputs. A 50 ohm coax cable such
as RG58/U or RG188A/U, is recommended.
Interconnect fittings should be 50 ohm GR, BNC,
Sealectro Conhex, or equivalent. Wire length should be
< 1/4 inch from TPin to input pin and TPout to output pin.
The pulse generator must be capable of 2.0 ns rise and fall
times for MECL 10K and 1.5 ns for MECL 10H and
SCOPE
CHANNEL A
SCOPE
CHANNEL B
OR
* Matched 50 ohm coax
** 0.1 F–decouples fixture
*** 25 F–dampens supply variations
*COAX
PULSE
GENERATOR
*COAX
NOR
*COAX
COAX
D.U.T.
1
16
8
**
**
††Pulse generator must be capable of rise
and fall times 2.0 ns for 10K and
1.0 ns for 10H.
***
NOTE: All power supply levels are
shown shifted 2 volts positive.
+2.0 V
VCC
-3.2 V
VEE
Figure 15. MECL Logic Switching Time Test Setup
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OPERATIONAL DATA
POWER SUPPLY CONSIDERATIONS
MECL circuits are characterized with the VCC point at
ground potential and the VEE point at –5.2 V. While this
MECL convention is not necessarily mandatory, it does
result in maximum noise immunity. This is so because any
noise induced on the VEE line is applied to the circuit as a
common–mode signal which is rejected by the differential
action of the MECL input circuit. Noise induced into the
VCC line is not cancelled out in this fashion. Hence, a good
system ground at the VCC bus is required for best noise
immunity. Also, MECL 10H circuits may be operated with
VEE at –4.5 V with a negligible loss of noise immunity.
Power supply regulation which will achieve 10%
regulation or better at the device level is recommended. The
–5.2 V power supply potential will result in best circuit
speed. Other values for VEE may be used. A more negative
voltage will increase noise margins at a cost of increased
power dissipation. A less negative voltage will have just the
opposite effect. (Noise margins and performance
specifications of MECL 10H are unaffected by variations in
VEE because of the internal voltage regulation.)
On logic cards, a ground plane or ground bus system
should be used. A bus system should be wide enough to
prevent significant voltage drops between supply and device
and to produce a low source inductance.
Although little power supply noise is generated by MECL
logic, power supply bypass capacitors are recommended to
handle switching currents caused by stray capacitance and
asymmetric circuit loading. A parallel combination of a
1.0 F and a 100 pF capacitor at the power entrance to the
board, and a 0.01 F low–inductance capacitor between
ground and the –5.2 V line every four to six packages, are
recommended.
Most MECL 10H, MECL 10K and MECL III circuits
have two VCC leads. VCC1 supplies current to the output
transistors and VCC2 is connected to the circuit logic
transistors. The separate VCC pins reduce cross–coupling
between individual circuits within a package when the
outputs are driving heavy loads. Circuits with large drive
capability, similar to the MC10110, have two VCC1 pins. All
VCC pins should be connected to the ground plane or ground
bus as close to the package as possible.
For further discussion of MECL power supply
considerations to be made in system designing, see MECL
System Design Handbook, HB205/D.
pulldown resistors permits the use of external terminations
designed to yield best system performance. To obtain total
operating power dissipation of a particular functional block
in a system, the dissipation of the output transistor, under
load, must be added to the circuit power dissipation.
Table 11 lists the power dissipation in the output transistors
plus that in the external terminating resistors, for the
more commonly used termination values and circuit
configurations. To obtain true package power dissipation, one
output–transistor power–dissipation value must be added to
the specified package power dissipation for each external
termination resistor used in conjunction with that package. To
obtain system power dissipation, the stated dissipation in the
external terminating resistors must be added as well. Unused
outputs draw no power and may be ignored.
Table 11. Average Power Dissipation in Output Circuit
with External Terminating Resistors
Output
Transistor
Power
Dissipation
(mW)
Terminating
Resistor
Power
Dissipation
(mW)
150 ohms to –2.0 Vdc
5.0
4.3
100 ohms to –2.0 Vdc
7.5
6.5
75 ohms to –2.0 Vdc
10
8.7
50 ohms to –2.0 Vdc
15
13
2.0 k ohms to VEE
2.5
7.7
1.0 k ohm to VEE
4.9
15.4
680 ohms to VEE
7.2
22.6
510 ohms to VEE
9.7
30.2
270 ohms to VEE
18.3
57.2
15
140
Terminating
Resistor Value
82 ohms to VCC and
130 ohms to VEE
LOADING CHARACTERISTICS
The differential input to MECL circuits offers several
advantages. Its common–mode–rejection feature offers
immunity against power–supply noise injection, and its
relatively high input impedance makes it possible for any
circuit to drive a relatively large number of inputs without
deterioration of the guaranteed noise margin. Hence, dc
fanout with MECL circuits does not normally present a
design problem.
Graphs showing typical output voltage levels as a function
of load current for MECL 10H, MECL 10K and MECL III
shown in Figure 16. These graphs can be used to determine
the actual output voltages for loads exceeding normal
operation.
POWER DISSIPATION
The power dissipation of MECL functional blocks is
specified on their respective data sheets. This specification
does not include power dissipated in the output devices due
to output termination. The omission of internal output
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TND309
VEE. As a result, unused inputs may be left unconnected (the
resistor provides a sink for ICBO leakage currents, and inputs
are held sufficiently negative that circuits will not trigger
due to noise coupled into such inputs). Input pulldown
resistor values are typically 50 k and are not to be used as
pulldown resistors for preceding open–emitter outputs.
Some MECL devices do not have input pulldowns.
Examples are the differential line receivers. If a single
differential receiver within a package is unused, one input of
that receiver must be tied to the VBB pin provided, and the
other input goes to VEE or is left open.
MECL circuits do not operate properly when inputs are
connected to VCC for a HIGH logic level. Proper design
practice is to set a HIGH level about –0.9 volts below VCC
with a resistor divider, a diode drop, or an unused gate
output.
While DC loading causes a change in output voltage
levels, thereby tending to affect noise margins, AC loading
increases the capacitances associated with the circuit and,
therefore, affects circuit speed, primarily rise and fall times.
MECL circuits typically have a 7.0 ohm output
impedance and a relatively unaffected by capacitive loading
on a positive–going output signal. However, the
negative–going edge is dependent on the output pulldown or
termination resistor. Loading close to a MECL output pin
will cause an additional propagation delay of 0.1 ns per
fanout load with a 50 ohm resistor to –2.0 Vdc or 270 ohms
to –5.2 Vdc. A 100 ohm resistor to –2.0 Vdc or 510 ohms to
–5.2 Vdc results in an additional 0.2 ns propagation delay
per fanout load.
Terminated transmission line signal interconnections are
used for best system performance. The propagation delay
and rise time of a driving gate are affected very little by
capacitance loading along a matched parallel–terminated
transmission line. However, the delay and characteristic
impedance of the transmission line itself are affected by the
distributed capacitance. Signal propagation down the line
will be increased by a factor, 1 CdCo . Here Co is the
normal intrinsic line capacitance, and Cd is the distributed
capacitance due to loading and stubs off the line.
Maximum allowable stub lengths for loading off of a
MECL 10K transmission line vary with the line impedance.
For example, with Zo = 50 ohms, maximum stub length
would be 4.5 inches (1.8 in. for MECL III). But when
Zo = 100 ohms, the maximum allowable stub length is
decreased to 2.8 inches (1.0 in. for MECL III).
The input loading capacitance of a MECL 10H and
MECL 10K gate is about 2.9 pF and 3.3 pF for MECL III.
To allow for the IC connector or solder connection and a
short stub length, 5.0 to 7.0 pF is commonly used in loading
calculations.
50
VBB
50 OHMS
I OUT (mA)
VIHA
VOH min
40
VILA
VOH
max
30
VOL
max
75 OHMS
VOL
min
20
100 OHMS
10
0
0
-0.5
-1.0
VOUT (VOLTS)
-1.5
-2.0
Figure 16. Output Voltage Levels vs. DC Loading
(Load Lines for Termination to –2.0 Vdc 25C)
50
VIHA
I OUT (mA)
40
UNUSED MECL INPUTS
The input impedance of a differential amplifier, as used in
the typical MECL input circuit, is very high when the
applied signal level is low. Under low–signal conditions,
therefore, any leakage to the input capacitance of the gate
could cause a gradual buildup of voltage on the input lead,
thereby adversely affecting the switching characteristics at
low repetition rates.
All single–ended input MECL logic circuits contain input
pulldown resistors between the input transistor bases and
VOL
max
VOH max
30
VOL
min
200 Ohms
270 Ohms
20
500 Ohms
10
0
VBB-VILA
VOH min
1 K Ohms
2 K Ohms
0
-0.5
-1.0
–1.5
-2.0
VOUT (VOLTS)
Figure 17. Output Voltage Levels vs. DC Loading
(Load Lines for Termination to VEE (–5.2 Vdc) 25C)
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SYSTEM DESIGN CONSIDERATIONS
THERMAL MANAGEMENT
Circuit performance and long–term circuit reliability are
affected by die temperature. Normally, both are improved by
keeping the IC junction temperatures low.
Electrical power dissipated in any integrated circuit is a
source of heat. This heat source increases the temperature of
the die relative to some reference point, normally the
ambient temperature of 25°C in still air. The temperature
increase, then, depends on the amount of power dissipated
in the circuit and on the net thermal resistance between the
heat source and the reference point.
The temperature at the junction is a function of the
packaging and mounting system’s ability to remove heat
generated in the circuit – from the junction region to the
ambient environment. The basic formula (a) for converting
power dissipation to estimated junction temperature is:
TJ = TA + PD(JC + CA)
(1)
or
TJ = TA + PD(JA)
(2)
PD = calculated maximum power dissipation
including effects of external loads
(see Power Dissipation section on page 18).
JC = average thermal resistance, junction to case
CA = average thermal resistance, case to ambient
JA = average thermal resistance, junction to
ambient
This ON Semiconductor recommended formula has
been approved by RADC and DESC for calculating a
“practical” maximum operating junction temperature for
MIL–M–38510 (JAN) MECL 10K devices.
Only two terms on the right side of equation (1) can be
varied by the user – the ambient temperature, and the device
case–to–ambient thermal resistance, CA. (To some extent
the device power dissipation can be also controlled, but
under recommended use the VEE supply and loading dictate
a fixed power dissipation.) Both system air flow and the
package mounting technique affect the CA thermal
resistance term. JC is essentially independent of air flow
and external mounting method, but is sensitive to package
material, die bonding method, and die area.
where
TJ = maximum junction temperature
TA = maximum ambient temperature
Table 12. Thermal Resistance Values for Standard MECL I/D Packages
Thermal Resistance in Still Air
Package Description
JA
(°C/Watt)
JC
(°C/Watt)
No.
Leads
Body
Style
Body
Material
Body
WxL
Die
Bond
Die Area
(Sq. Mils)
Flag Area
(Sq. Mils)
Avg.
Max.
Avg.
Max.
8
DIL
EPOXY
1/4″×3/8″
EPOXY
2496
8100
102
133
50
80
8
DIL
ALUMINA
1/4″×3/8″
SILVER/GLASS
2496
N/A
140
182
35
56
14
DIL
EPOXY
1/4″×3/4″
EPOXY
4096
6400
84
109
38
61
14
DIL
ALUMINA
1/4″×3/4″
SILVER/GLASS
4096
N/A
100
130
25
40
16
DIL
EPOXY
1/4″×3/4″
EPOXY
4096
12100
70
91
34
54
16
DIL
ALUMINA
1/4″×3/4″
SILVER/GLASS
4096
N/A
100
130
25
40
20
PLCC
EPOXY
0.35″×0.35″
EPOXY
4096
14,400
74
82
N/A
(Note 11)
N/A
(Note 11)
24
DIL (4)
EPOXY
1/2″×1–1/4″
EPOXY
8192
22500
67
87
31
50
24
DIL (5)
ALUMINA
1/2″×1–1/4″
SILVER/GLASS
8192
N/A
50
65
10
16
28
PLCC
EPOXY
0.45″×0.45″
EPOXY
7134
28,900
65
68
N/A
(Note 11)
N/A
(Note 11)
6. All plastic packages use copper lead frames – ceramic packages use alloy 42 frames.
7. Body style DIL is “Dual–In–Line.”
8. Standard Mounting Methods:
a. Dual–In–Line In Socket or P/C board with no contact between bottom of package and socket or P/C board.
b. PLCC packages solder attached to traces on 2.24″ × 2.24″ × 0.062″ FR4 type glass epoxy board with 1 oz./S.F. copper (solder coated)
mounted to tester with 3 leads of 24 gauge copper wire.
9. Case Outline 649.
10. Case Outline 623.
T TA
11. JC JA C
PD
TC = Case Temperature (determined by thermocouple).
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As an example of the use of the information above, the
maximum junction temperature for a 16 lead ceramic
dual–in–line packaged MECL 10K quad OR/NOR gate
(MC10101L) loaded with four 50 ohm loads can be
calculated. Maximum total power dissipation (including 4
output loads) for this quad gate is 195 mW. Assume for this
thermal study that air flow is 500 linear feet per minute.
From Figure 21, JA is 50°C/W. With TA (air flow
temperature at the device) equal to 25°C, the following
maximum junction temperature results:
TJ = PD (JA) + TA
TJ = (0.195 W) (50°C/W) + 25°C = 34.8°C
For applications where the case is held at essentially
a fixed temperature by mounting on a large or
temperature–controlled heatsink, the estimated junction
temperature is calculated by:
TJ = TC + PD (JC)
(3)
where TC = maximum case temperature and the other
parameters are as previously defined.
The maximum and average thermal resistance values
for standard MECL IC packages are given in Table 12. In ,
this basic data is converted into graphs showing the
maximum power dissipation allowable at various ambient
temperatures (still air) for circuits mounted in the different
packages, taking into account the maximum permissible
operating junction temperature for long term life
( 100,000 hours for ceramic packages).
Under the above operating conditions, the MECL 10K
quad gate has its junction elevated above ambient
temperature by only 9.8°C.
Even though different device types mounted on a printed
circuit board may each have different power dissipations, all
will have the same input and output levels provided that each
is subject to identical air flow and the same ambient air
temperature. This eases design, since the only change in
levels between devices is due to the increase in ambient
temperatures as the air passes over the devices, or
differences in ambient temperature between two devices.
MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)
AIR FLOW
The effect of air flow over the packages on JA (due to a
decrease in CA) is illustrated in the graphs of Figures 18
through 20. This air flow reduces the thermal resistance of
the package, therefore permitting a corresponding increase
in power dissipation without exceeding the maximum
permissible operating junction temperature.
3500
Alumina Ceramic for
All Packages
3000
2500
24 Lead
2000
1500
1000
14 and 16 Lead
8 Lead
500
0
25
50
75
100
125
150 165 175
200
TA, AMBIENT TEMPERATURESTILL AIR (°C)
2000
1750
24 Lead
1500
16 Lead
1250
14 Lead
1000
750
8 Lead
500
250
0
25
50
75
100
125 140 150
175
200
MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)
MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)
Figure 18. Ambient Temperature Derating Curves (Ceramic Dual–In–Line Package)
2000
1750
1500
28 Lead
1250
1000
750
20 Lead
500
250
0
0
25
50
75
100
125
150
175
200
TA, AMBIENT TEMPERATURE  STILL AIR (°C)
TA, AMBIENT TEMPERATURE (°C)  STILL AIR
Figure 19. Ambient Temperature Derating Curves
(Plastic Dual–In–Line Package)
Figure 20. Ambient Temperature Derating Curves
(PLCC Package)
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200
θJA , AVERAGE THERMAL RESISTANCE (C/W)
°
θJA , AVERAGE THERMAL RESISTANCE (C/W)
°
200
Z-Axis (Transverse)
180
160
Airflow Direction
140
120
8 Lead (Alumina)
100
14 and 16 Lead (Alumina)
80
60
40
24 Lead (Alumina)
20
0
200
400
600
AIRFLOW (Ifpm)
800
180
Z-Axis (Transverse)
160
Airflow Direction
140
120
8 Lead
100
24 Lead
40
20
200
Figure 21. Airflow vs. Thermal Resistance
(Ceramic Dual–In–Line Package)
400
600
AIRFLOW (Ifpm)
800
1000
Figure 22. Airflow vs. Thermal Resistance
(Plastic Dual–In–Line Package)
100
°
θJA , AVERAGE THERMAL RESISTANCE (C/W)
16 Lead
60
0
1000
14 Lead
80
Z-Axis (Transverse)
80
Airflow Direction
60
20 Lead
40
28 Lead
20
0
250
500
AIRFLOW (Ifpm)
750
1000
Figure 23. Airflow vs. Thermal Resistance
(PLCC Package)
Table 13. Thermal Gradient of Junction Temperature
(16–Pin MECL Dual–In–Line Package)
Power Dissipation
(mW)
Junction Temperature Gradient
(°C/Package)
200
0.4
250
0.5
300
0.63
400
0.88
The majority of MECL 10H, MECL 10K, and MECL III
users employ some form of air–flow cooling. As air passes
over each device on a printed circuit board, it absorbs heat
from each package. This heat gradient from the first package
to the last package is a function of the air flow rate and
individual package dissipations. Table 13 provides gradient
data at power levels of 200 mW, 250 mW, 300 mW, and
400 mW with an air flow rate of 500 lfpm. These figures
show the proportionate increase in the junction temperature
of each dual–in–line package as the air passes over each
device. For higher rates of air flow the change in junction
temperature from package to package down the airstream
will be lower due to greater cooling.
Devices mounted on 0.062″ PC board with Z axis spacing 0.5″.
Air flow is 500 lfpm along the Z axis.
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Table 14. Device Junction Temperature vs.
Time to 0.1% Bond Failures
OPTIMIZING THE LONG TERM RELIABILITY OF
PLASTIC PACKAGES
Todays plastic integrated circuit packages are as reliable
as ceramic packages under most environmental conditions.
However when the ultimate in system reliability is required,
thermal management must be considered as a prime system
design goal.
Modern plastic package assembly technology utilizes
gold wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
protracted periods of time an intermetallic compound can
form in the bond area resulting in high impedance contacts
and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device
junction temperature, it is incumbent on the designer to
determine that the device junction temperatures are
consistent with system reliability goals.
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80C
TJ = 90C
TJ = 100C
TJ = 110C
TJ = 120C
°
TJ = 130C
°
NORMALIZED FAILURE RATE
°
= Time in hours to 0.1% bond failure
(1 failure per 1,000 bonds).
= Device junction temperature, °C.
°
11554.267
273.15 T J
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
°
TJ
Time, Years
1,032,200
°
Where: T
Time, Hours
80
Table 14 is graphically illustrated in Figure 24 which
shows that the reliability for plastic and ceramic devices are
the same until elevated junction temperatures induces
intermetallic failures in plastic devices. Early and mid–life
failure rates of plastic devices are not effected by this
intermetallic mechanism.
Predicting Bond Failure Time:
Based on the results of almost ten (10) years of +125°C
operating life testing, a special arrhenius equation has been
developed to show the relationship between junction
temperature and reliability.
(1) T (6.376 10 -9 ) e
Junction Temp °C
1.0
1
10
TIME, YEARS
100
1000
And:
Figure 24. Failure Rate vs. Time Junction
Temperature
(2) TJ = TA + PDJA = TA + TJ
Device junction temperature, °C.
Ambient temperature, °C.
Device power dissipation in watts.
Device thermal resistance, junction to air,
°C/Watt.
TJ = Increase in junction temperature due to
on–chip power dissipation.
Where: TJ
TA
PD
JA
=
=
=
=
MECL Junction Temperatures:
Power levels have been calculated for a number of MECL
10K and MECL 10H devices in 20 pin plastic leaded chip
carriers and translated to the resulting increase of junction
temperature (TJ) for still air and moving air at 500 LFPM
using equation 2 and are shown in Table 15.
Table 14 shows the relationship between junction
temperature, and continuous operating time to 0.1% bond
failure, (1 failure per 1,000 bonds).
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Table 15. Increase in Junction Temperature Due to I/C Power Dissipation. 20 Pin Plastic Leaded Chip Carrier.
MECL 10K
Device Type
TJ, °C
Still Air
TJ, °C
500 LFPM Air
MECL 10H
Device Type
TJ, °C
Still Air
TJ, °C
500 LFPM Air
MC10101
MC10102
MC10103
MC10104
MC10105
MC10106
MC10107
MC10109
MC10110
MC10111
MC10113
MC10114
MC10115
MC10116
MC10117
MC10121
MC10123
MC10124
MC10125
MC10131
MC10133
MC10134
MC10135
MC10136
MC10138
MC10141
MC10153
MC10158
MC10159
MC10160
MC10161
MC10162
MC10164
MC10165
MC10166
MC10168
MC10170
MC10171
MC10172
MC10173
MC10174
MC10175
MC10176
MC10178
MC10186
MC10188
MC10189
MC10192
MC10195
MC10197
MC10198
MC10210
MC10211
MC10212
MC10216
MC10231
21.8
17.6
17.6
20.8
17.2
13.0
19.8
11.7
24.7
24.7
22.2
22.6
16.7
17.2
16.2
13.5
37.6
42.9
–
26.9
34.4
27.0
31.9
52.3
37.0
42.7
34.4
23.9
25.8
32.0
40.7
40.7
31.3
53.7
43.5
34.4
29.9
41.1
41.1
30.5
31.9
43.7
49.6
38.1
49.6
25.4
24.6
67.0
46.7
27.7
21.2
24.5
24.6
24.3
24.1
30.6
14.1
11.4
11.4
13.4
11.2
8.4
12.8
7.7
16.1
16.1
14.3
14.6
10.9
11.1
10.5
8.5
24.0
27.3
–
17.1
21.9
17.2
20.3
32.6
23.2
26.7
21.9
15.2
16.4
20.4
26.0
26.0
20.1
33.6
27.6
21.9
18.9
26.2
26.2
19.3
20.5
27.6
31.3
23.9
31.1
16.4
15.9
43.0
29.9
17.7
13.4
16.0
16.0
15.8
15.6
19.5
MC10H016
MC10H100
MC10H101
MC10H102
MC10H103
MC10H104
MC10H105
MC10H106
MC10H107
MC10H109
MC10H113
MC10H115
MC10H116
MC10H117
MC10H121
MC10H123
MC10H124
MC10H125
MC10H130
MC10H135
MC10H136
MC10H141
MC10H158
MC10H159
MC10H160
MC10H161
MC10H162
MC10H164
MC10H165
MC10H166
MC10H171
MC10H172
MC10H173
MC10H174
MC10H175
MC10H176
MC10H179
MC10H180
MC10H181 (Note 15)
MC10H186
MC10H188
MC10H189
MC10H209
MC10H210
MC10H211
MC10H330 (Note 15)
MC10H332
MC10H334
MC10H350
MC10H351
MC10H352
MC10H424
48.0
16.6
22.1
18.0
18.0
21.0
17.8
13.2
20.0
11.9
22.8
16.7
17.8
16.7
13.9
23.1
44.2
–
28.2
33.2
61.7
44.3
25.3
27.3
32.1
41.5
41.5
31.9
56.3
44.4
41.9
41.9
32.6
32.5
45.9
50.9
35.0
42.4
64.4
50.2
25.8
25.8
18.9
25.0
25.0
65.8
52.2
77.8
–
27.2
27.2
37.7
30.0
10.8
14.5
11.8
11.8
13.5
11.7
8.7
12.9
7.8
14.8
10.9
11.7
11.0
9.1
15.0
28.4
–
18.2
21.4
38.5
28.0
16.4
17.7
20.5
26.7
26.7
20.6
35.8
28.3
26.9
26.9
21.1
21.0
29.6
32.3
22.6
27.2
38.6
31.8
16.7
16.7
12.5
16.4
16.4
36.1
33.5
49.3
–
18.1
18.1
24.3
12. All ECL outputs are loaded with a 50 resistor and assumed operating at 50% duty cycle.
13. TJ for ECL to TTL translators are excluded since the supply current to the TTL section is dependent on frequency, duty cycle and loading.
14. Thermal Resistance (JA) measured with PLCC packages solder attached to traces on 2.24″ x 2.24″ x 0.062″ FR4 type glass epoxy board
with 1 oz./sq. ft. copper (solder–coated) mounted to tester with 3 leads of 24 gauge copper wire.
15. 28 lead PLCC.
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Case Example:
After the desired system failure rate has been established
for failure mechanisms other than intermetallics, each
plastic device in the system should be evaluated for
maximum junction temperature using Table 15. Knowing
the maximum junction temperature refer to Table 14 or
Equation 1 to determine the continuous operating time
required to 0.1% bond failures due to intermetallic
formation. At this time, system reliability departs from the
desired value as indicated in Figure 24.
To illustrate, assume that system ambient air temperature
is 55°C (an accepted industry standard for evaluating system
failure rates). Reference is made to Table 15 to determine the
maximum junction temperature for each device for still air
and transverse air flow of 500 LFPM.
Adding the 55°C ambient to the highest, TJ listed,
77.8°C (for the MC10H334 with no air flow), gives a
maximum junction temperature of 132.8°C. Reference to
Table 14 indicates a departure from the desired failure rate
after about 2 years of constant exposure to this junction
temperature. If 500 LFPM of air flow is utilized, maximum
junction temperature for this device is reduced to 104.3°C
for which Table 14 indicates an increased failure rate in
about 15 years.
Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
used methods include heat sinks for higher powered devices,
refrigerated air flow and lower density board stuffing.
The material presented here emphasizes the need to
consider thermal management as an integral part of system
design and also the tools to determine if the management
methods being considered are adequate to produce the
desired system reliability.
though the ambient temperature is the same. Higher junction
temperatures will cause logic levels to shift.
As an example, a 300 mW 16 lead dual–in–line ceramic
device operated at JA = 100°C/W (in still air) shows a
HIGH logic level shift of about 21 mV above the HIGH logic
level when operated with 500 lfpm air flow and a JA =
50°C/W. (Level shift = TJ × 1.4 mV/°C).
If logic levels of individual devices shift by different
amounts (depending on PD and JA), noise margins are
somewhat reduced. Therefore, the system designer must lay
out his system bearing in mind that the mounting procedures
to be used should minimize thermal effects on noise margin.
The following sections on package mounting and
heatsinking are intended to provide the designer with
sufficient information to insure good noise margins and high
reliability in MECL system use.
MOUNTING AND HEATSINK SUGGESTIONS
With large high–speed logic systems, the use of multilayer
printed circuit boards is recommended to provide both a
better ground plane and a good thermal path for heat
dissipation. Also, a multilayer board allows the use of
microstrip line techniques to provide transmission line
interconnections.
Two–sided printed circuit boards may be used where
board dimensions and package count are small. If possible,
the VCC ground plane should face the bottom of the package
to form the thermal conduction plane. If signal lines must be
placed on both sides of the board, the VEE plane may be used
as the thermal plane, and at the same time may be used as a
pseudo ground plane. The pseudo ground plane becomes the
ac ground reference under the signal lines placed on the
same side as the VCC ground plane (now on the opposite side
of the board from the packages), thus maintaining a
microstrip signal line environment.
Two–ounce copper P/C board is recommended for
thermal conduction and mechanical strength. Also,
mounting holes for low power devices may be countersunk
to allow the package bottom to contact the heat plane. This
technique used along with thermal paste will provide good
thermal conduction.
Printed channeling is a useful technique for conduction of
heat away from the packages when the devices are soldered
into a printed circuit board. As illustrated in Figure 25, this
heat dissipation method could also serve as VEE voltage
distribution or as a ground bus. The channels should
terminate into channel strips at each side or the rear of a
plug–in type printed circuit board. The heat can then be
removed from the circuit board, or board slide rack, by
means of wipers that come into thermal contact with the
edge channels.
THERMAL EFFECTS ON NOISE MARGIN
The data sheet dc specifications for standard MECL 10K
and MECL III devices are given for an operating
temperature range from –30°C to +85°C (0° to +75°C for
MECL 10H and memories). These values are based on
having an airflow of 500 lfpm over socket or P/C board
mounted packages with no special heatsinking (i.e.,
dual–in–line package mounted on lead seating plane with no
contact between bottom of package and socket or P/C board
and flat package mounted with bottom in direct contact with
non–metalized area of P/C board).
The designer may want to use MECL devices under
conditions other than those given above. The majority of the
low–power device types may be used without air and with
higher JA. However, the designer must bear in mind that
junction temperatures will be higher for higher JA, even
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INTERFACING MECL TO SLOWER LOGIC TYPES
MECL circuits are interfaceable with most other logic
forms. For MECL/TTL/DTL interfaces, when MECL is
operated at the recommended –5.2 volts and TTL/DTL at
+5.0 V supply, currently available translator circuits, such as
the MC10124 and MC10125, may be used.
For systems where a dual supply (–5.2 V and +5.0 V) is
not practical, the MC10H350 includes four single supply
MECL to TTL translators, or a discrete component
translator can be designed. For details, see MECL System
Design Handbook (HB205/D). Such circuits can easily be
made fast enough for any available TTL.
MECL also interfaces readily with MOS. With CMOS
operating at +5.0 V, any of the MECL to TTL translators
works very well.
Specific circuitry for use in interfacing MECL families to
other logic types is given in detail in the MECL System
Design Handbook.
Complex MECL 10K devices are presently available for
interfacing MECL with MOS logic, MOS memories, TTL
three–state circuits, and IBM bus logic levels. See
Application Note AN720/D for additional interfacing
information.
CHANNEL
WIPER
Figure 25. Channel/Wiper Heatsinking on Double
Layer Board
For operating some of the higher power device types*
in 16 lead dual–in–line packages in still air, requiring
JA <100°C/W, a suitable heatsink is the IERC
LIC–214A2WCB shown in Figure 26. This sink reduces the
still air JA to around 55°C/W. By mounting this heatsink
directly on a copper ground plane (using silicone paste) and
passing 500 lfpm air over the packages, JA is reduced to
approximately 35°C/W, permitting use at higher ambient
temperatures than +85°C (+75°C for MECL 10H memories)
or in lowering TJ for improved reliability.
*10136 and 10H136 Max PD > 800 mW.
CIRCUIT INTERCONNECTIONS
Though not necessarily essential, the use of multilayer
printed circuit boards offers a number of advantages in the
development of high–speed logic cards. Not only do
multilayer boards achieve a much higher package density,
interconnecting leads are kept shorter, thus minimizing
propagation delay between packages. This is particularly
beneficial with MECL III which has relatively fast (1.0 ns)
rise and fall times. Moreover, the unbroken ground planes
made possible with multilayer boards permit much more
precise control of transmission line impedances when these
are used for interconnecting purposes. Thus multilayer
boards are recommended for MECL III layouts and are
justified when operating MECL 10H and MECL 10K at top
circuit speed, when high–density package is a requirement,
or when transmission line interconnects are used.
Point–to–point back–plane wiring without matched line
terminations may be employed for MECL interconnections
if line runs are kept short. At MECL 10K speeds, this applies
to line runs up to 6 inches, for MECL 10H and MECL III up
to 1 inch (Maximum open wire lengths for less than 100 mV
undershoot). But, because of the open–emitter outputs of
MECL 10H, MECL 10K and MECL III circuits, pull–down
resistors are always required. Several ways of connecting
such pull–down resistors are shown in Figures 27, 28,
and 29.
Mounting
Screws
Retainer Clip
IERC DC
000080B
16-Pine Dual
In-Line
Ceramic
Package
Thermal
Paste
Heat Dissipator
IERC-LIC-214A2WCB
Mounting
Hole
Strip
Lines
Multi-Layer
PC Board
Figure 26. MECL High–Power Dual–In–Line Package
Mounting Method
It should be noted that the use of a heatsink on the top
surface of the dual–in–line package is not very effective in
lowering the JA. This is due to the location of the die near
the bottom surface of the package. Also, very little (< 10%)
of the internal heat is withdrawn through the package leads
due to the isolation from the ceramic by the solder glass seals
and the limited heat conduction from the die through 1.0 to
1.5 mil aluminum bonding wires.
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transmission line terminated to –2.0 Vdc. This is the
equivalent current load of 22 mA in the HIGH logic state and
6.0 mA in the LOW state.
Parallel termination of transmission lines can be done in
two ways. One, as shown in Figure 30, uses a single resistor
whose value is equal to the impedance (Zo) of the line. A
terminating voltage (VTT) of –2.0 Vdc must be supplied to
the terminating resistor.
Another method of parallel termination uses a pair of
resistors, R1 and R2. Figure 31 illustrates this method. The
following two equations are used to calculate the values of
R1 and R2:
R1 = 1.6 Zo
R2 = 2.6 Zo
Resistor values for the connection in Figure 27 may range
from 270 ohms to k depending on power and load
requirements. (See MECL System Design Handbook.)
Power may be saved by connecting pull–down resistors in
the range of 50 ohms to 150 ohms, to –2.0 Vdc, as shown in
Figure 28. Use of a series damping resistor, Figure 29, will
extend permissible lengths of unmatched–impedance
interconnections, with some loss of edge speed.
With proper choice of the series damping resistor, line
lengths can be extended to any length,** while limiting
overshoot and undershoot to a predetermined amount.
Damping resistors usually range in value from 10 ohms to
100 ohms, depending on the line length, fanout, and line
impedance, the open emitter–follower outputs of
MECL 10H, MECL III and MECL 10K give the system
designer all possible line driving options.
One major advantage of MECL over saturated logic is its
capability for driving matched–impedance transmission
lines. Use of transmission lines retains signal integrity
over long distances. The MECL 10H and MECL 10K
emitter–follower output transistors will drive a 50–ohm
Another popular approach is the series–terminated
transmission line (see Figures 30 and 31). This differs from
parallel termination in that only one–half the logic swing is
propagated through the lines. The logic swing doubles at the
end of the transmission line due to reflection on an open line,
again establishing a full logic swing.
Pull–Down Resistor Techniques
RP
RP
-5.2 V
-2.0 V ( V TT)
Figure 27.
Figure 28.
RD
RP
-5.2 V
Figure 29.
tpd
To maintain clean wave fronts, the input impedance of the
driven gate must be much greater than the characteristic
impedance of the transmission line. This condition is
satisfied by MECL circuits which have high impedance
inputs. Using the appropriate terminating resistor (RS) at
point A (Figure 32), the reflections in the transmission line
will be terminated.
A
Zo
B
VL
to
VL
to
Zo
VTT (-2.0 V)
Figure 30. Parallel Terminated Line
** Limited only by line attenuation and band–width characteristics.
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Wire–wrapped connections can be used with MECL 10K.
For MECL III and MECL 10H, the fast edge speeds (1.0 ns)
create a mismatch at the wire–wrap connections which can
cause reflections, thus reducing noise immunity. The
mismatch occurs also with MECL 10K, but the distance
between the wire–wrap connections and the end of the line
is generally short enough so the reflections cause no
problem.
Series damping resistors may be used with wire–wrapped
lines to extend permissible backplane wiring lengths.
Twisted pair lines may be used for even longer distances
across large wire–wrapped cards. The twisted pair gives a
more defined characteristic impedance (than a single wire),
and can be connected either single–ended, or differentially
using a line receiver.
The recommended wire–wrapped circuit cards have a
ground plane on one side and a voltage plane on the other
side to insure a good ground and a stable voltage source for
the circuits. In addition, the ground plane near the
wire–wrapped lines lowers the impedance of those lines and
facilitates terminating the line. Finally, the ground plane
serves to minimize cross talk between parallel paths in the
signal lines. Point–to–point wire routing is recommended
because cross talk will be minimized and line lengths will be
shortest. Commercial wire–wrap boards designed for
MECL 10K are available from several vendors.
R1
Zo
R2
-5.2 V
Figure 31. Parallel Termination – Thevenin Equivalent
tpd
RS
A
B
Zo
RP
C
VEE
A
VL
50%
VL
B
tpd
50%
tpd
tpd
tpd
VL/2
C
VL
50%
Figure 32. Series Terminated Line
The advantages of series termination include ease of
driving multiple series–terminated lines, low power
consumption, and low cross talk between adjacent lines. The
disadvantage of this system is that loads may not be
distributed along the transmission line due to the one–half
logic swing present at intermediate points.
For board–to–board interconnections, coaxial cable may
be used for signal conductors. The termination techniques
just discussed also apply when using coax. Coaxial cable has
the advantages of good noise immunity and low attenuation
at high frequencies.
Twisted pair lines are one of the most popular methods of
interconnecting cards or panels. The complementary
outputs of any MECL function may be connected to one end
of the twisted pair line, and any MECL differential line
receiver to the other as shown in the example, Figure 33. RT
is used to terminate the twisted pair line. The 1 to 1.5 V
common–mode noise rejection of the line receiver ignores
common–mode cross talk, permitting multiple twisted pair
lines to be tied into cables. MECL signals may be sent very
long distances (> 1000 feet) on twisted pair, although line
attenuation will limit bandwidth, degrading edge speeds
when long line runs are made.
If timing is critical, parallel signals paths (shown in
Figure 34) should be used when fanout to several cards is
required. This will eliminate distortion caused by long stub
lengths off a signal path.
390
Zo
100
RT
390
VEE
Figure 33. Twisted Pair Line Driver/Receiver
Card A
Card B
Card C
Rp
VEE
*
Card A
Zo
Card B
Zo
Card C
Zo
RT = Zo (each)
VTT
*Multiple output gate eg MC10110
Figure 34. Parallel Fanout Techniques
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Microstrip and Stripline
Microstrip and stripline techniques are used with printed
circuit boards to form transmission lines. Microstrip
consists of a constant–width conductor on one side of a
circuit board, with a ground plane on the other side (shown
in Figure 35). The characteristic impedance is determined
by the width and thickness of the conductor, the thickness of
the circuit board, and the dielectric constant of the circuit
board material.
FAN-OUT = 4
EACH
ON
CARD
OFF
CARD
RT
R = 1
0.0014 (AIR)
0.062
R = 4.5
EPOXY GLASS
0.0014
0.008
0.008
W
R = 4.5
EPOXY
GLASS
Figure 35. PC Interconnection Lines for use
with MECL
Stripline is used with multilayer circuit boards as shown
in Figure 35. Stripline consists of a constant–width
conductor between two ground planes.
Refer to MECL System Design Handbook for a full
discussion of the properties and use of these.
Figure 36. 64 Fanout Clock Distribution
(Proper Termination Required)
4. To minimize clock skewing problems on
synchronous sections of the system, line delays
should be matched to within 1.0 ns.
5. Parallel drive gates should be used when clocking
repetition rates are high, or when high capacitance
loads occur. The bandwidth of a MECL III gate
may be extended by paralleling both halves of a
dual gate. Approximately 40 or 50 MHz bandwidth
can be gained by paralleling two or three clock
driver gates.
6. Fanout limits should be applied to clock distribution
drivers. Four to six loads should be the maximum
load per driver for best high speed performance.
Avoid large lumped loads at the end of lines greater
than 3 inches. A lumped load, if used, should be four
or fewer loads.
7. For wire–OR (emitter dotting), two–way lines
(busses) are recommended. To produce such lines,
both ends of a transmission line are terminated
with 100–ohm impedance. This method should be
used when wire–OR connections exceed 1 inch
apart on a drive line.
CLOCK DISTRIBUTION
Clock distribution can be a system problem. At MECL
10K speeds, either coaxial cable or twisted pair line (using
the MC10101 and MC10115) can be used to distribute clock
signals throughout a system. Clock line lengths should be
controlled and matched when timing could be critical. Once
the clocking signals arrive on card, a tree distribution should
be used for large–fanouts at high frequency. An example of
the application of the technique is shown in Figure 36.
Because of the very high clock rates encountered in
MECL III systems, rules for clocking are more rigorous than
in slower systems.
The following guidelines should be followed for best results:
On–Card Synchronous Clock Distribution
via Transmission Line
1. Use the NOR output in developing clock chains or
trees. Do not mix OR and NOR outputs in the chain.
2. Use balanced fanouts on the clock drivers.
3. Overshoot can be reduced by using two parallel
drive lines in place of one drive line with twice the
lumped load.
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Off–Card Clock Distribution
Propagation delay is increased approximately 50 ps per
wire–OR connection. In general, wire–OR should be limited
to 6 MECL outputs to maintain a proper LOW logic level.
The MC10123 is an exception to this rule because it has a
special VOL level that allows very high fanout on a bus or
wire–OR line. The use of a single output pull–down resistor
is recommended per wire–OR, to economize on power
dissipation. However, two pull–down resistors per
wired–OR can improve fall times and be used for double
termination of busses.
Wire–OR should be done between gates in a package or
nearby packages to avoid spikes due to line propagation
delay. This does not apply to bus lines which activate only
one driver at a time.
1. The OR/NOR outputs of an MC1660 may be
used to drive into twisted pair lines or into flat,
fixed–impedance ribbon cable. At the far end of the
twisted pair on MC1692 differential line receiver is
used. The line should be terminated as shown in
Figure 33. This method not only provides high
speed, board–to–board clock distribution, but also
provides system noise margin advantages. Since
the line receiver operates independently of the VBB
reference voltage (differential inputs) the noise
margin from board to board is also independent
of temperature differentials.
LOGIC SHORTCUTS
MECL circuitry offers several logic design conveniences.
Among these are:
1. Wire–OR (can be produced by wiring MECL
output emitters together outside packages).
2. Complementary Logic Outputs (both OR and
NOR are brought out to package pins in most cases).
An example of the use of these two features to reduce gate
and package count is shown in Figure 37.
The connection shown saves several gate circuits over
performing the same functions with non–ECL type logic.
Also, the logic functions in Figure 37 are all accomplished
with one gate propagation delay time for best system
speed. Wire–ORing permits direct connections of MECL
circuits to busses. (MECL System Design Handbook and
Application Note AN726/D).
A
AB + CD
B
RP
C
C+D+E+F+G
D
RP
E
F
G
A+B+E+F+G
RP
MC10105
Figure 37. Use of Wire–OR and Complementary
Outputs
Table 16. System Considerations – A Summary of Recommendations
MECL 10H
Power Supply Regulation
On–Card Temperature Gradient
Maximum Non–Transmission Line Length
(No Damping Resistor)
Unused Inputs
PC Board
Cooling Requirements
Bus Connection Capability
Maximum Twisted Pair Length
(Differential Drive)
The Ground Plane to Occupy Percent
Area of Card
Wire Wrap may be used
Compatible with MECL 10,000
16. All DC and AC parameters guaranteed for VEE = –5.2 V ± 5%.
17. At the devices (functional only).
18. Except special functions without input pull–down resistors.
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MECL 10K
±5% (Note 16)
10% (Note 17)
20°C
Less Than 25°C
1″
8″
Leave Open (Note 18)
Leave Open (Note 18)
Multilayer
Standard 2–Sided or
Multilayer
500 lfpm Air
500 lfpm Air
Yes (Wire–OR)
Yes (Wire–OR)
Limited by Cable
Response Only,
Usually >1000′
Limited by Cable
Response Only,
Usually >1000′
>75%
>50%
Not Recommended
Yes
Yes
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Notes
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MECL, MECL 10K, MECL 10H and MECL III are trademarks of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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