Logic: Standard, Special and Programmable In Brief . . . Page Motorola Programmable Arrays (MPA) . . . . . . . . . . . . 3.1–1 Selection by Function Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–8 Device Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–36 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–46 Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–50 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–83 Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–83 Pin Conversion Tables . . . . . . . . . . . . . . . . . . . . . . . 3.1–83 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–84 This selector guide is a quick reference to Motorola’s vast offering of standard logic integrated circuits. In TTL, popular due to its ease of use, low cost, medium–to–high speed operation and good output drive capability, Motorola offers both LS and FAST. Motorola’s CMOS portfolio includes MC14000B standard CMOS series devices, High–Speed CMOS consisting of a full line of products that are pinout– compatible with many LSTTL and MC14000B standard CMOS logic devices which offers designers a solution to the long–standing combined barrier — high speed and low power. Motorola’s Emitter Coupled Logic (MECL) is a non–saturated form of digital logic which eliminates transistor storage time permitting very high speed operation. Motorola offers five versions of MECL: MECL 10K, MECL 10H, MECL III, and the recently introduced families ECLinPS (ECL in picoseconds) and ECLinPS Lite. Also included are timing solution products such as clock drivers, clock generators and programmable delay chips, high performance and communications products such as VCO’s, prescalers, and synthesizers, and a wide variety of translators, low–voltage bus interface and serial data transmission devices. Field programmable logic and in particular, field programmable arrays, have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, reconfigurable arrays have been used to enhance Customer product flexibility in ways that no other technology can match. Motorola Master Selection Guide 3.0–1 Logic: Standard, Special and Programmable INTRODUCTION TO MOTOROLA PROGRAMMABLE ARRAYS AND THE MPA DESIGN SYSTEM Field programmable logic and in particular, field programmable arrays, have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, reconfigurable arrays have been used to enhance Customer product flexibility in ways that no other technology can match. Programmable logic not only vastly reduces the time necessary to implement a static design, but significant product feature benefits can be realized when hardware can be dynamically altered as easily as software. The reconfigurable Motorola Programmable Array (MPA) and MPA design system maximize application flexibility and minimize time to market by delivering a gate level, push button, programmable logic solution. architecture is ideal for traditional schematic driven or high level language based design capture methods. In fact, logic synthesis tools were originally designed for and produce the most efficient results for targeting gate level devices. A design is analyzed, optimized, transformed into MPA cells, partitioned, placed and routed based on timing constraints for all paths in the design – automatically. A netlist from one of the popular design capture systems or an existing XNF or LPM netlist is imported into the MPA design system. The logic is mapped to a series of MPA cells and the entire resulting netlist is optimized and checked. Based on a simple clock specification, the MPA design system generates timing constraints for all paths in the design. During automatic partitioning, placement and routing path slack time is constantly redistributed insuring only the resources required to meet timing requirements are consumed. Because MPA tools implement the design according to constraints, tool induced design iterations are virtually eliminated. Completed layouts can be transformed into device configurations, as well as annotated simulation netlists. A layout browser is also available. The MPA design system also includes complete on–line, hypermedia, help covers the device, the design system and the integration kits. Integration kits for Viewlogic, Exemplar, VHDL (1076 and SDF), Verilog (OVI and SDF) and OrCAD are included (contact your vendor for additional kits).All these features add up to a powerful yet extremely easy to use design implementation engine for the MPA product family. Design Capture Logic system designers have two basic options when selecting a method for capturing their designs. For smaller or very regular designs, schematic capture continues to be a popular design entry vehicle. With the increasing size and complexity of today’s designs coupled with decreasing design cycle time requirements, many designers are turning to Hardware Description Languages (HDLs). The MPA family was designed from the outset to be well suited to both methodologies. The output of logic synthesis compilers maps effortlessly and efficiently onto the MPA architecture. Unlike other FPGA offerings, the MPA poses no significant architectural limitations for which the designer might otherwise have to adjust his schematic design techniques for. Design Importation Push Button Design Implementation Designs can be captured using schematics, a high level language, or a combination of these entry methods using commercially available design capture and logic synthesis software and the appropriate interface kit. Alternatively, existing designs can be retargeted from other programmable logic devices to the MPA device using commercial logic synthesis tools or the powerful retargetting capabilities provided with MPA design system. Design importation begins with a netlist and an optional clock specification file. The clock specification file provides a mechanism for the user or design capture tools to document system level timing requirements. In addition, a rich set of attributes can be attached to specific components or nets within the design to specify timing and design pinout constraints. The MPA design system minimizes training investment and automatically generates design implementations which meet timing constraints. The gate level logic and abundant hierarchical routing resources of the MPA device present a rich implementation media for design implementation. MPA design tools understand and optimally utilize the MPA device resources so there are no elaborate rules to learn or design modifications required to begin design capture. Staying focused on end product design rather than implementation tools or device architecture gets the design done faster and, unlike other programmable solutions, without programmable logic device specificity to impede future design migration efforts. The combination of automatic tools and gate level Motorola Master Selection Guide 3.1–1 Logic: Standard, Special and Programmable A retargetting rules file is read and the input netlist is transformed into a series of MPA cells and associated interconnections. Rules files provide a mechanism to perform attribute mapping, cell mapping and macro expansion. By creating custom rule files, the user can extend the importation process from arbitrary sources. The MPA design system comes with rules for it’s native library/EDIF. The resulting netlist is optimized to clip unused logic and remove redundant logic. For example: each MPA cell has programmable input inversion capability. All Inverters or non–inverting buffers can be removed from the netlist and replaced with signal sense information attached to each input. A series of design rule checks are performed to insure design integrity before the layout process begins. the same size called clusters. A cluster boundary delay estimation is applied to pull the most tightly constrained paths into a minimum number of clusters. The clusters are then assigned to zones talking into account zonal boundary delay cost and relative zone placement delay costs. Other costs like total number of port connections per zone and are also considered. As assignment proceeds, cluster and zone boundary delay costs are added to each path and slack is recomputed. Next global placement and routing is done. Global routes begin and end on either I/O cells or port cells. Intrazone placement and routing is deferred to a later phase. During global routing all the port cell and I/O cell locations are fixed and the connections between them established. High fanout nets are constructed in a highly regular manner to insure efficient resource utilization. As in partitioning, slack estimates are refined throughout global routing. Constraint Generation Finally the intrazonal placement and routing is done. Cells assigned to a particular zone are placed and routed to other zone cells or zone port cells. Port cells and core cells are constructed to allow port swapping. Core cells can be routed through if necessary. Allowing core cells to act as routing cells allows dynamic adjustment of routing resources within the zone. Dynamic resource adjustment is a powerful design specific adaptation mechanism. Timing constraints, the optimized MPA netlist and static timing analysis is used to generate path slack constraints for all paths in the design. Each unique signal pathway between a register output and a register input throughout the design are enumerated. The total logic and estimated or real wire delays along the path are summed. The time between the active upstream register clock edge and the next active downstream clock edge minus the downstream register setup time is subtracted from the total path delay. This difference is called path slack. If any path in the design has a negative slack value, the implementation will not function at the required clock rate(s). Path constraints are utilized throughout the layout process to insure that a design implementation which meets timing constraints is automatically generated. If no clock or timing specifications are provided, the MPA design system uses the fastest possible clock based on very small net delay estimates to generate the path constraints. This usually results in the best possible implementation, but may take longer than the time required to generate a satisfactory rather than best possible result. Contrast this to other programmable logic design tools which only provide manual net constraint annotation or net criticality assignment. In these cases significant effort is necessary to generate constraints and many costly iterations are required to tune these constraints for a given design. If any changes are made to the design, another costly round of iterations is required. This process produces a layout from which device configurations, delay back annotations, and chipviews can be generated. Incremental Design Support When specification changes necessitate design iterations, simply push the button again. Constraints are automatically recalculated and autolayout only reworks those portions of the design which have changed. Full incremental design support means simple design changes to facilitate design verification can be made quickly and easily. Delay Back Annotation Designs can be verified through numerous methods. One particularly useful method is the annotation of device and implementation specific delays back into the original simulation environment to improve system or device level simulation accuracy. A MPA device layout can be transformed into an appropriately formatted delay annotation file or annotated netlist quickly and easily. The annotated delay information represents the worst case delays for a given device speed grade. Autolayout The autolayout process makes use of the hierarchical organization of the MPA device to minimize run time and deliver implementations that meet timing requirements. Designs which have diverse timing requirements are ideally implemented because path slack estimates are refined throughout the autolayout process insuring only the resources required to meet timing requirements are consumed. The process begins by flattening the design and partitioning it into small component groups of approximately Logic: Standard, Special and Programmable Chipview While the MPA design system provides a rich set of reports describing the implementation of a design, a graphical view of the implementation can be indispensable for reviewing overall layout quality. Chipview provides a graphical view of a completed layout. Chipview can be useful during initial design iterations to visually verify I/O pin placements before commencing PCB layout, for example. 3.1–2 Motorola Master Selection Guide Configuration at no charge on the MPA design system CDROM. Other kits can be acquired directly from the vendor. Refer to the MPA Design System Product List for more information. A layout can be transformed into a device configuration which, when loaded into the appropriate MPA device, produces a physical design realization. Many formatting options are available. The MPA download pod can be used to emulate a serial PROM. Using the pod, device configuration files can be downloaded to a device directly from the PC or workstation development environment. Low Cost, Easy Access MPA Design systems are easy to use, competitively priced and widely available. Copies of MPA design system software supporting up to 8000 gates can be downloaded from the World Wide Web (WWW) at URL: Integration Kits http://sps.motorola.com/fpga The MPA design system can be used with a large number of commercial electronic design automation software. For each supported vendor, an integration kit is provided which facilitates MPA design within that vendors’ environment. Many of these kits are available from Motorola and included Motorola Master Selection Guide Complete kits including download pod, evaluation board, MPA device, CDROM and documentation can be ordered from your local authorized Motorola distributor or Motorola sales representative. 3.1–3 Logic: Standard, Special and Programmable MPA Family Overview SEMICONDUCTOR TECHNICAL DATA The Motorola Programmable Array (MPA) design system is a bridge between a design capture environment and Motorola field programmable arrays. The MPA design system automatically transforms designs into device configurations to realize a design, when loaded into an MPA device. A design is automatically analyzed, optimized, transformed into MPA cells, partitioned, placed and routed based on timing constraints for every path in the design. MPA design tools understand and optimally utilize the MPA device architecture; this eliminates the need to learn a new set of rules and makes these tools ideally suited for use with logic synthesis. Full incremental design support reduces design implementation time and powerful library retargeting capabilities allow you to reuse designs which may have been implemented on less capable devices. The MPA design system operates on existing hardware platforms and supports design capture and simulation tools from more than 10 vendors. All these features plus on–line, hypermedia, help make the MPA design system a powerful, yet extremely easy to use, design implementation engine. Features • • • • • • • • • Layout viewer Push Button Implementation Optimal Use of MPA Device Resources Optimal Results with Gate Level Design Input Library of Common MSI Functions Design Flow Manager Design Retargeter Timing Driven with Integrated Static Timing Analysis Layout Delay extraction for post layout simulation • Incremental design support • On–line, hypermedia, documentation • Supports all popular design capture and simulation tools • Lowest cost FPGA development systems. • Instant access; Downloading via the internet (WWW, ftp). • Supports multiple speed grades Design Importation • Read Appropriate Rules File • Retarget to MPA Primitives • Macro Expansion • Design Optimization • Design Rule Checks Constraint Generation • Read User Constraints • Path Enumeration • Path Constraint Generation Chipview • Read Stored Layout • Construct Graphical Representation Timing Driven Autolayout • Partition Design Into Clusters • Assign Clusters to Zones • Global Place & Route • Zonal Place & Route • Continuous Slack Redistribution Delay Annotation • Read Stored Layout • Construct Annotated Netlist Configuration • Read Stored Layout • Construct Bitstream MPA Device Logic: Standard, Special and Programmable 3.1–4 Motorola Master Selection Guide MPA Family Overview SEMICONDUCTOR TECHNICAL DATA Motorola Programmable Array (MPA) products are a high density, high performance, low cost, solution for your reconfigurable logic needs. When used with our automatic high performance design tools, MPA delivers custom logic solutions in minutes rather than weeks. And the low cost keeps those solutions competitive throughout the product lifecycle. The MPA architecture has solved the historical problems associated with fine grain devices without sacrificing re–programmability, reliability, or cost. MPA1000 devices are reprogrammable SRAM based products manufactured on a standard 0.43µ Leff CMOS process with logic capacities from 3,500 to more than 22,000 equivalent FPGA gates. MPA Logic resources hold a single gate or storage element providing a highly efficient, adaptable, design implementation medium. Gate level logic resources, abundant hierarchical interconnection resources and automatic, timing driven, tools work together to quickly provide design implementations that meet timing constraints without sacrificing device utilization. Staying focused on end product design rather than implementation tools or device architecture gets the design done faster and, unlike other programmable solutions, without programmable logic device specificity to impede future design migration efforts. The combination of automatic tools and gate level architecture is ideal for traditional schematic driven or high level language based design methodologies. In fact, logic synthesis tools were originally designed for and produce the most efficient results when targeting gate level devices. High MPA1000 register count and controlled clock skew is ideal for designs employing pipelining techniques such as communications. The unique set of MPA1000 I/O programming options make these devices suitable for industrial and computer interfacing circuits. PROGRAMMABLE ARRAY 3,500 to 22,000 GATES • • • • • • • • Multiple I/O from 80–200 I/O Pins Programmable 3V/5V I/O at Any Site Multiple Packaging Options Fine Grain Structure Is Optimized for Logic Synthesis Programmable Output Drive, 4/6mA @ 5.0V and 3.3V High Register Count, with 560–2,900 Flip–Flops IEEE 1149.1 JTAG Boundary Scan Eight Low–Skew (<1ns) Clocks MPA1000 Family Members FPGA Gates* Part No. Logic Cells Internal Flip–Flops I/O Cell Flip–Flops Avail I/O Pins Packages Availability 3500 MPA1016FN MPA1016DD 1600 400 122 160 61 80 84 PLCC 128 PQFP NOW NOW 8000 MPA1036FN MPA1036DD MPA1036DH MPA1036HI 3600 900 122 160 240 240 61 80 120 120 84 PLCC 128 PQFP 160 PQFP 181 PGA NOW NOW NOW NOW 14200 MPA1064DH MPA1064DK MPA1064KE MPA1064BG 6400 1600 240 320 320 320 120 160 160 160 160 PQFP 208 PQFP 224 PGA 256 PBGA NOW NOW NOW 3Q97 22000 MPA1100DK MPA1100HV MPA1100BG 10000 2500 320 400 400 160 200 200 208 PQFP 299 PGA 256 PBGA NOW NOW 3Q97 * Equivalent to Industry Standards, as supplied by most manufacturers. Motorola Master Selection Guide 3.1–5 Logic: Standard, Special and Programmable MPA Family Overview SEMICONDUCTOR TECHNICAL DATA The MPA17128, MPA1765 serial OTP EPROMs provide a compact, low pin count, non–volatile configuration store for MPA1000 devices. MPA17000 devices can be cascaded for increased memory capacity when needed. They are available in the standard 8–pin plastic DIP (N suffix), 8–pin SOIC (D suffix) and 20–pin PLCC (FN suffix) packages. • Configuration EPROM for MPA1000 Devices • • • • • • • • • • Voltage Range — 4.5 to 6.0V Maximum Read Current of 10mA Standby Current of 10µA, Typical Industry Standard Synchronous Serial Interface Full Static Operation 10MHz Maximum Clock Rate at 5.0V Programmable Polarity on Hardware Reset Programs With Industry Standard Programmers Electrostatic Discharge Protection > 2000 Volts 8–Pin PDIP and SOIC; 20–Pin PLCC Packages 128K, 64K SERIAL EPROM 8 • Commercial (0 to +70°C) and Industrial (–40 to +85°C) 1 P SUFFIX PLASTIC PACKAGE CASE 626–05 8–Lead Pinouts (Top View) 8 DATA 1 8 VCC CLK 2 7 Vpp 1 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–05 6 CEO RESET/OE 3 CE 4 5 Vss 8 19 3 FN SUFFIX PLCC PACKAGE CASE 775–02 20–Lead Pinout (Top View) NC Vpp NC NC CEO 18 17 16 15 14 NC 19 13 NC VCC 20 12 NC NC 1 11 NC DATA 2 10 Vss NC 3 9 NC 4 5 6 7 CLK NC RESET/ NC OE Logic: Standard, Special and Programmable 4 PIN NAMES 8 CE 3.1–6 Pins Function DATA CLK RESET/OE CE VSS CEO VPP VCC NC Data I/O Clock Reset Input and Output Enable Chip Enable Input Ground Chip Enable Output Programming Voltage Supply +4.5 to 6.0V Power Supply Not Connected Motorola Master Selection Guide MPA Family Overview SEMICONDUCTOR TECHNICAL DATA The MPA17C256 is an easy to use and cost effective serial configuration memory ideally suited for use with today’s popular SRAM based FPGAs. The MPA17C256 is available in 8–pin PDIP and 20–pin SOIC and PLCC packages, adhering to industry standard pinouts. The device interfaces downstream FPGA(s) with a very simple enable, clock and data interface. The MPA17C256 is reprogrammable with no need for a higher programming “super voltage”; it may even be reprogrammed on board. The MPA17C256 also has user programmable RESET/OE polarity. MPA17C256 P SUFFIX 8–LEAD PLASTIC PACKAGE CASE 626–05 • EE Programmable 262,144 x 1 bit Serial Memories Designed to Store Configuration Programs for FPGAs • Simple Interface to SRAM FPGAs • Cascadable to Support Additional Configurations or Future Higher Density FPGAs • Low Power CMOS EEPROM Process • Programmable Reset Polarity • Available in Space Efficient 8–Pin PDIP, 20–Pin SOIC and 20–Pin PLCC Packages DW SUFFIX 20–LEAD PLASTIC SOIC WIDE PACKAGE CASE 751D–04 • In–System Programmable via 2–Wire Bus FN SUFFIX 20–LEAD PLCC PACKAGE CASE 775–02 Controlling the MPA17C256 Serial EEPROM Most connections between the FPGA device and the Serial EEPROM are simple and self–explanatory: PIN NAMES • The DATA output of the MPA17C256 drives DIN of the FPGA devices Pins Function • The master FPGA DCLK output drives the CLK input of the MPA17C256 • The CEO output of the first MPA17C256 drives the CE input of the next MPA17C256 in a cascade chain of EEPROMs. • SER_EN must be connected to VCC • CE enables the chip and is required to enable the DATA output pin DATA CLK RESET/OE CE VSS CEO SER_EN VCC NC Data I/O Clock Reset Input and Output Enable Chip Enable Input Ground Chip Enable Output Programming Enable +4.5 to 6.0V Power Supply Not Connected • RESET/OE is chip reset and is part of the DATA output enable structure This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola Master Selection Guide 3.1–7 Logic: Standard, Special and Programmable Selection by Function In order to better serve our customers, we have made some modifications to the Selection by Function portion of the Logic Selector Guide. For easy selection of Logic’s newer, more complex functions, as well as standard family functions, refer to the subject index below. Within the Selection by Function tables on the next 27 pages, you will find functions sorted by these broad subjects, and then broken down alphabetically into more precise functions. Logic Functions AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–9 ARITHMETIC OPERATORS . . . . . . . . . . . . . . . . . . 3.1–9 BOUNCE ELIMINATOR . . . . . . . . . . . . . . . . . . . . . . 3.1–9 BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–9 BUFFERS, 3–STATE . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–9 BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–10 CBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–12 CLOCK DISTRIBUTION CHIPS . . . . . . . . . . . . . . 3.1–12 CLOCK DRIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–12 COAX CABLE DRIVERS . . . . . . . . . . . . . . . . . . . . 3.1–13 COMPARATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–14 CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–14 COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–14 DECODER/DEMULTIPLEXERS . . . . . . . . . . . . . . 3.1–16 DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–17 DISPLAY DECODE DRIVERS . . . . . . . . . . . . . . . . 3.1–17 DIVIDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–17 DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–17 EDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–17 ENCODERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–17 ENCODER/DECODERS . . . . . . . . . . . . . . . . . . . . . 3.1–18 EXPANDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–18 FIELD PROGRAMMABLE GATE ARRAYS . . . . . 3.1–18 FLIP–FLOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–18 GATES, AND/NAND . . . . . . . . . . . . . . . . . . . . . . . . 3.1–21 GATES, COMPLEX . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–22 GATES, EXCLUSIVE OR/EXCLUSIVE NOR . . . 3.1–23 GATES, NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–24 Logic: Standard, Special and Programmable GATES, OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDUSTRIAL CONTROL UNIT . . . . . . . . . . . . . . . INVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVERTER/BUFFERS, 2–STATE . . . . . . . . . . . . . LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY SUPPORT . . . . . . . . . . . . . . . . . . . . . . . MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . MULTIPLEXER/DATA SELECTORS . . . . . . . . . . . MULTIVIBRATORS . . . . . . . . . . . . . . . . . . . . . . . . . OSCILLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSCILLATOR/TIMERS . . . . . . . . . . . . . . . . . . . . . . PARITY CHECKERS . . . . . . . . . . . . . . . . . . . . . . . . PHASE–LOCKED LOOP . . . . . . . . . . . . . . . . . . . . PRESCALERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMABLE DELAY CHIPS . . . . . . . . . . . . RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER FILES . . . . . . . . . . . . . . . . . . . . . . . . . . SCHMITT TRIGGERS . . . . . . . . . . . . . . . . . . . . . . . SCSI BUS TERMINATORS . . . . . . . . . . . . . . . . . . SERIAL EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . SHIFT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . SYNTHESIZERS . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSCEIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–8 3.1–24 3.1–25 3.1–25 3.1–25 3.1–26 3.1–27 3.1–27 3.1–27 3.1–29 3.1–29 3.1–30 3.1–30 3.1–30 3.1–30 3.1–31 3.1–31 3.1–31 3.1–32 3.1–32 3.1–32 3.1–32 3.1–32 3.1–32 3.1–34 3.1–34 3.1–34 3.1–35 Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM AMPLIFIER Fiber Optic Post Amplifier ECL MC10SX1125 – 16 D TTL MC74F181 – 24 N DW TTL MC74F381 – 20 N DW TTL MC74F382 – 20 N DW ECL MC10H181 – 24 P,L, PW, LW FN ECL MC10181 – 24 P,L TTL MC74F283 – 16 N D TTL SN54LS83A SN74LS83A 14 N,J D TTL SN54LS283 SN74LS283 16 N,J D 4–Bit Full Adder CMOS MC14008B – 16 P,L D 9’s Complementer CMOS MC14561B – 14 P D BCD Rate Multiplier CMOS MC14527B – 16 P DW Carry Lookahead Generator TTL MC74F182 – 16 N D Dual 2–Bit Adder/Subtractor ECL MC10H180 – 16 P,L FN ARITHMETIC OPERATORS 4–Bit Arithmetic Logic Unit 4–Bit Arithmetic Logic Unit/Function Generator 4–Bit Binary Full Adder With Fast Carry ECL MC10180 – 16 P,L Look Ahead Carry Block ECL MC10H179 – 16 P,L FN NBCD Adder CMOS MC14560B – 16 P,L D Triple Serial Adder (Negative Logic) CMOS MC14038B – 16 L CMOS MC14490 – 16 P,L 1:2 Differential Fanout Buffer ECL MC100LVEL11 8 D 2:8 Differential Fanout Buffer ECL MC100LVE310 MC100E310 28 FN Dual 1:3 Fanout Buffer ECL MC100LVEL13 MC100EL13 20 Expandable Buffer DTL MC832 Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer, ECL/PECL Compatible ECL MC100LVE210 Low–Voltage CMOS 16–Bit Buffer, 3–State, Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16240A Low–Voltage CMOS 16–Bit Buffer, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS Low–Voltage CMOS Octal Buffer, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs BOUNCE ELIMINATOR Hex Contact Bounce Eliminator DW BUFFERS – – MC100E210 14 DW P,L 28 FN – 20 DW,M, DT MC74LCX16244 – 20 DW,M, DT CMOS MC74LCX244 – 20 DW,M, DT Low–Voltage CMOS Octal Buffer, 3–State, Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX240 – 20 DW,M, DT Low–Voltage CMOS Octal Buffer Flow Through Pinout, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX541 – 20 DW,M, DT Low–Voltage CMOS Octal Buffer Flow Through Pinout, 3–State, Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX540 – 20 DW,M, DT Low–Voltage CMOS Quad Buffer, 3–State, Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX125 – 20 DW,M, DT Low–Voltage Quiet CMOS Octal Buffer CMOS MC74LVQ541 – 20 D,M, SD,DT Low–Voltage Quiet CMOS Octal Buffer, 3–State, Non–Inverting CMOS MC74LVQ244 – 20 DW,M, SD,DT BUFFERS, 3–STATE Motorola Master Selection Guide 3.1–9 Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM BUFFERS, 3–STATE Low–Voltage Quiet CMOS Octal Buffer, 3–State, Inverting CMOS MC74LVQ240 – 20 DW,M, SD,DT Low–Voltage Quiet CMOS Quad Buffer, 3–State, Non–Inverting CMOS MC74LVQ125 – 14 D,M, SD,DT 10–Bit Buffer/Line Driver (Inverting), With 3–State Outputs TTL MC74F828 – 24 N DW 10–Bit Buffer/Line Driver (Non–Inverting), With 3–State Outputs TTL MC74F827 – 24 N DW 3–Bit Registered Bus Transceiver, 25Ω Cutoff Outputs ECL MC10E336 MC100E336 28 FN 3–Bit Scannable Registered Bus Transceiver ECL MC10E337 MC100E337 28 FN 32–Bit to 32/16/8–Bit Dynamic READ/WRITE Bus Sizer CMOS MC68150*33 – 68 FN CMOS MC68150*40 – 68 FN 9–Bit Bus Interface, NINV, 3 State Outputs TTL MC74F823 – 24 N DW Dual Bus Driver/Receiver With 4–to–1 Output Multiplexer (25Ω) ECL MC10H332 – 20 P,L FN Hex 3–State Inverting Buffer With Common Enables CMOS MC54HC366 16 N,J Hex 3–State Inverting Buffer With Separate 2–Bit and 4–Bit Sections CMOS MC74HC368 16 N Hex 3–State Non–Inverting Buffer With Common Enables CMOS MC54HC365 MC74HC365 16 N,J Hex 3–State Non–Inverting Buffer With Separate 2–Bit and 4–Bit Sections CMOS MC54HC367 MC74HC367 16 N,J Hex Buffer 4/2–Bit/Inverting With 3–State Outputs TTL SN54LS368A SN74LS368A 16 N,J D Hex Buffer 4/2–Bit/Non–Inverting With 3–State Outputs TTL SN54LS367A SN74LS367A 16 N,J D Hex Buffer Driver, 4+2–Bit, Inverting, With 3–State Outputs TTL MC74F368 16 N D Hex Buffer Gated Enable Inverting With 3–State Outputs TTL SN54LS366A SN74LS366A 16 N,J D Hex Buffer Gated Enable Non–Inverting With 3–State Outputs TTL SN54LS365A SN74LS365A 16 N,J D Hex Buffer/Driver Gated Enable Inverting, With 3–State Outputs TTL MC74F366 – 16 N D Hex Buffer/Driver Gated Enable Non–Inverting, With 3–State Outputs TTL MC74F365 – 16 N D Hex Buffer/Driver, 4+2–Bit, Non–Inverting, With 3–State Outputs TTL MC74F367 – 16 N D Hex With 3–State Outputs Buffer (Non–Inverting) CMOS MC14503B – 16 P,L D Octal 3–State Non–Inverting Bus Transceiver With LSTTL Compatible Inputs CMOS MC54HCT245A MC74HCT245A 20 N,J DW, SD,DT Octal Bidirectional Transceiver With 3–State Inputs/Outputs CMOS MC74AC245 – 20 N DW CMOS MC74ACT245 – 20 N DW CMOS MC74AC620 – 20 N DW CMOS MC74ACT620 – 20 N DW CMOS MC74AC623 – 20 N DW CMOS MC74ACT623 – 20 N DW CMOS MC74AC640 – 20 N DW CMOS MC74ACT640 – 20 N DW CMOS MC74AC643 – 20 N DW CMOS MC74ACT643 – 20 N DW TTL MC74F245 – 20 N DW Octal Bidirectional Transceiver With 8–Bit Parity y Generator Checker With 3–State 3 State Outputs O tp ts Checker, TTL MC74F657A – 24 N DW TTL MC74F657B – 24 N DW Octal Bidirectional Transceiver, With 3–State Inputs/Outputs TTL MC74F1245 – 20 N DW (81LS95) TTL SN54LS795 SN74LS795 20 N,J DW (81LS96) TTL SN54LS796 SN74LS796 20 N,J DW (81LS97) TTL SN54LS797 SN74LS797 20 N,J DW (81LS98) TTL SN54LS798 SN74LS798 20 N,J DW BUS INTERFACE Octal Bidirectional Transceiver With 3–State Outputs Octal Buffer With 3–State Outputs Logic: Standard, Special and Programmable 3.1–10 MC74HC366 – – DT Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM BUS INTERFACE Octal Buffer/Line Driver With 3–State Outputs TTL SN54LS244 20 N,J DW TTL MC74F240 – 20 N DW TTL MC74F241 – 20 N DW TTL MC74F244 – 20 N DW TTL SN54LS240 SN74LS240 20 N,J DW TTL SN54LS241 SN74LS241 20 N,J DW TTL SN54LS540 SN74LS540 20 N,J DW TTL SN54LS541 SN74LS541 20 N,J DW CMOS MC74AC241 – 20 N DW CMOS MC74AC244 – 20 N DW CMOS MC74ACT244 – 20 N DW CMOS MC74AC540 – 20 N DW CMOS MC74ACT540 – 20 N DW CMOS MC74AC541 – 20 N DW CMOS MC74ACT541 – 20 N DW CMOS MC74AC240 – 20 N DW CMOS MC74ACT240 – 20 N DW CMOS MC74ACT241 – 20 N DW TTL SN54LS245 SN74LS245 20 N,J DW TTL SN54LS623 SN74LS623 20 N,J DW Octal Bus Transceiver, With 3–State Outputs TTL MC74F623 20 N DW Octal Bus Transceiver/Inverting With 3–State Outputs TTL SN54LS640 20 N,J DW TTL MC74F620 – 20 N DW TTL MC74F640 – 20 N DW Octal Bus Transceiver/Non–Inverting With 3–State Outputs TTL SN54LS645 20 N,J DW Octal Bus Transceiver/Register With 3–State Outputs Non–Inverting CMOS MC74AC652 – 24 N DW Octal Bus Transceiver SN74LS244 – SN74LS640 SN74LS645 CMOS MC74ACT652 – 24 N DW Octal Registered Transceiver Inverting, With 3–State Outputs TTL MC74F544 – 24 N DW Octal Transceiver/Register With 3–State Outputs Non–Inverting CMOS MC74AC646 – 24 N DW CMOS MC74ACT646 – 24 N DW CMOS MC74AC648 – 24 N DW CMOS MC74ACT648 – 24 N DW Octal Transceiver/Register, With 3–State Outputs TTL MC74F646 – 24 N DW Octal With 3–State Non–Inverting Buffer/Line Driver/Line Receiver CMOS MC54HC241A MC74HC241A 20 N,J DW Octal With 3–State Non–Inverting g Buffer/Line Driver/Line Receiver With LSTTL Compatible Inputs CMOS MC54HCT241A MC74HCT241A 20 N,J DW CMOS MC54HCT244A MC74HCT244A 20 N,J DW, SD,DT Octal With 3–State Outputs Inverting Buffer/Line Driver/Line Receiver CMOS MC54HC240A MC74HC240A 20 N,J DW, DT MC74HC540A 20 N,J DW 20 N DW, SD,DT Octal Transceiver/Register With 3–State Outputs Inverting CMOS MC54HC540A Octal With 3–State Outputs Inverting Buffer/Line Driver/Line Receiver With LSTTL Compatible Inputs CMOS MC74HCT240A Octal With 3–State Outputs Inverting Bus Transceiver CMOS MC54HC640A MC74HC640A 20 N,J DW Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver CMOS MC54HC541A MC74HC541A 20 N,J DW CMOS MC74VHC541 – 20 CMOS MC74HCT541A – 20 Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver With LSTTL Compatible Inputs Motorola Master Selection Guide 3.1–11 – DW, DT,M N DW Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM 20 N,J DW, SD,DT BUS INTERFACE Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver CMOS MC54HC244A CMOS MC74VHC244 CMOS MC54HC245A CMOS MC74VHC245 Octal With 3–State Outputs Non–Inverting Bus Transceiver & D Flip–Flop CMOS MC54HC646 MC74HC646 24 N,J Quad Buffers With 3–State Outputs TTL SN54LS125A SN74LS125A 14 N,J D Quad 3–State Non–Inverting Buffers CMOS MC74HC125A – 14 N D,DT CMOS MC74VHC125 – 14 CMOS MC74HC126A – 14 N D,DT CMOS MC74AC125 – 14 N D CMOS MC74ACT125 – 14 N D CMOS MC74AC126 – 14 N D CMOS MC74ACT126 – 14 N D TTL MC74F125 – 14 N D TTL MC74F126 – 14 N D TTL SN54LS126A 14 N,J D Quad Bus Driver ECL MC10192 – 16 P,L FN Quad Bus Driver/Receiver With 2–to–1 Output Multiplexer (25Ω) ECL MC10H330 – 24 P,L FN Quad Bus Driver/Receiver With Transmit & Receiver Latches (25Ω) ECL MC10H334 – 20 P,L FN Quad Bus Transceiver/Inverting With 3–State Outputs TTL SN54LS242 SN74LS242 14 N,J D Quad Bus Transceiver/Non–Inverting With 3–State Outputs TTL SN54LS243 SN74LS243 14 N,J D Quad Bus Transceivers With 3–State Outputs TTL MC74F242 – 14 N D TTL MC74F243 – 14 N D Quad With 3–State Outputs Inverting Bus Transceiver CMOS MC74HC242 – 14 N Triple 3–Input Bus Driver With Enable (25Ω) ECL MC10H423 – 16 P,L FN Triple 4–3–3 Input Bus Driver (25Ω) ECL MC10H123 – 16 P,L FN ECL MC10123 – 16 P,L FN SXLG MC68194 – 52 1:4 Clock Distribution Chip ECL MC10EL15 MC100EL15 16 D 1:5 Clock Distribution Chip ECL MC100LVEL14 MC100EL14 20 DW 1:6 Differential Clock Distribution Chip ECL MC10E211 MC100E211 28 FN Low Voltage 1:12 Clock Distribution Chip SXLG MPC948 – 32 FA FA Octal With 3–State Outputs Non–Inverting Bus Transceiver Quad Buffer With 3–State Outputs MC74HC244A – MC74HC245A – SN74LS126A 20 20 DW, DT,M N,J 20 DW DW DT,M DW D, DT,M CBM CBM – Carrier Band Modem *FJ CLOCK DISTRIBUTION CHIPS SXLG MPC948L – 32 Low Voltage 1:9 Clock Distribution Chip SXLG MPC947 – 32 FA Low Voltage 1:9 ECL/PECL Clock Distribution Chip ECL MC100LVE111 – 28 FN 1:2 Differential Clock Driver ECL MC10EL11 8 D 1:6 PCI Clock Generator/Fanout Buffer CMOS MPC903 – 16 D CMOS MPC904 – 16 D CMOS MPC905 – 16 D ECL MC10E111 28 FN CLOCK DRIVERS 1:9 Differential Clock Driver With Low Skew, Enable, Vbb Logic: Standard, Special and Programmable 3.1–12 MC100EL11 MC100E111 Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM CLOCK DRIVERS 1:9 Differential ECL/PECL RAMBus Clock Buffer ECL MC10E411 – 28 FN 1:9 TTL/TTL Clock Distribution Chip ECL MC10H645 – 28 FN 3.3/5.0V Fully Integrated PLL Clock Driver CMOS MPC974 – 52 FA 50 MHz Low Skew CMOS PLL Clock Driver With µP Power Down CMOS MC88920 – 20 DW 66 MHz Low Skew CMOS PLL Clock Driver With µP Power–Down/Power–Up Feature CMOS MC88921 – 20 DW 68030/040 PECL/TTL Clock Driver ECL MC10H640 MC100H640 28 FN ECL MC10H642 MC100H642 28 FN ECL MC10H644 MC100H644 20 TTL MC74F1803 – 14 N N Clock Driver Quad D–Type Flip–Flop w/ Matched Propagation Delays FN D TTL MC74F803 – 14 CMOS PLL Clock Driver Programmable Frequency, Low Skew, High Fan–Out CMOS MC88PL117 – 52 Dual 3.3V PLL Clock Generator CMOS MPC980 – 52 FA Dual Supply ECL/TTL 1:8 Clock Driver ECL MC10H643 28 FN High Frequency PLL Clock Generator ECL MC12429 – 28 FN ECL MC12430 – 28 FN ECL MC12439 – 28 Low Skew CMOS Clock Driver CMOS MC88913 – 14 N D Low Skew CMOS Clock Driver With Reset CMOS MC88914 – 14 N D Low Skew CMOS PLL 68060 Clock Driver CMOS MC88LV926 – 20 DW Low Skew CMOS PLL Clock Driver CMOS MC88915*55 – 28 FN CMOS MC88915*70 – 28 FN CMOS MC88916*70 – 20 DW CMOS MC88916*80 – 20 DW CMOS MC88915T*160 – 28 FN 133 MHz Version CMOS MC88915T*133 – 28 FN 100 MHz Version CMOS MC88915T*100 – 28 FN 70 MHz Version CMOS MC88915T*70 – 28 FN 55 MHz Version CMOS Low Skew CMOS PLL Clock Driver With Processor Reset Low Skew CMOS PLL Clock Driver 160 MHz Version MC100H643 D FN FN MC88915T*55 – 28 FN Low Voltage 1:10 CMOS Clock Driver CMOS MPC946 – 32 FA Low Voltage 1:15 Differential ÷1/2 ECL/PECL Clock Driver ECL MC100LVE222 – 52 FA Low Voltage 1:15 PECL to CMOS Clock Driver CMOS MPC949 – 52 FA Low Voltage 1:9 Differential ECL/HSTL to HSTL Clock Driver CMOS MPC911 – 28 FN Low Voltage PECL PLL Clock Driver CMOS MPC992 – 32 FA Low Voltage PLL Clock Driver CMOS MPC930 MPC931 32 FA CMOS MPC950 MPC951 32 FA CMOS MPC956 – 32 FA CMOS MPC970 – 52 FA CMOS MPC972 MPC973 52 FA CMOS MPC990 MPC991 52 FA Low Voltage Wide Fanout PLL Clock Driver CMOS MPC952 – 32 FA PECL/TTL to TTL 1: 8 Clock Distribution Chip ECL MC10H646 MC100H646 28 FN Single Supply PECL/TTL 1:9 Clock Distribution Chip ECL MC10H641 MC100H641 28 FN ÷2, ÷4/6 Clock Generation Chip (3.3V) ECL MC100LVEL38 MC100EL38 20 DW ÷2/4, ÷4/6 Clock Generation Chip ECL MC100LVEL39 MC100EL39 20 DW ÷2,4,8 Differential Clock Driver ECL MC10EL34 MC100EL34 16 D Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit SDX MC10SX1189 – 16 D 300 MBit/s LED Driver for FDDI and Fibre Channel SDX MC10SX1130 – 16 D COAX CABLE DRIVERS Motorola Master Selection Guide 3.1–13 Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM COMPARATORS 4–Bit Magnitude Comparator TTL MC74F85 – 16 N D CMOS MC74HC85 – 16 N DT TTL SN54LS85 16 N,J D CMOS MC14585B – 16 P,L D ECL MC10H166 – 16 P,L FN ECL MC10166 – 16 P,L FN 8–Bit Equality Comparator CMOS MC54HC688 20 N,J DW 8–Bit Identity Comparator CMOS MC74ACT521 – 20 N TTL MC74F521 – 20 N DW TTL SN54LS682 SN74LS682 20 N,J DW TTL SN54LS684 SN74LS684 20 N,J DW TTL SN54LS688 SN74LS688 20 N,J DW 9–Bit Magnitude Comparator ECL MC10E166 MC100E166 Dual Analog Comparator With Latch ECL MC10E1651 – 16,20 L FN Dual Analog Comparator With Latch (Hi–Perf MC1651) ECL MC10E1652 – 16,20 L FN 4–Bit Parallel to Serial Converter ECL MC10E446 MC100E446 28 4–Bit Serial to Parallel Converter ECL MC10E445 MC100E445 28 Dual A/D Converter ECL MC1650 – 16 L ECL MC1651 – 16 L 12–Bit Binary Counter CMOS MC14040B – 16 P,L D 12–Stage Binary Ripple Counter CMOS MC54HC4040A MC74HC4040A 16 N,J D,DT CMOS MC74AC4040 – 16 N D 14–Bit Binary Counter CMOS MC14020B – 16 P,L D 14–Bit Binary Counter and Oscillator CMOS MC14060B – 16 P,L D 14–Stage Binary Ripple Counter CMOS MC74HC4020A – 16 N D,DT CMOS MC74AC4020 – 16 N D CMOS MC54HC4060 MC74HC4060 16 N,J DT CMOS MC54HC4060A MC74HC4060A 16 N,J D,DT 3–Digit BCD Counter CMOS MC14553B – 16 P DW 4–Bit BCD Decade Counter, Asynchronous Reset TTL SN54LS160A SN74LS160A 16 N,J D TTL SN54LS162A SN74LS162A 16 N,J D 4–Bit Bidirectional Binary Counter, With 3–State Outputs TTL MC74F569 – 20 N DW 4–Bit Bidirectional Decade Counter, With 3–State Outputs TTL MC74F568 – 20 N DW 4–Bit Binary Counter TTL SN54LS93 SN74LS93 14 N,J D TTL SN54LS293 SN74LS293 14 N,J D ECL MC10H16 – 16 P,L FN CMOS MC14161B – 16 P D CMOS MC14163B – 16 P D TTL SN54LS161A SN74LS161A 16 N,J D TTL SN54LS163A SN74LS163A 16 N,J D 4–Bit Up/Down Counter With 3–State Outputs TTL SN54LS569A SN74LS569A 20 N,J DW 4–Stage Presettable Ripple Counters TTL SN54LS196 SN74LS196 14 N,J D TTL SN54LS197 SN74LS197 14 N,J D TTL MC74F168 – 16 N D TTL MC74F169 – 16 N D 5 Cascaded BCD Counters CMOS MC14534B – 24 P,L DW 6–Bit Universal Counter, (Lookahead Carry) ECL MC10E136 7–Stage Ripple Counter CMOS MC14024B 5–Bit Magnitude Comparator 8–Bit Magnitude Comparator SN74LS85 MC74HC688 28 FN CONVERTERS FN FN COUNTERS 14–Stage Binary Ripple Counter With Oscillator 4–Bit Binary Counter, Synchronous Presettable 4–Bit Binary Counter, Synchronous Reset 4–Stage Synchronous Bidirectional Counter Logic: Standard, Special and Programmable 3.1–14 MC100E136 – 28 14 FN P,L D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM COUNTERS 8–Bit Bidirectional Binary Counter TTL MC74F269 – 24 N DW 8–Bit Bidirectional Binary Counter, With 3–State Outputs TTL MC74F579 – 20 N DW TTL MC74F779 – 16 N 8–Bit Ripple Counter ECL MC10E137 MC100E137 28 8–Bit Synchronous Binary Up Counter ECL MC10E016 MC100E016 28 BCD Decade Counter, Synchronous Presettable TTL MC74F160A – 16 N D TTL MC74F162A – 16 N D BCD Decade Synchronous Bidirectional Counter TTL SN54LS168 16 N,J D Bi–Quinary Counter ECL MC10138 – 16 P,L FN Binary Counter ECL MC10154 – 16 P,L ECL MC10178 – 16 P,L FN TTL MC74F161A – 16 N D D Binary Counter, Synchronous Presettable, 4–Bit SN74LS168 D FN FN TTL MC74F163A – 16 N Counter Control Logic ECL MC12014 – 16 P,L Decade Counter TTL SN54LS90 SN74LS90 14 N,J D TTL SN54LS290 SN74LS290 14 N,J D CMOS MC14017B – 16 P,L D CMOS MC74HC4017 – 16 N D Divide By 12 Counter TTL SN54LS92 SN74LS92 14 N,J D Dual 4–Stage Binary Counter TTL SN54LS393 SN74LS393 16 N,J D Dual 4–Stage Binary Ripple Counter CMOS MC54HC393 MC74HC393 14 N,J D Dual 4–Stage Binary Ripple Counter W ÷2, ÷5 Sections CMOS MC54HC390 MC74HC390 16 N,J D Dual BCD Up Counter CMOS MC14518B – 16 P,L DW Dual Binary Up Counter CMOS MC14520B – 16 P,L DW Dual Decade Counter TTL SN54LS390 SN74LS390 16 N,J D SN74LS490 16 N,J D 16 P D 16 N,J D D TTL SN54LS490 Industrial Time Base Generator CMOS MC14566B Modulo 16 Binary Synchronous Bidirectional Counter TTL SN54LS169 Octal Counter CMOS MC14022B – 16 P,L Phase Comparator and Programmable Counter CMOS MC14568B – 16 P,L D Presettable 4–Bit BCD Down Counter CMOS MC14522B – 16 P DW Presettable 4–Bit Binary Down Counter CMOS MC14526B – 16 P,L DW Presettable 4–Bit Binary Up/Down Counter TTL SN54LS191 SN74LS191 16 N,J D SN74LS193 16 N,J D 16 P D – SN74LS169 TTL SN54LS193 Presettable BCD Up/Down Counter CMOS MC14510B Presettable BCD/Decade Up/Down Counter TTL SN54LS190 SN74LS190 16 N,J D TTL SN54LS192 SN74LS192 16 N,J D Presettable Binary Up/Down Counter CMOS MC14516B – 16 P,L D Presettable Binary/BCD Up/Down Counter CMOS MC14029B – 16 P,L D Presettable Counter CMOS MC54HC160 MC74HC160 16 N,J D CMOS MC54HC161A MC74HC161A 16 N,J D CMOS MC54HCT161A MC74HCT161A 16 N,J D CMOS MC54HC162 MC74HC162 16 N,J D CMOS MC54HC163A MC74HC163 16 N,J D CMOS MC54HCT163A MC74HCT163A 16 N,J D Presettable Divide–by–N Counter CMOS MC14018B – 16 P D Programmable Dual Binary/BCD Counter CMOS MC14569B – 16 P,L DW Motorola Master Selection Guide 3.1–15 – Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM COUNTERS Programmable Modulo–N Counters (N=0–9) ECL MC4016 – 16 P,L ECL MC4018 – 16 P,L ECL MC4316 – 16 P,L Synchronous 4–Bit Up/Down Counter TTL SN54LS669 16 N,J D Synchronous Presettable Binary Counter CMOS MC74AC161 – 16 N D CMOS MC74ACT161 – 16 N D CMOS MC74AC163 – 16 N D CMOS MC74ACT163 – 16 N D CMOS MC74AC160 – 16 N D CMOS MC74ACT160 – 16 N D CMOS MC74AC162 – 16 N D CMOS MC74ACT162 – 16 N D Universal Decade Counter ECL MC10137 – 16 P,L Universal Hexadecimal Counter ECL MC10H136 – 16 P,L FN ECL MC10136 – 16 P,L FN CMOS MC74AC190 – 16 N D CMOS MC74HC42 – 16 N D TTL SN54LS42 SN74LS42 16 N,J D 1–of–10 Decoder/Driver Open–Collector TTL SN54LS145 SN74LS145 16 N,J D 1–of–10 Decoder, With 3–State Outputs TTL MC74F537 20 N DW 1–of–16 Decoder/Demultiplexer CMOS MC54HC154 24 N,J DW 1–of–16 Decoder/Demultiplexer With Address Latch CMOS MC74HC4514 – 24 N DW 1–of–4 Decoder, With 3–State Outputs TTL MC74F539 – 20 N DW 1–of–8 Decoder, With 3–State Outputs TTL MC74F538 – 20 N DW 1–of–8 Decoder/Demultiplexer CMOS MC74AC138 – 16 N D CMOS MC74ACT138 – 16 N D TTL MC74F138 – 16 N D CMOS MC54HC138A 16 N,J CMOS MC74VHC138 – 16 CMOS MC74HCT138A – 16 N D,DT TTL SN54LS138 16 N,J D CMOS MC74HC137 – 16 N D CMOS MC74HC237 – 16 N D 3–Line to 8–Line Decoders/Demultiplexers With Address Latches TTL SN54LS137 16 N,J D 4–Bit Transparent Latch/4–to–16 Line Decoder (High) CMOS MC14514B – 24 P,L DW 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) CMOS MC14515B – 24 P,L DW 8–Bit Addressable Latch/1–of–8 Decoder CMOS MC54HC259 16 N,J D BCD–to–Decimal Decoder/Binary–to–Octal Decoder CMOS MC14028B – 16 P,L D Binary to 1–4 Decoder (Low) ECL MC10171 – 16 P,L FN Binary to 1–8 Decoder, (High) ECL MC10H162 – 16 P,L FN ECL MC10162 – 16 P,L FN ECL MC10H161 – 16 P,L FN – Synchronous Presettable Binary Counter Synchronous Presettable Binary–Coded–Decimal Decade Counter Up/Down Counter With Preset and Ripple Clock SN74LS669 DECODER/DEMULTIPLEXERS 1–of–10 Decoder 1–of–8 Decoder/Demultiplexer With Address Latch Binary to 1–8 Decoder, (Low) – MC74HC154 MC74HC138A SN74LS138 SN74LS137 MC74HC259 D D,DT, M ECL MC10161 16 P,L FN Dual 1–of–4 Decoder TTL SN54LS155 SN74LS155 16 N,J D Dual 1–of–4 Decoder Open–Collector TTL SN54LS156 SN74LS156 16 N,J D Logic: Standard, Special and Programmable 3.1–16 Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM DECODER/DEMULTIPLEXERS Dual 1–of–4 Decoder/Demultiplexer Dual 1–of–4 Decoder/Demultiplexer Dual Binary to 1–4 Decoder (High) CMOS MC74AC139 – 16 N D CMOS MC74ACT139 – 16 N D TTL MC74F139 – 16 N D CMOS MC54HC139A MC74HC139A 16 N,J D TTL SN54LS139 SN74LS139 16 N,J D ECL MC10H172 – 16 P,L FN ECL MC10172 – 16 P,L FN Dual Binary to 1–4 Decoder (Low) ECL MC10H171 – 16 P,L FN Dual Binary to 1–of–4 Decoder (Active High Outputs) CMOS MC14555B – 16 P D Dual Binary to 1–of–4 Decoder (Active Low Outputs) CMOS MC14556B – 16 P Low–Voltage CMOS 1–of–8 Decoder/Demultiplexer With 5V Tolerant Inputs and Outputs CMOS MC74LCX138 – 16 D,DT Low–Voltage Quiet CMOS 1–of–8 Decoder/Demultiplexer CMOS MC74LVQ138 – 16 D,M, SD,DT Analog Mixer ECL MC12002 – 14 P,L Phase–Frequency Detector ECL MC4044 – 14 P,L ECL MC4344 – 14 P,L ECL MC12040 – 14 P,L ECL MCH12140 MCK12140 8 TTL SN54LS48 SN74LS48 16 CMOS MC14558B TTL SN54LS47 SN74LS47 TTL SN54LS247 TTL D DETECTORS D FN D DISPLAY DECODE DRIVERS BCD–to–Seven Segment Decoder BCD–to–Seven Segment Decoder/Driver N,J D 16 P,L D 16 N,J D SN74LS247 16 N,J D SN54LS248 SN74LS248 16 N,J D SN74LS249 D – TTL SN54LS249 16 N,J BCD–to–Seven Segment Latch/Decoder/Display Driver CMOS MC74HC4511 – 16 N D BCD–to–Seven Segment Latch/Decoder/Driver CMOS MC14511B – 16 P,L D,DW BCD–to–Seven Segment Latch/Decoder/Driver for Liquid Crystals CMOS MC14543B – 16 P,L D BCD–to–Seven Segment g Latch/Decoder/Driver With Ripple pp Blanking CMOS MC14544B – 18 P,L CMOS MC14513B – 18 P High Current BCD–to–Seven Segment Decoder/Driver CMOS MC14547B – 16 P,L ECL MC10EL32 ECL MC100LVEL32 ECL MC10EL33 ECL MC100LVEL33 – Coaxial Cable Driver ECL MC10EL89 300MBit/s LED Driver for FDDI and Fibre Channel ECL MC10SX1130 Error Detection–Correction Circuit (IBM Code) ECL Error Detection–Correction Circuit (Motorola Code) ECL 10–Line to 4–Line Priority Encoder TTL SN54LS147 8–Bit Priority Encoder CMOS MC14532B DW DIVIDERS ÷ 2 Divider ÷ 4 Divider MC100EL32 8 D 8 D 8 D 8 D – 8 D – 16 D MC10163 – 16 P,L MC10193 – 16 P,L 16 N,J D 16 P,L D – MC100EL33 DRIVER EDACs ENCODERS Motorola Master Selection Guide 3.1–17 SN74LS147 – Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM ENCODERS 8–Input Priority Encoder TTL SN54LS348 ECL MC10H165 SN74LS348 16 N,J D – 16 P,L FN – 16 P,L FN 16 N,J D ECL MC10165 8–Input Priority Encoder (Glitchless) TTL SN54LS848 8–Line to 3–Line Priority Encoder TTL MC74F148 16 N D TTL SN54LS148 SN74LS148 16 N,J D TTL SN54LS748 SN74LS748 16 N,J D CMOS MC74HC147 – 16 N D ECL MC100SX1230 – 28 Dual 4–Iput Expander HTL MC669 – 14 P,L Expandable Dual 4–Input Gate (Active Pullup) HTL MC660 – 14 P,L Expandable Dual 4–Input Gate (Passive Pullup) HTL MC661 – 14 P,L Expandable Dual 4–Input Line Driver HTL MC662 – 14 P,L Expandable Dual Power Gate DTL MC844 – 14 P,L DTL MC944 – 14 P,L 14,200–Gate Programmable Array With Up to 160 User I/Os CMOS MPA1064 – 160, 224 22,000–Gate Programmable Array With Up to 200 User I/Os CMOS MPA1100 – 229 HV 3,500–Gate Programmable Array With Up to 80 User I/Os CMOS MPA1016 – 84, 128 FN, DD 8,000–Gate Programmable Array With Up to 120 User I/Os CMOS MPA1036 – 84, 128, 160, 181 FN, DD, DH, HI 3–Bit Differential Flip–Flop ECL MC10E431 MC100E431 28 FN 4–Bit D Flip–Flop Individual Clock, Reset Differential Output ECL MC10E131 MC100E131 28 4–Bit D Flip–Flop With Enable TTL SN54LS379 SN74LS379 16 N,J D 4–Bit D–Type Register With With 3–State Outputs TTL SN54LS173A SN74LS173A 16 N,J D 5–Bit Differential Register ECL MC10E452 MC100E452 28 FN 6–Bit 2:1 Mux–Register With Common Clock, Asynchronous Master Reset Single Ended ECL MC10E167 MC100E167 28 FN 6–Bit D Register With Common Clock, Asynchronous Master Reset, Differential Outputs ECL MC10E151 MC100E151 28 FN 6–Bit D Register, With Differential Inputs, (Data & Clock) , VBB, Common Reset ECL MC10E451 MC100E451 28 FN 6–Bit Parallel D Register With Enable CMOS MC74AC378 – 16 N D CMOS MC74ACT378 – 16 N D 9–Bit Hold Register, 700MHz, With Asynchronous Master Reset ECL MC10E143 Clocked Flip–Flop DTL MC845 Clocked Flip–Flop DTL MC945 D Flip–Flop With Set & Reset ECL MC10EL31 MC100EL31 8 D Differential Clock D Flip–Flop ECL MC10EL51 MC100EL51 8 D ECL MC100LVEL51 8 D Differential Data & Clock D Flip–Flop ECL MC10EL52 Dual D Flip–Flop CMOS MC74AC74 – 14 CMOS MC74ACT74 – CMOS MC14013B – Decimal–to–BCD Encoder SN74LS848 – ENCODER/DECODERS CMI Encoder/Decoder FN EXPANDERS FIELD PROGRAMMABLE GATE ARRAY DH, KE FLIP–FLOPS Logic: Standard, Special and Programmable 3.1–18 MC100E143 FN 28 FN – 14 P,L – 14 P,L – MC100EL52 8 D N D 14 N D 14 P,L D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM 14 N,J D,DT FLIP–FLOPS Dual D Flip–Flop With Set and Reset CMOS MC54HC74A CMOS MC74VHC74 MC74HC74A – 14 Dual D Flip–Flop With Set and Reset With LSTTL Compatible Inputs CMOS MC74HCT74A – 14 Dual D–Type Positive Edge–Triggered Flip–Flop TTL MC74F74 – TTL SN54LS74A SN74LS74A Dual Differential Data and Clock D Flip–Flop With Set and Reset ECL MC100LVEL29 MC100EL29 20 Dual J–K Negative Edge–Triggered Flip–Flop TTL SN54LS112A SN74LS112A 16 N,J D TTL SN54LS113A SN74LS113A 14 N,J D TTL SN54LS114A SN74LS114A 14 N,J D Dual J–K Positive Edge–Triggered Flip–Flop TTL SN54LS109A SN74LS109A 16 N,J D Dual J–K Flip–Flop HTL MC663 14 P,L – N D 14 N D 16 N,J D DW TTL SN54LS107A 14 N,J Dual J–K Flip–Flop (Common Clock and CD Separate SD) DTL MC952 – 14 P,L Dual J–K Flip–Flop (Separate Clock and SD, No CD) DTL MC953 – 14 P,L Dual J–K Flip–Flop Negative Edge Trigger CMOS MC74AC112 – 16 N D CMOS MC74ACT112 – 16 N D CMOS MC74AC113 – 14 N D CMOS MC74ACT113 – 14 N D Dual J–K Flip–Flop With Set and Clear TTL SN54LS76A 16 N,J D Dual J–K Flip–Flop With Set and Reset CMOS MC74HC112 – 16 N D,DT Dual J–K Flip–Flop CMOS MC14027B – 16 P,L D Dual J–K Flip–Flop With Reset CMOS MC74HC73 – 14 N D CMOS MC74HC107 – 14 N D Dual J–K Flip–Flop With Set and Reset CMOS MC74HC76 – 16 N D Dual J–K Master–Slave Flip–Flop ECL MC10135 – 16 P,L FN ECL MC10H135 – 16 P,L FN TTL MC74F112 – 16 N D TTL SN54LS73A 14 N,J D CMOS MC74AC109 – 16 N D CMOS MC74ACT109 – 16 N D Dual J–K Flip–Flop With Set and Reset CMOS MC74HC109 – 16 N D Dual J–K Positive Edge–Triggered Flip–Flop TTL MC74F109 – 16 N D Dual Type–D Master–Slave Flip–Flop ECL MC10131 – 16 P,L FN ECL MC10H131 – 16 P,L FN TTL SN54LS174 16 N,J D CMOS MC14174B 16 P,L D Hex D Flip–Flop With Enable TTL SN54LS378 16 N,J D Hex D Flip–Flop With Master Reset CMOS MC74AC174 – 16 N D TTL MC74F174 – 16 N D CMOS MC74ACT174 – 16 N D CMOS MC54HC174A 16 N,J D CMOS MC74HCT174A – 16 N D ECL MC10H176 – 16 P,L FN ECL MC10176 – 16 P,L FN ECL MC10H186 – 16 P,L FN ECL MC10186 – 16 P,L FN High Speed Dual D Master–Slave Flip–Flop ECL MC10231 – 16 P,L FN J–K Flip–Flop ECL MC10EL35 Dual J–K Flip–Flop Negative Edge Trigger Dual J–K Negative Edge–Triggered Flip–Flop Dual J–K Positive Edge–Triggered Flip–Flop With Set & Clear Hex D Flip–Flop Hex D Flip–Flop With Common Clock & Reset Hex D Master–Slave Flip–Flop Hex D Master–Slave Flip–Flop With Reset Motorola Master Selection Guide 3.1–19 SN74LS107A D, DT,M SN74LS76A SN74LS73A SN74LS174 – SN74LS378 MC74HC174A MC100EL35 8 D D Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM FLIP–FLOPS Low–Voltage CMOS Octal D–Type Flip–Flop With Set and Reset, 3–State, Non–Inverting With 5V Tolerant Inputs CMOS MC74LCX74 – 14 D,DT Low–Voltage CMOS 16–Bit D–Type Flip–Flop, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16374 – 20 DW,M, DT Low–Voltage CMOS Octal D–Type Flip–Flop, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX374 – 20 DW,M, DT Low–Voltage CMOS Octal D–Type Flip–Flop Flow Through Pinout, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX574 – 20 DW,M, DT Low Voltage D Flip–Flop With Set & Reset ECL MC100LVEL31 – 8 D Low–Voltage Quiet CMOS Octal D–Type Flip–Flop CMOS MC74LVQ374 – 20 DW,M, SD,DT Low–Voltage Quiet CMOS Octal D–Type Flip–Flop Flow Through Pinout CMOS MC74LVQ574 – 20 DW,M, SD,DT Master–Slave Flip–Flop ECL MC1670 – 16 Master–Slave R–S Flip–Flop HTL MC664 – 14 P,L Octal 3–State Inverting D Flip–Flop CMOS MC54HC534A MC74HC534A 20 N,J DW Octal 3–State Non–Inverting D Flip–Flop With LSTTL Compatible Inputs CMOS MC54HCT374A MC74HCT374A 20 N,J DW, SD,DT Octal D Flip Flop, With 3–State Outputs TTL MC74F374 – 20 N DW Octal D Flip–Flop CMOS MC74AC273 – 20 N DW CMOS MC74ACT273 – 20 N DW Octal D Flip–Flop With 3–State Outputs/Broadside Pinout, F374 TTL MC74F574 – 20 N DW Octal D Flip–Flop With Clear TTL SN54LS273 20 N,J DW Octal D Flip–Flop With Clock Enable CMOS MC74AC377 – 20 N DW CMOS MC74ACT377 – 20 N DW Octal D Flip–Flop With Common Clock & Reset CMOS MC54HC273A 20 N,J DW, DT Octal D Flip–Flop With Common Clock and Reset With LSTTL Compatible Inputs CMOS MC74HCT273A – 20 N DW Octal D Flip–Flop With Enable TTL MC74F377 – 20 N DW Octal D Flip–Flop With Enable/ Non–Inverting TTL SN54LS377 20 N,J DW Octal D Type Flip–Flop With 3–State Outputs CMOS MC74AC374 – 20 N DW CMOS MC74ACT374 – 20 N DW TTL MC74F534 – 20 N DW TTL SN54LS374 20 N,J DW CMOS MC74AC534 – 20 N DW CMOS MC74ACT534 – 20 N DW CMOS MC74AC564 – 20 N DW CMOS MC74ACT564 – 20 N DW CMOS MC74AC574 – 20 N DW DW Octal D–Type Latch With 3–State Outputs SN74LS273 MC74HC273A SN74LS377 SN74LS374 L CMOS MC74ACT574 – 20 N Octal With 3–State Outputs Inverting D Flip–Flop CMOS MC74HC564A – 20 N DW Octal With 3–State Outputs Non–Inverting D Flip–Flop CMOS MC54HC374A 20 N,J DW, SD,DT CMOS MC74VHC374 CMOS MC54HC574A CMOS MC74VHC574 Octal With 3–State Outputs Non–Inverting D Flip–Flop With LSTTL Compatible Inputs CMOS MC54HCT574A Quad D Flip–Flop CMOS CMOS TTL Logic: Standard, Special and Programmable 3.1–20 MC74HC374A – MC74HC574A 20 20 DW, DT,M N,J DW – 20 DW, DT,M MC74HCT574A 20 N,J DW MC74AC175 – 16 N D MC74ACT175 – 16 N D MC74F175 – 16 N D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM 16 N,J D 16 P,L D FLIP–FLOPS Quad D Flip–Flop TTL SN54LS175 CMOS MC14175B CMOS MC54HC175 MC74HC175 16 N,J D CMOS MC54HC175A MC74HC175A 16 N,J D,SD Quad D–Type Register With 3–State Outputs CMOS MC14076B – 16 P,L D Quad Parallel Register With Enable TTL MC74F379 – 16 N D Quad With 3–State Outputs D Flip–Flop With Common Clock & Reset CMOS MC74HC173 – 16 N D Triple D Flip–Flop With Set and Reset ECL MC100LVEL30 CMOS MC74HC133 TTL SN54LS133 CMOS MC74HC30 TTL SN54LS30 CMOS MC14068B TTL MC74F21 TTL SN54LS21 CMOS MC14082B TTL MC74F40 TTL SN54LS40 CMOS MC74AC20 – CMOS MC74ACT20 TTL MC74F20 CMOS MC74HC20 TTL SN54LS20 SN74LS20 TTL SN54LS22 SN74LS22 CMOS MC14012B Dual 4–Input NAND Gate (Unbuffered) CMOS Expandable NAND Gate Hex AND Gate Quad D Flip–Flop With Common Clock & Reset SN74LS175 – MC100EL30 20 DW GATES, AND/NAND 13–Input NAND Gate 16 N D 16 N,J D 14 N D 14 N,J D – 14 P D – 14 N D 14 N,J D – 14 P,L D – 14 N D 14 N,J D 14 N D – 14 N D – 14 N D – 14 N D 14 N,J D 14 N,J D – 14 P,L D MC14012UB – 14 P,L D DTL MC830 – 14 P,L ECL MC10197 – 16 P,L Low–Voltage CMOS Quad 2–Input AND Gate, 5V–Tolerant Inputs CMOS MC74LCX08 – 14 D,DT Low–Voltage CMOS Quad 2–Input NAND Gate, 5V–Tolerant Inputs CMOS MC74LCX00 – 14 D,DT Low–Voltage Quiet CMOS Quad 2–Input NAND Gate CMOS MC74LVQ00 – 14 D,M, DT,SD Quad 2–Input AND Gate CMOS MC74AC08 – 14 N D CMOS MC74ACT08 – 14 N D TTL MC74F08 – 14 N D CMOS MC54HC08A 14 N,J D,DT CMOS MC74VHC08 TTL SN54LS08 SN74LS08 14 N,J TTL SN54LS09 SN74LS09 14 N,J D ECL MC10H104 – 16 P,L FN ECL MC10104 – 16 P,L FN – 14 P,L D 14 N,J D 14 N D 8–Input NAND Gate Dual 4–Input AND Gate Dual 4–Input NAND Buffer Dual 4–Input NAND Gate – SN74LS133 – SN74LS30 SN74LS21 SN74LS40 MC74HC08A – 14 FN D, DT,M D CMOS MC14081B Quad 2–Input AND Gate With LSTTL–Compatible Inputs CMOS MC54HCT08A Quad 2–Input NAND Buffer TTL MC74F37 TTL SN54LS26 SN74LS26 14 N,J D TTL SN54LS37 SN74LS37 14 N,J D Motorola Master Selection Guide 3.1–21 MC74HCT08A – Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM 14 N D 14 N,J D GATES, AND/NAND Quad 2–Input NAND Buffer Open–Collector TTL MC74F38 Quad 2–Input NAND Buffer Open–Collector TTL SN54LS38 Quad 2–Input NAND Gate DTL MC846 – 14 P,L DTL MC946 – 14 P,L CMOS MC74AC00 – 14 N D CMOS MC74ACT00 – 14 N D TTL MC74F00 – 14 N D CMOS MC54HC00A 14 N,J D,DT CMOS MC74VHC00 TTL SN54LS00 SN74LS00 14 N,J D TTL SN54LS01 SN74LS01 14 N,J D TTL SN54LS03 SN74LS03 14 N,J D CMOS MC14011B – 14 P,L D Quad 2–Input NAND Gate (Unbuffered) CMOS MC14011UB – 14 P,L D Quad 2–Input NAND Gate With LSTTL–Compatible Inputs CMOS MC54HCT00A 14 N,J D Quad 2–Input NAND Gate With Open–Drain Outputs CMOS MC74HC03A – 14 N D,DT Triple 3–Input AND Gate CMOS MC74AC11 – 14 N D CMOS MC74ACT11 – 14 N D TTL MC74F11 – 14 N D CMOS MC74HC11 – 14 N D TTL SN54LS11 SN74LS11 14 N,J D TTL SN54LS15 SN74LS15 14 N,J D CMOS MC14073B – 14 P,L D CMOS MC74AC10 – 14 N D CMOS MC74ACT10 – 14 N D TTL MC74F10 – 14 N D CMOS MC74HC10 – 14 N D TTL SN54LS10 SN74LS10 14 N,J D TTL SN54LS12 SN74LS12 14 N,J D CMOS MC14023B – 14 P,L D CMOS MC14023UB – 14 P,L D 2–Input AND/NAND Gate ECL MC10EL04 MC100EL04 8 D 2–Input Differential AND/NAND Gate ECL MC10EL05 MC100EL05 8 D ECL MC100LVEL05 8 D 2–Input XOR/NOR Gate ECL MC10EL07 2–Wide, 2–Input/2–Wide, 3–Input AND–NOR Gate CMOS MC74HC51 – 14 N D 2–Wide, 2–Input/2–Wide, 3–Input AND–OR Gate CMOS MC74HC58 – 14 N D 2–Wide, 4–Input AND/OR Invert Gate TTL SN54LS55 SN74LS55 14 N,J D 3–2–2–3–Input AND/OR Invert Gate TTL SN54LS54 SN74LS54 14 N,J D 4–2–3–2 Input AND–OR–Invert Gate TTL MC74F64 – 14 N D 4–Bit AND/OR Selector CMOS MC14519B – 16 P D 4–Input OR/NOR Gate ECL MC10EL01 Triple 3–Input NAND Gate Triple 3–Input NAND Gate (Unbuffered) – SN74LS38 MC74HC00A – MC74HCT00A 14 D, DT,M GATES, COMPLEX – MC100EL07 MC100EL01 8 D 8 D ECL MC100LVEL01 – 8 4–Wide 4–3–3–3 Input OR–AND Gate ECL MC10H119 – 16 P,L FN 4–Wide OR–AND/OR–AND–Invert Gate ECL MC10H121 – 16 P,L FN 4–Wide OR–AND/OR–AND–Invert Gate ECL MC10121 – 16 P,L FN Logic: Standard, Special and Programmable 3.1–22 D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM 14 N D 14 N,J D GATES, COMPLEX 8–Input NOR/OR Gate CMOS MC74HC4078 Dual 2 Wide 2–Input/3–Input AND/OR Invert Gate TTL SN54LS51 – Dual 2–Wide 2–3–Input OR–AND/OR–AND–Invert Gate ECL MC10117 – 16 P,L FN ECL MC10H117 – 16 P,L FN Dual 2–Wide 2–Input, 2–Wide 3–Input AND–OR–Invert Gate TTL MC74F51 – 14 N D Dual 2–Wide 3–Input OR–AND Gate ECL MC10H118 – 16 P,L FN Dual 4–5 Input OR/NOR Gate ECL MC10H109 – 16 P,L FN ECL MC10109 – 16 P,L FN SN74LS51 ECL MC10H209 – 16 P,L FN Dual 4–Input NAND, 2–Input NOR/OR, 8–Input AND/NAND Gate (Unbuffered) CMOS MC14501UB – 16 P D Dual 4–Input OR/NOR Gate ECL MC1660 – 16 L Dual 5–Input Majority Logic Gate CMOS MC14530B – 16 P Dual Expandable AND OR Invert Gate (Unbuffered) CMOS MC14506UB – 16 L Hex NAND/NOR/Invert Gate (Unbuffered) CMOS MC14572UB – 16 P High Speed Dual 3–Input 3–Output OR/NOR Gate ECL MC10212 – 16 P Quad 4–Input OR/NOR Gate ECL MC10E101 MC100E101 28 Quad Differential AND/NAND Gate ECL MC10E404 MC100E404 28 Quad OR/NOR Gate ECL MC10H101 – 16 P,L FN ECL MC10101 – 16 P,L FN Quint 2–Input AND/NAND Gate ECL MC10E104 MC100E104 28 Quint 2–Input XOR/XNOR Gate ECL MC10E107 MC100E107 28 Triple 2–3–2 Input OR/NOR Gate ECL MC10H105 – 16 P,L FN ECL MC10105 – 16 P,L FN ECL MC10H107 – 16 P,L FN ECL MC10107 – 16 P,L FN Low–Voltage CMOS Quad 2–Input Exclusive OR Gate With 5V Tolerant Inputs CMOS MC74LCX86 – 14 Quad 2–Input Exclusive NOR Gate CMOS MC74AC810 – 14 N DW CMOS MC74ACT810 – 14 N DW CMOS MC74HC7266 – 14 N D CMOS MC74HC7266A – 14 N D,DT TTL SN54LS266 14 N,J D Quad Exclusive NOR Gate CMOS MC14077B – 14 P,L D Quad 2–Input Exclusive OR Gate CMOS MC74AC86 – 14 N D CMOS MC74ACT86 – 14 N D TTL MC74F86 – 14 N D CMOS MC54HC86 MC74HC86 14 N,J D CMOS MC54HC86A MC74HC86A 14 N,J D,DT TTL SN74LS136 14 N,J D TTL SN54LS386 SN74LS386 14 N,J D TTL SN54LS86 SN74LS86 14 N,J D ECL MC10H113 – 16 P,L FN ECL MC10113 – 16 P,L FN CMOS MC14070B – 14 P,L D ECL MC1672 – 16 L Triple 2–Input Exclusive OR/Exclusive NOR Gate D D FN FN FN FN GATES, EXCLUSIVE OR/EXCLUSIVE NOR Quad Exclusive OR Gate Triple 2–Input Exclusive–OR Gate Motorola Master Selection Guide 3.1–23 SN74LS266 – D,M SD,DT Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM GATES, NOR 8–Input NOR Gate CMOS MC14078B – 14 P D Dual 3–Input 3–Output NOR Gate ECL MC10111 – 16 P,L FN ECL MC10H211 – 16 P,L FN ECL MC10211 – 16 P,L FN CMOS MC74HC4002 – 14 N D CMOS MC14002B – 14 P,L D Dual 4–Input NOR Gate (Unbuffered) CMOS MC14002UB – 14 P,L D Dual 5–Input NOR Gate TTL SN54LS260 14 N,J D Low–Voltage CMOS Quad 2–Input NOR Gate, 5V–Tolerant Inputs CMOS MC74LCX02 Quad 2–Input NOR Buffer TTL SN54LS28 SN74LS28 14 N,J D TTL SN54LS33 SN74LS33 14 N,J D CMOS MC74AC02 – 14 N D CMOS MC74ACT02 – 14 N D TTL MC74F02 – 14 N D CMOS MC54HC02A 14 N,J D,DT CMOS MC74VHC02 TTL SN54LS02 14 N,J D ECL MC10H102 – 16 P,L FN ECL MC10102 – 16 P,L FN ECL MC1662 – 16 L Dual 4–Input NOR Gate Quad 2–Input NOR Gate SN74LS260 – MC74HC02A – SN74LS02 14 D,DT 14 D, DT,M CMOS MC14001B – 14 P,L Quad 2–Input NOR Gate (Unbuffered) CMOS MC14001UB – 14 P,L D D Quad 2–Input NOR Gate With strobe ECL MC10H100 – 16 P,L FN Triple 3–Input NOR Gate CMOS MC54HC27 MC74HC27 14 N,J D TTL SN54LS27 SN74LS27 14 N,J D CMOS MC14025B – 14 P,L D Triple 3–Input NOR Gate (Unbuffered) CMOS MC14025UB – 14 P,L D Triple 4–3–3 Input NOR Gate ECL MC10H106 – 16 P,L FN ECL MC10106 – 16 P,L FN ECL MC10110 – 16 P,L FN ECL MC10H210 – 16 P,L FN ECL MC10210 – 16 P,L FN Dual 4–Input OR Gate CMOS MC14072B – 14 P Low–Voltage CMOS Quad 2–Input OR Gate, 5V–Tolerant Inputs CMOS MC74LCX32 – 14 D,DT Low–Voltage Quiet CMOS Quad 2–Input OR Gate, 5V–Tolerant Inputs CMOS MC74LVQ32 – 14 D,M SD,DT Quad 2–Input OR Gate CMOS MC74AC32 – 14 N D CMOS MC74ACT32 – 14 N D TTL MC74F32 – 14 N D CMOS MC54HC32A 14 N,J D,DT CMOS MC74VHC32 CMOS MC54HCT32A MC74HCT32A 14 N,J TTL SN54LS32 SN74LS32 14 N,J D ECL MC10H103 – 16 P,L FN ECL MC10103 – 16 P,L FN CMOS MC14071B – 14 P,L D GATES, OR Dual 3–Input 3–Output OR Gate Logic: Standard, Special and Programmable 3.1–24 MC74HC32A – 14 D D, DT,M D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM GATES, OR Triple 3–Input OR Gate CMOS MC74HC4075 – 14 N D CMOS MC14075B – 14 P,L D CMOS MC14500B – 16 P DW DTL MC836 – 14 P DTL MC837 – 14 P DTL MC936 – 14 P,L DTL MC937 – 14 P,L DTL MC840 – 14 P 9–Bit Buffer ECL MC10E122 MC100E122 28 FN Driver ECL MC10EL12 MC100EL12 8 D ECL MC100LVEL12 – 8 Dual Complementary Pair Plus Inverter (Unbuffered) CMOS MC14007UB – 14 P D Hex Buffer With Enable ECL MC10H188 – 16 P,L FN INDUSTRIAL CONTROL UNIT Industrial Control Unit INVERTERS Hex Inverter Hex Inverter (Without Input Diodes) INVERTER/BUFFERS, 2–STATE D ECL MC10188 – 16 P,L FN Hex Buffer/Non–Inverting CMOS MC14050B – 16 P,L D Hex Inverter CMOS MC74AC04 – 14 N D CMOS MC74ACT04 – 14 N D TTL MC74F04 – 14 N D CMOS MC54HC04A 14 N,J D,SD, DT CMOS MC74VHC04 TTL SN54LS04 SN74LS04 14 N,J D TTL SN54LS05 SN74LS05 14 N,J D Hex Inverter Gate (Unbuffered) CMOS MC14069UB – 14 P,L D Hex Inverter With Enable ECL MC10H189 – 16 P,L FN MC74HC04A – 14 D, DT,M ECL MC10189 – 16 P,L FN Hex Inverter With LSTTL Compatible Inputs CMOS MC74HCT04A – 14 N D,DT Hex Inverter With open Drain Outputs CMOS MC74AC05 – 14 N D CMOS MC74ACT05 – 14 N D Hex Inverter With Strobe (Active Pullup) HTL MC677 – 14 P,L Hex Inverter With Strobe (Without Output Resistors) HTL MC678 – 14 P,L Hex Inverter/Buffer ECL MC10195 – 16 P,L FN CMOS MC14049B – 16 P D Hex Inverter/Buffer (Unbuffered) CMOS MC14049UB – 16 P,L D Hex Inverting Buffer/Logic–Level Down Converter CMOS MC54HC4049 MC74HC4049 16 N,J D Hex Non–Inverting Buffer/Logic–Level Down Converter CMOS MC54HC4050 MC74HC4050 16 N,J D Hex Unbuffered Inverter CMOS MC74HCU04 – 14 N D CMOS MC74HCU04A – 14 N D,DT Low–Voltage CMOS Hex Inverter, With 5V–Tolerant Inputs CMOS MC74LCX04 – 14 D,DT Low–Voltage Quiet CMOS Hex Inverter CMOS MC74LVQ04 – 14 D,M, SD,DT Quad 2–Input Gate (Active Pullup) HTL MC672 – 14 P,L Quad 2–Input Gate (Passive Pullup) HTL MC668 – 14 P,L Quad Driver ECL MC10E112 Strobed Hex Inverter/Buffer CMOS MC14502B – 16 P,L Triple 3–Input Gate (Active Pullup) HTL MC671 – 14 P,L Triple 3–Input Gate (Passive Pullup) HTL MC670 – 14 P,L Motorola Master Selection Guide 3.1–25 MC100E112 28 FN DW Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM LATCHES 3–Bit 4:1 Mux–Latch (Integrated E156 & E171) ECL MC10E256 MC100E256 28 FN 3–Bit 4:1 Mux–Latch, With Common Enable, Asynchronous Master Reset, Differential Output ECL MC10E156 MC100E156 28 FN 4–Bit D Latch TTL SN54LS75 SN74LS75 16 N,J D TTL SN54LS77 SN74LS77 14 N,J D TTL SN54LS375 SN74LS375 16 N,J 5–Bit 2:1 Mux–Latch, With Common Enable, Asynchronous Master Reset Differential Output ECL MC10E154 MC100E154 28 FN 6–Bit 2:1 Mux–Latch, With Common Enable, Asynchronous Master Reset Single Ended ECL MC10E155 MC100E155 28 FN 6–Bit D Latch ECL MC10E150 MC100E150 28 8–Bit Addressable Latch CMOS MC74AC259 – 16 N D CMOS MC74ACT259 – 16 N D TTL MC74F259 – 16 N D TTL SN54LS259 16 N,J D CMOS MC14099B – 16 P DW CMOS MC14599B – 18 P 8–Bit Bus Compatible Addressable Latch CMOS MC14598B – 18 P,L 9–Bit Latch, With Parity ECL MC10E175 Dual Latch ECL MC10H130 – 16 P,L FN Dual 2–Bit Transparent Latch CMOS MC74HC75 – 16 N D Dual 4–Bit Addressable Latch CMOS MC74AC256 – 16 N DW CMOS MC74ACT256 – 16 N DW TTL MC74F256 – 16 N D TTL SN54LS256 – 16 N,J D Dual 4–Bit Latch CMOS MC14508B – 24 P,L DW Dual Latch ECL MC10130 – 16 P,L Low–Voltage CMOS Octal Transparent Latch, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX373 – 20 DW,M, DT Low–Voltage CMOS 16–Bit Transparent Latch, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16373 – 48 DT Low–Voltage CMOS Octal Transparent Latch Flow Through Pinout, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX573 – 20 DW,M, SD,DT Low–Voltage Quiet CMOS Octal Transparent Latch CMOS MC74LVQ373 – 20 DW,M, SD,DT Low–Voltage Quiet CMOS Octal Transparent Latch Flow Through Pinout CMOS MC74LVQ573 – 20 DW,M, SD,DT Octal 3–State Non–Inverting Transparent Latch With LSTTL Compatible Inputs CMOS MC54HCT373A MC74HCT373A 20 N,J DW, SD,DT Octal D Latch With 3–State Outputs CMOS MC74AC563 – 20 N DW CMOS MC74ACT563 – 20 N DW CMOS MC74AC573 – 20 N DW CMOS MC74ACT573 – 20 N DW CMOS MC74AC373 – 20 N DW CMOS MC74ACT373 – 20 N DW TTL SN54LS373 20 N,J DW TTL MC74F373 – 20 N DW TTL MC74F533 – 20 N DW CMOS MC74AC533 – 20 N DW CMOS MC74ACT533 – 20 N DW Octal Transparent Latch With 3–State Outputs Logic: Standard, Special and Programmable 3.1–26 SN74LS259 MC100E175 SN74LS373 D FN 28 FN FN Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM LATCHES Octal With 3–State Outputs Inverting Transparent Latch CMOS MC54HC533A MC74HC533A 20 N,J DW CMOS MC54HC563A MC74HC563A 20 N,J DW,DT CMOS MC54HC373A MC74HC373A 20 N,J DW, DT,SD CMOS MC74VHC373 CMOS MC54HC573A CMOS MC74VHC573 – 20 Octal With 3–State Outputs Non–Inverting Transparent Latch With LSTTL Compatible Inputs CMOS MC74HCT573A – 20 N DW Quad Latch ECL MC10133 – 16 P,L FN ECL MC10153 – 16 P,L FN Quad NAND R–S Latch CMOS MC14044B – 16 P D Quad NOR R–S Latch CMOS MC14043B – 16 P,L D Quad Set/Reset Latch TTL SN54LS279 16 N,J D Quad Transparent Latch CMOS MC14042B – 16 P,L D Quint Latch ECL MC10H175 – 16 P,L FN ECL MC10175 – 16 P,L FN ECL MC10H660 ECL MC10E197 CMOS CMOS 16–Channel Analog Multiplexer/Demultiplexer CMOS MC14067B 16:1 Multiplexer ECL MC10E164 MC100E164 28 FN 2–Bit 8:1 Multiplexer ECL MC10E163 MC100E163 28 FN 2:1 Multiplexer ECL MC10EL58 MC100EL58 8 D 3–Bit 4:1 Multiplexer, With Split Select Differential Output ECL MC10E171 MC100E171 28 FN 4:1 Differential Multiplexer ECL MC10EL57 MC100EL57 16 D 5–Bit 2:1 Multiplexer, With Differential Output ECL MC10E158 MC100E158 28 FN 8–Channel Analog Multiplexer/Demultiplexer With Address Latch CMOS MC54HC4351 MC74HC4351 20 N,J DW 8–Channel Analog Multiplexer/Demultiplexer CMOS MC54HC4051 MC74HC4051 16 N,J D, DW ,DT Octal With 3–State Outputs Non–Inverting Transparent Latch – MC74HC573A SN74LS279 20 20 DW, DT,M N,J DW DW, DT,M MEMORY SUPPORT 4–Bit ECL–TTL Load Reducing DRAM Driver MC100H660 28 FN – 28 FN MC74AC151 – 16 N D MC74ACT151 – 16 N D – 24 P DW MISCELLANEOUS Data Separator MULTIPLEXER/DATA SELECTORS 1–of–8 Decoder/Demultiplexer CMOS MC14051B – 16 P,L D 8–Channel Data Selector CMOS MC14512B – 16 P,L D 8–Input Data Selector/Multiplexer CMOS MC74HC151 – 16 N D 8–Input Data Selector/Multiplexer With 3–State Outputs CMOS MC54HC251 16 N,J D 8–Input Multiplexer TTL MC74F151 16 N D TTL SN54LS151 SN74LS151 16 N,J D TTL SN54LS251 SN74LS251 16 N,J D TTL MC74F251 – 16 N D CMOS MC74AC251 – 16 N D CMOS MC74ACT251 – 16 N D 8–Input Data Selector/Multiplexer With Data and Address Latchs and With 3–State Outputs CMOS MC54HC354 20 N,J DW 8–Line Multiplexer ECL MC10H164 – 16 P,L FN ECL MC10164 – 16 P,L FN CMOS MC74HC4851A MC74HC4852A 16 N MC74HC4853A – D,DW, DT 8–Input Multiplexer With 3–State Outputs Analog With Injection Current Effect g Multiplexer/Demultiplexer p p j Control Automotive Customized Control, Motorola Master Selection Guide 3.1–27 MC74HC251 – MC74HC354 Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM MULTIPLEXER/DATA SELECTORS Dual 4–Channel Analog Data Selector CMOS MC14529B – 16 P D Dual 4–Channel Analog Multiplexer/Demultiplexer CMOS MC74HC4052 – 16 N D, DW CMOS MC14052B – 16 P,L D Dual 4–Channel Data Selector/Multiplexer CMOS MC14539B – 16 P D Dual 4–Input Data Selector/Multiplexer CMOS MC74HC153 – 16 N D Dual 4–Input Data Selector/Multiplexer With 3–State Outputs CMOS MC74HC253 – 16 N D Dual 4–Input Multiplexer CMOS MC74AC153 – 16 N D CMOS MC74ACT153 – 16 N D CMOS MC74AC352 – 16 N DW CMOS MC74ACT352 – 16 N DW TTL MC74F153 – 16 N D TTL MC74F352 – 16 N D TTL SN54LS153 SN74LS153 16 N,J D TTL SN54LS352 SN74LS352 16 N,J D CMOS MC74AC253 – 16 N DW CMOS MC74ACT253 – 16 N DW CMOS MC74AC353 – 16 N D CMOS MC74ACT353 – 16 N D TTL SN54LS253 SN74LS253 16 N,J D TTL SN54LS353 SN74LS353 16 N,J D TTL MC74F253 – 16 N D TTL MC74F353 – 16 N D ECL MC10H174 – 16 P,L FN – 16 P,L Dual 4–Input Multiplexer With 3–State Outputs Dual 4–to–1 Multiplexer ECL MC10174 Dual Differential 2:1 Multiplexer (3.3V) ECL MC100LVEL56 Dual Multiplexer With Latch ECL MC10134 – 16 Low Voltage 16:1 Multiplexer ECL MC100LVE164 – 32 FA Low–Voltage CMOS Quad 2–Input, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX157 – 16 M,D, SD,DT Quad 2–Input Multiplexer With Latch ECL MC10H173 – 16 P,L FN Quad 2–Channel Analog Multiplexer/Demultiplexer CMOS MC14551B – 16 P D Quad 2–Input Data Selector/Multiplexer CMOS MC54HC158 16 N,J D CMOS MC74HC158A – 16 N,J D,DT Quad 2–Input Data Selector/Multiplexer With 3–State Outputs CMOS MC74HC257 – 16 N D Quad 2–Input Data Selectors/Multiplexers CMOS MC54HC157A 16 N,J D,DT CMOS MC74VHC157 – 16 Quad 2–Input Data Selector/Multiplexer With LSTTL Compatible Inputs CMOS MC74HCT157A – 16 N D Quad 2–Input Multiplexer TTL MC74F157A – 16 N D TTL MC74F158A – 16 N D TTL SN54LS157 SN74LS157 16 N,J D SN74LS158 MC100EL56 MC74HC158 MC74HC157A 20 FN DW P,L FN D, DT,M TTL SN54LS158 16 N,J D Quad 2–Input Multiplexer (Inverting) ECL MC10159 – 16 P,L FN Quad 2–Input Multiplexer (Non–Inverting) ECL MC10158 – 16 P,L FN Quad 2–Input Multiplexer Inverting With 3–State Outputs CMOS MC74AC258 – 16 N DW CMOS MC74ACT258 – 16 N DW CMOS MC74ACT257 – 16 N D CMOS MC74AC257 – 16 N D Quad 2–Input Multiplexer With 3–State Outputs TTL SN54LS257B SN74LS257B 16 N,J D Quad 2–Input Multiplexer With Storage TTL SN54LS298 SN74LS298 16 N,J D Quad 2–Input Multiplexer Non–Inverting With 3–State Outputs Logic: Standard, Special and Programmable 3.1–28 Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM D MULTIPLEXER/DATA SELECTORS Quad 2–Input Multiplexer, Inverting CMOS MC74AC158 – 16 N CMOS MC74ACT158 – 16 N D Quad 2–Input Multiplexer, Inverting Output ECL MC10H159 – 16 P,L FN Quad 2–Input Multiplexer, Inverting, With 3–State Outputs TTL SN54LS258B 16 N,J D Quad 2–Input Multiplexer, Non–Inverting CMOS MC74AC157 – 16 N D CMOS MC74ACT157 – 16 N D Quad 2–Input Multiplexer, Non–Inverting Output ECL MC10H158 – 16 P,L FN Quad 2–Input Multiplexer, With 3–State Outputs TTL MC74F257A – 16 N D SN74LS258B TTL MC74F258A – 16 N D Quad 2–Input Multiplexer/Latch ECL MC10173 – 16 P,L FN Quad 2–Port Register TTL MC74F398 – 20 N DW TTL MC74F399 – 16 N D TTL SN54LS398 SN74LS398 20 N,J DW TTL SN54LS399 SN74LS399 16 N,J Quad 2:1 Mux, Individual–Select ECL MC10E157 MC100E157 28 Quad Analog Switch/Multiplexer CMOS MC14016B CMOS MC14066B CMOS MC54HC4016 MC74HC4016 CMOS MC54HC4066 MC74HC4066 Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/Digital Power Supplies CMOS MC74HC4316 Triple 2–Channel Analog Multiplexer/Demultiplexer CMOS MC54HC4053 CMOS MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer With Address Latch CMOS MC54HC4353 Triple 2:1 Multiplexer ECL MC100EL59 – 20 DW Triple 2:1 Multiplexer (3.3V) ECL MC100LVEL59 – 20 DW Triple Differential 2:1 Multiplexer ECL MC100E457 – 28 FN ECL MC10E457 – 28 FN 130MHz Voltage Controlled Multivibrator ECL MC12101 – 20 P FN 200 MHz Voltage Controlled Multivibrator ECL MC12100 – 20 P FN Dual Monostable Multivibrator HTL MC667 – 14 P,L CMOS MC14528B – 16 P,L D Dual Monstable Multivibrators With Schmitt Trigger Inputs TTL SN54LS221 SN74LS221 16 N,J D Dual Precision Monostable Multivibrator Retriggerable, Resettable) CMOS MC54HC4538A MC74HC4538A 16 N,J D Dual Precision Monostable Multivibrator CMOS MC14538B – 16 P,L D, DW Dual Voltage–Controlled Multivibrator ECL MC4024 – 14 P,L Monostable Multivibrator DTL MC951 – 14 P,L ECL MC10198 – 16 P,L FN TTL SN54LS122 SN74LS122 14 N,J D TTL SN54LS123 SN74LS123 14 N,J D ECL MC1658 – 16 P,L D,FN 7–Stage Binary Ripple Counter CMOS MC74HC4024 – 14 N D Crystal Oscillator ECL MC12061 – 16 P,L Dual Voltage–Controlled Multivibrator ECL MC4324 – 14 P,L Low Power Voltage Controlled Oscillator ECL MC12148 – 8 Quad Analog Switch/Multiplexer/Demultiplexer – 14 – – MC74HC4053 – MC74HC4353 D FN P,L D 14 P,L D 14 N,J D 14 N,J D,DT 16 N D 16 N,J D, DW 16 P,L D 20 N,J DW MULTIVIBRATORS Retriggerable Monostable Multivibrators Voltage Controlled Multivibrator OSCILLATORS Motorola Master Selection Guide 3.1–29 D,SD Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM OSCILLATORS Voltage Controlled Oscillator ECL MC1648 – 14 P,L D,FN 24–Stage Frequency Divider CMOS MC14521B – 16 P,L D Programmable Oscillator Timer CMOS MC14541B – 14 P,L D Programmable Timer CMOS MC14536B – 16 P,L DW Quad Precision Timer/Driver CMOS MC14415 – 16 P,L DW ECL MC10H160 – 16 P,L FN ECL MC10160 – 16 P,L FN 12–Bit Parity Generator/Checker, Register–Shiftable, Diff Output ECL MC10E160 12–Bit Parity Tree CMOS MC14531B – 16 P D 9 + 2–Bit Parity Generator–Checker ECL MC10170 – 16 P,L FN 9–Bit Odd/Even Parity Generator/Checker CMOS MC74HC280 – 14 N D 14 N,J D 14 N OSCILLATOR/TIMERS PARITY CHECKERS 12–Bit Parity Generator/Checker MC100E160 SN74LS280 28 FN TTL SN54LS280 9–Bit Parity Generator/Checker TTL MC74F280 Error Detection and Correction Circuit ECL MC10E193 CMOS MC14046B – 16 P,L 1.1GHz ÷10/20/40/80 Prescaler ECL MC12080 – 8 P 1.1GHz ÷126/128, ÷254/256 Low Power Dual Modulus Prescaler ECL MC12058 – 8 1.1GHz ÷127/128, ÷255/256 Low Power Dual Modulus Prescaler ECL MC12038A – 8 P D 1.1GHz ÷8/9, ÷16/17 Dual Modulus Prescaler ECL MC12026A – 8 P D D – MC100E193 28 D FN PHASE–LOCKED LOOP Phase–Locked Loop DW PRESCALERS D D,SD ECL MC12026B – 8 P 1.1GHz ÷2 Low Power Prescaler With Stand–By Mode ECL MC12083 – 8 P D 1.1GHz ÷2/4/8 Low Power Prescaler With Stand–By Mode ECL MC12093 – 8 P D,SD 1.1GHz ÷256 Prescaler ECL MC12074 – 8 P D 1.1GHz ÷32/33, ÷64/65 Dual Modulus Prescaler ECL MC12028A – 8 P D 1.1GHz ÷32/33, ÷64/65 Dual Modulus Prescaler ECL MC12028B – 8 P D 1.1GHz ÷64 Prescaler ECL MC12073 – 8 P D 1.1GHz ÷64/65, ÷128/129 Dual Modulus Prescaler ECL MC12022A – 8 P D ECL MC12022B – 8 P D ECL MC12022SLA – 8 P D ECL MC12022SLB – 8 P D ECL MC12022TSA – 8 P D ECL MC12022TSB – 8 P D 1.1GHz ÷64/65, ÷128/129 Dual Modulus Prescaler With Stand–By y Mode ECL MC12036A – 8 P D ECL MC12036B – 8 P D 1.1GHz ÷64/65, ÷128/129 Low Voltage Dual Modulus Prescaler ECL MC12022LVA – 8 P D ECL MC12022LVB – 8 P D ECL MC12022TVA – 8 P D ECL MC12022TVB – 8 P 1.1GHz ÷64/65, ÷128/129 Super Low Power Dual Modulus Prescaler ECL MC12052A – 8 D,SD 1.1GHz ÷64/65, ÷128/129 Super Low Power Dual Modulus Prescaler With Stand–By Mode ECL MC12053A – 8 D,SD 1.3GHz ÷64 Prescaler ECL MC12075 – 8 1.3GHz ÷64/256 Prescaler ECL MC12066 – 8 Logic: Standard, Special and Programmable 3.1–30 P D D D Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM PRESCALERS 1.3GHz ÷256 Prescaler ECL MC12076 – 8 P D ECL MC12078 – 8 P D ECL MC12034A – 8 P D ECL MC12034B – 8 P D ECL MC12033A – 8 P D ECL MC12033B – 8 P D ECL MC12032A – 8 P D ECL MC12032B – 8 P D ECL MC12031A – 8 P D ECL MC12031B – 8 P 2.0GHz ÷64/65, ÷128/129 Super Low Power Dual Modulus Prescaler ECL MC12054A – 8 D,SD 2.5GHz ÷2, ÷4 Low Power Prescaler With Satnd–By Mode ECL MC12095 – 8 D,SD 2.5GHz ÷8192 Prescaler ECL MC12098 – 8 2.8GHz ÷64/128/256 Prescaler ECL MC12079 – 8 P D ECL MC12089 – 8 P D 225MHz ÷20/21 Dual Modulus Prescaler ECL MC12019 – 8 P,L D 225MHz ÷32/33 Dual Modulus Prescaler ECL MC12015 – 8 P,L D 225MHz ÷40/41 Dual Modulus Prescaler ECL MC12016 – 8 P,L D 225MHz ÷64 Prescaler ECL MC12023 – 8 P D 225MHz ÷64/65 Dual Modulus Prescaler ECL MC12017 – 8 P,L D 480MHz ÷5/6 Dual Modulus Prescaler ECL MC12009 – 16 P,L 520MHz ÷128/129 Dual Modulus Prescaler ECL MC12018 – 8 P,L D 520MHz ÷64/65 Dual Modulus Prescaler ECL MC12025 – 8 P D 550MHz ÷10/11 Dual Modulus Prescaler ECL MC12013 – 16 P,L 550MHz ÷8/9 Dual Modulus Prescaler ECL MC12011 – 16 P,L 750MHz ÷2 UHF Prescaler ECL MC12090 – 16 P,L Programmable Delay Chip (Dig 80ps Anal. 1.6 Ps/mv) ECL MC10E196 MC100E196 28 FN Programmable Delay Chip (Digitally Selectable 20ps Res) ECL MC10E195 MC100E195 28 FN 1024 X 1–Bit Random Access Memory ECL MCM10146 – 16 L 256 X 1–Bit Random Access Memory ECL MCM10152 – 16 L ECL MC10EL16 ECL MC100LVEL16 – 8 High Speed Triple Line Receiver ECL MC10216 – 16 Low–Voltage Quad Differential Line Receiver ECL MC100LVEL17 Quad Bus Receiver ECL MC10129 – 16 L Quad Line Receiver ECL MC10H115 – 16 P,L FN ECL MC10115 – 16 P,L FN ECL MC1692 – 16 L ECL MC10E116 MC100E116 28 FN ECL MC10E416 MC100E416 28 FN 2.0GHz ÷32/33, ÷64/65 Dual Modulus Prescaler 2.0GHz ÷32/33, ÷64/65 Low Voltage Dual Modulus Prescaler 2.0GHz ÷64/65, ÷128/129 Dual Modulus Prescaler 2.0GHz ÷64/65, ÷128/129 Low Voltage Dual Modulus Prescaler D D PROGRAMMABLE DELAY CHIPS RAMs RECEIVERS Differential Receiver Quint Differential Line Receiver Motorola Master Selection Guide 3.1–31 MC100EL16 MC100EL17 8 D D P,L 20 FN DW Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM RECEIVERS Triple Line Receiver ECL MC10H116 – 16 P,L D,FN ECL MC10114 – 16 P,L FN ECL MC10116 – 16 P,L FN 4 X 4 Multiport Register CMOS MC14580B – 24 P,L D Hex Parallel D Register With Enable TTL MC74F378 – 16 N D 16 X 4–Bit Register File (RAM) ECL MC10H145 – 16 P,L FN 4 X 4 Register File Open Collector TTL SN54LS170 SN74LS170 16 N,J D 4 X 4 Register File With 3–State Outputs TTL SN54LS670 SN74LS670 16 N,J D 64–Bit Register File (RAM) ECL MCM10145 – 16 L 8 X 2 Multiport Register File (RAM) ECL MCM10143 – 24 L TTL MC74F13 – 14 N D TTL SN54LS13 14 N,J D Dual Schmitt Trigger CMOS MC14583B – 16 P D Hex Inverter Schmitt Trigger CMOS MC74AC14 – 14 N D CMOS MC74ACT14 – 14 N D TTL MC74F14 – 14 N D TTL SN54LS14 14 N,J D CMOS MC14106B – 14 P,L D CMOS MC14584B – 14 P,L D CMOS MC54HC14A 14 N,J D,DT CMOS MC74VHC14 REGISTERS REGISTER FILES SCHMITT TRIGGERS Dual 4–Input NAND Schmitt Trigger Hex Schmitt Trigger Hex Schmitt Trigger Inverter SN74LS13 SN74LS14 MC74HC14A – 14 D, DT,M CMOS MC54HCT14A MC74HCT14A 14 N,J D Quad 2–Input NAND Gate With Schmitt Trigger Inputs CMOS MC54HC132A MC74HC132A 14 N,J D Quad 2–Input NAND Schmitt Trigger CMOS MC74AC132 – 14 N D CMOS MC74ACT132 – 14 N D TTL MC74F132 – 14 N D CMOS MC14093B – 14 P,L D TTL SN54LS132 14 N,J D 9–Bit Switchable Active SCSI–2 Bus Term (110Ω) with Volt Reg CMOS MCCS142237 – 16,20 DW, DT 9–Bit Switchable SCSI Bus Term (220Ω & 330Ω: Passive) CMOS MCCS142233 – 20 FN 18–Bit Active SCSI Bus Terminator (*Also Available in 32–Pin QFP Package) CMOS MCCS142235 – 24,32 DW, *FA 18–Bit Switchable Active SCSI–2 Bus Term (110Ω) with Volt Reg CMOS MCCS142236 – 28 DW 18–Bit Switchable Active SCSI–2 Bus Term (110Ω) with Volt Reg Plus Inverted Disconnect CMOS MCCS142238 – 28 DW 9–Bit Switchable Active SCSI Bus Terminator (110Ω) with Volt Reg CMOS MCCS142239 – 16 D,DW Serial EPROM for MPA1016: 8–Pin DIP and SOIC; 20–Pin PLCC CMOS MPA1765 – 8,20 N D,FN Serial EPROM for MPA1036: 8–Pin DIP and SOIC; 20–Pin PLCC CMOS MPA17128 – 8,20 P D,FN 1–to–64–Bit Variable Length Shift Register CMOS MC14557B – 16 P,L DW 128–Bit Static Shift Register CMOS MC14562B – 14 P,L 18–Bit Static Shift Register CMOS MC14006B – 14 P,L 3–Bit Scannable Registered Address Driver, ECL ECL MC10E212 Quad 2–Input Schmitt Trigger NAND Gate SN74LS132 SCSI BUS TERMINATORS SERIAL EPROMs SHIFT REGISTERS Logic: Standard, Special and Programmable 3.1–32 MC100E212 28 D FN Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM SHIFT REGISTERS 4–Bit Bidirectional Universal Shift Register CMOS MC74AC194 – 16 N D CMOS MC74ACT194 – 16 N D TTL MC74F194 – 16 N D CMOS MC74HC194 – 16 N TTL SN54LS194A 16 N,J D TTL MC74F195 16 N D TTL SN54LS95B 14 N,J D CMOS MC14035B – 16 P,L D 4–Bit Shift Register With 3–State Outputs TTL SN74LS395 – 16 N,J D 4–Bit Shifter With 3–State CMOS MC74AC350 – 16 N D CMOS MC74ACT350 – 16 N D 4–Bit Shifter, With 3–State Outputs TTL MC74F350 – 16 N D 4–Bit Universal Shift Register CMOS MC74HC195 – 16 N ECL MC10H141 – 16 P,L FN ECL MC10141 – 16 P,L FN CMOS MC14194B – 16 P,L D 8–Bit Bidirectional Universal Shift Register With parallel I/O CMOS MC74HC299 – 20 N DW 8–Bit Parallel–to–Serial Shift Register TTL SN54LS165 SN74LS165 16 N,J 8–Bit Scannable Register ECL MC10E241 MC100E241 28 8–Bit Serial In–Serial Out Shift Register TTL MC74F164 8–Bit Serial or Parallel–Input/Serial–Output Shift Register CMOS MC54HC165 8–Bit Serial or Parallel–Input/Serial–Output p p Shift Register g With 3–State 3 State Outputs O tp ts CMOS MC54HC589 CMOS 8–Bit Serial or Parallel–Input/Serial–Output p p Shift Register g With Inp t Latch Input 4–Bit Shift Register SN74LS194A – SN74LS95B 14 N D MC74HC165 16 N,J D MC74HC589 16 N,J D MC54HC589A MC74HC589A 16 N,J D,SD DT CMOS MC54HC597 MC74HC597 16 N,J D CMOS MC54HC597A MC74HC597A 16 N,J D,DT 8–Bit Serial–In/Parallel–Out Shift Register TTL SN54LS164 SN74LS164 14 N,J D 8–Bit Serial–Input/Parallel–Output Shift Register CMOS MC54HC164 MC74HC164 14 N,J D CMOS MC54HC164A MC74HC164A 14 N,J D,DT CMOS MC54HC595A MC74HC595A 16 N,J D,DT CMOS MC74VHC595 ECL MC10E141 MC100E141 28 TTL SN54LS166 SN74LS166 16 N,J D 8–Bit Shift Registers With Sign Extend TTL SN54LS322A SN74LS322A 20 N,J DW 8–Bit Shift/Storage Register With 3–State Outputs TTL SN54LS299 SN74LS299 20 N,J DW TTL SN54LS323 SN74LS323 20 N,J DW CMOS MC14014B – 16 P,L D CMOS MC14021B – 16 P,L D 8–Input Shift/Storage Register W/Synchronous Reset and Common I/O Pins TTL MC74F323 – 20 N DW 8–Input p Universal Shift/Storage g Register g With Common Parallel I/O Pins With 3–State Pins: 3 State Outputs O tp ts CMOS MC74AC299 – 20 N DW CMOS MC74ACT299 – 20 N DW 8–Input p Universal Shift/Storage g Register g With Syn y Reset/Common Parallel I/O Pins: Pins With 3 3–State State O Outputs tp ts CMOS MC74AC323 – 20 N DW CMOS MC74ACT323 – 20 N DW 8–Input Universal Shift/Storage Register, W/Common Parallel I/O Pins TTL MC74F299 – 20 N DW 8–Stage Shift/Store Register With 3–State Outputs CMOS MC14094B – 16 P,L 9–Bit Shift Register, 700MHz, With Asynchronous Master Reset ECL MC10E142 Dual 5–Bit Shift Register CMOS MC14015B 8–Bit Serial–Input/Serial or Parallel–Output Shift Register With Latched 3–State Outputs 8–Bit Shift Register 8–Bit Static Shift Register Motorola Master Selection Guide 3.1–33 – D FN – MC100E142 – 16 D, DT,M FN 28 16 D FN P,L D Logic: Standard, Special and Programmable Selection by Function Description Tech. Device(s) Pins DIP SM SHIFT REGISTERS Dual 64–Bit Static Shift Register CMOS MC14517B – 16 P DW Successive Approximation Register CMOS MC14549B – 16 P,L DW CMOS MC14559B – 16 P,L DW TTL SN54LS195A 16 N,J D 1.1GHz Serial Input Synthesizer With ÷64/65, ÷128/129 Prescaler ECL MC12202 – 16,20 D,M, DT 125–1000MHz Frequency Synthesizer With Parallel Programming Interface ECL MC12181 – 16 DT 2.0GHz Serial Input Synthesizer With ÷64/65, ÷128/129 Prescaler ECL MC12206 – 16,20 D,DT 2.5GHz Serial Input Synthesizer With ÷32/33, ÷64/65 Prescaler ECL MC12210 – 16,20 D,DT 2.7GHz Frequency Synthesizer ECL MC12179 – 8 D 25Ω Octal Bidirectional Transceiver w/ 3–State Inputs and Outputs ECL MC74F2245 – 20 DW,SD 4–Bit Differential ECL Bus/TTL Bus Transceiver ECL MC10H680 28 FN Dual Supply Octal Translating Transceiver CMOS MC74LVX4245 – 24 DW,DT ECL/TTL Inverting Bidirectional Transceivers With Latch (4–Bit) ECL MC10804 – 16 L ECL/TTL Inverting Bidirectional Transceivers With Latch (5–Bit) ECL MC10805 – 20 L Hex ECL/TTL Transceiver With Latches ECL MC10H681 28 FN Low–Voltage CMOS 16–Bit Latching Transceiver, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16543A – 56 DT Low–Voltage CMOS 16–Bit Transceiver, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16245 – 48 DT Low–Voltage CMOS 18–Bit Universal Bus Transceiver, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX16500 – 56 DT Universal 4–Bit Shift Register SN74LS195A SYNTHESIZERS TRANSCEIVERS MC100H680 MC100H681 CMOS MC74LCX16501 – 56 DT Low–Voltage CMOS Octal Registered Transceiver With Dual Output and Clock Enables, With 5V Tolerant Inputs and Outputs CMOS MC74LCX2952 – 24 DW, SD,DT Low–Voltage CMOS Octal Transceiver, 3–State, Non–Inverting With 5V Tolerant Inputs and Outputs CMOS MC74LCX245 – 20 M,DW, DT Low–Voltage Quiet CMOS Octal Transceiver, 3–State, Non–Inverting CMOS MC74LVQ245 – 20 M,DW, SD,DT Low–Voltage CMOS Octal Transceiver/Registered Transceiver With 5V Tolerant Inputs and Outputs CMOS MC74LCX646 – 24 DW, SD,DT Low–Voltage CMOS Octal Transceiver/Registered Transceiver With Dual Enable, With 5V Tolerant Inputs and Outputs CMOS MC74LCX652 – 24 DW, DT Low–Voltage Quiet CMOS Octal Transceiver/Registered Transceiver CMOS MC74LVQ646 – 24 DW, SD,DT Low–Voltage Quiet CMOS Octal Transceiver/Registered Transceiver CMOS MC74LVQ652 – 24 DW, SD,DT Octal Bus Transceiver/Inverting With Open Collector TTL SN54LS642 SN74LS642 20 N,J DW Octal Bus Transceiver/Non–Inverting With Open Collector TTL SN54LS641 SN74LS641 20 N,J DW Quad Futurebus Backplane Transceiver, With 3–State Outputs and Open Collector TTL MC74F3893A 9–Bit ECL/TTL Translator ECL MC10H601 9–Bit Latch ECL/TTL Translator ECL MC10H603 9–Bit Latch TTL/ECL Translator ECL 9–Bit TTL/ECL Translator – 20 FN MC100H601 28 FN MC100H603 28 FN MC10H602 MC100H602 28 FN ECL MC10H600 MC100H600 28 FN Differential ECL/TTL Translator ECL MC10ELT25 MC100ELT25 8 D Differential PECL/TTL Translator ECL MC10ELT21 MC100ELT21 8 D Dual Differential PECL/TTL Translator ECL MC100ELT23 – 8 D Dual LVTTL/LVCMOS to Differential PECL Translator ECL MC100LVELT22 – 8 D Dual TTL/Differential PECL Translator ECL MC10ELT22 8 D TRANSLATORS Logic: Standard, Special and Programmable 3.1–34 MC100ELT22 Motorola Master Selection Guide Selection by Function Description Tech. Device(s) Pins DIP SM FN TRANSLATORS ECL/TTL Translator (Single P.S. @+ 5.0V) ECL MC10H350 – 16 P,L Hex ECL/MST Translator ECL MC10191 – 16 P,L Hex TTL OR CMOS/CMOS Hex Level Shifter CMOS MC14504B – 16 P,L D Quad CMOS/ECL Translator (Single P.S. @+ 5.0V) ECL MC10H352 – 20 P,L FN Quad MECL/TTL Translator ECL MC10H125 – 16 P,L FN ECL MC10125 – 16 P,L FN Quad MST/ECL Translator ECL MC10190 – 16 P Quad TTL/ECL Translator (ECL Strobe) ECL MC10H424 – 16 P,L FN Quad TTL/MECL Translator ECL MC10124 – 16 P,L FN Quad TTL/MECL Translator, With TTL Strobe Input ECL MC10H124 – 16 P,L FN Quad TTL/NMOS–to–PECL Translator (Single P.S. @+ 5.0V) ECL MC10H351 – 20 P,L FN Registered Hex ECL/TTL Translator ECL MC10H605 MC100H605 28 FN Registered Hex PECL/TTL Translator ECL MC10H607 MC100H607 28 FN Registered Hex TTL/ECL Translator ECL MC10H604 MC100H604 28 FN Registered Hex TTL/PECL Translator ECL MC10H606 MC100H606 28 Triple MECL/NMOS Translator ECL MC10177 Triple ECL to PECL Translator ECL MC100LVEL90 20 DW Triple PECL to LVPECL Translator ECL MC100LVEL92 – 20 DW Triple PECL to ECL Translator ECL MC100LVEL91 – 20 DW TTL/Differential ECL Translator ECL MC10ELT24 MC100ELT24 8 D TTL/Differential PECL Translator ECL MC10ELT20 MC100ELT20 8 D TTL to Differential PECL/Differential PECL to TTL Translator ECL MC10ELT28 MC100ELT28 8 D Phase–Locked–Loop With VCO CMOS MC74HC4046A – 16 Low Power Voltage Controlled Oscillator Buffer CMOS MC12147 – 8 D,SD Low Power Voltage Controlled Oscillator Buffer CMOS MC12149 – 8 D,SD – MC100EL90 16 FN L VCO Motorola Master Selection Guide 3.1–35 N D Logic: Standard, Special and Programmable Device Index MC100E016 3.1–15 MC100EL11 3.1–12 MC100LVE310 3.1–9 MC100E101 3.1–23 MC100EL12 3.1–25 MC100LVEL01 3.1–22 MC100E104 3.1–23 MC100EL13 3.1–9 MC100LVEL05 3.1–22 MC100E107 3.1–23 MC100EL14 3.1–12 MC100LVEL11 3.1–9 MC100E111 3.1–12 MC100EL15 3.1–12 MC100LVEL12 3.1–25 MC100E112 3.1–25 MC100EL16 3.1–31 MC100LVEL13 3.1–9 MC100E116 3.1–31 MC100EL17 3.1–31 MC100LVEL14 3.1–12 MC100E122 3.1–25 MC100EL29 3.1–19 MC100LVEL16 3.1–31 MC100E131 3.1–18 MC100EL30 3.1–21 MC100LVEL17 3.1–31 MC100E136 3.1–14 MC100EL31 3.1–18 MC100LVEL29 3.1–19 MC100E137 3.1–15 MC100EL32 3.1–17 MC100LVEL30 3.1–21 MC100E141 3.1–33 MC100EL33 3.1–17 MC100LVEL31 3.1–20 MC100E142 3.1–33 MC100EL34 3.1–13 MC100LVEL32 3.1–17 MC100E143 3.1–18 MC100EL35 3.1–19 MC100LVEL33 3.1–17 MC100E150 3.1–26 MC100EL38 3.1–13 MC100LVEL38 3.1–13 MC100E151 3.1–18 MC100EL39 3.1–13 MC100LVEL39 3.1–13 MC100E154 3.1–26 MC100EL51 3.1–18 MC100LVEL51 3.1–18 MC100E155 3.1–26 MC100EL52 3.1–18 MC100LVEL56 3.1–28 MC100E156 3.1–26 MC100EL56 3.1–28 MC100LVEL59 3.1–29 MC100E157 3.1–29 MC100EL57 3.1–27 MC100LVEL90 3.1–35 MC100E158 3.1–27 MC100EL58 3.1–27 MC100LVEL91 3.1–35 MC100E160 3.1–30 MC100EL59 3.1–29 MC100LVEL92 3.1–35 MC100E163 3.1–27 MC100EL90 3.1–35 MC100LVELT22 3.1–34 MC100E164 3.1–27 MC100ELT20 3.1–35 MC100SX1230 3.1–18 MC100E166 3.1–14 MC100ELT21 3.1–34 MC10101 3.1–23 MC100E167 3.1–18 MC100ELT22 3.1–34 MC10102 3.1–24 MC100E171 3.1–27 MC100ELT23 3.1–34 MC10103 3.1–24 MC100E175 3.1–26 MC100ELT24 3.1–35 MC10104 3.1–21 MC100E193 3.1–30 MC100ELT25 3.1–34 MC10105 3.1–23 MC100E195 3.1–31 MC100ELT28 3.1–35 MC10106 3.1–24 MC100E196 3.1–31 MC100H600 3.1–34 MC10107 3.1–23 MC100E210 3.1–9 MC100H601 3.1–34 MC10109 3.1–23 MC100E211 3.1–12 MC100H602 3.1–34 MC10110 3.1–24 MC100E212 3.1–32 MC100H603 3.1–34 MC10111 3.1–24 MC100E241 3.1–33 MC100H604 3.1–35 MC10113 3.1–23 MC100E256 3.1–26 MC100H605 3.1–35 MC10114 3.1–32 MC100E310 3.1–9 MC100H606 3.1–35 MC10115 3.1–31 MC100E336 3.1–10 MC100H607 3.1–35 MC10116 3.1–32 MC100E337 3.1–10 MC100H640 3.1–13 MC10117 3.1–23 MC100E404 3.1–23 MC100H641 3.1–13 MC10121 3.1–22 MC100E416 3.1–31 MC100H642 3.1–13 MC10123 3.1–12 MC100E431 3.1–18 MC100H643 3.1–13 MC10124 3.1–35 MC100E445 3.1–14 MC100H644 3.1–13 MC10125 3.1–35 MC100E446 3.1–14 MC100H646 3.1–13 MC10129 3.1–31 MC100E451 3.1–18 MC100H660 3.1–27 MC10130 3.1–26 MC100E452 3.1–18 MC100H680 3.1–34 MC10131 3.1–19 MC100E457 3.1–29 MC100H681 3.1–34 MC10133 3.1–27 MC100EL01 3.1–22 MC100LVE111 3.1–12 MC10134 3.1–28 MC100EL04 3.1–22 MC100LVE164 3.1–28 MC10135 3.1–19 MC100EL05 3.1–22 MC100LVE210 3.1–9 MC10136 3.1–16 MC100EL07 3.1–22 MC100LVE222 3.1–13 MC10137 3.1–16 TTL, ECL, CMOS and Special Logic Circuits 3.1–36 Motorola Master Selection Guide Device Index MC10138 3.1–15 MC10E141 3.1–33 MC10EL52 3.1–18 MC10141 3.1–33 MC10E142 3.1–33 MC10EL57 3.1–27 MC10153 3.1–27 MC10E143 3.1–18 MC10EL58 3.1–27 MC10154 3.1–15 MC10E150 3.1–26 MC10EL89 3.1–17 MC10158 3.1–28 MC10E151 3.1–18 MC10ELT20 3.1–35 MC10159 3.1–28 MC10E154 3.1–26 MC10ELT21 3.1–34 MC10160 3.1–30 MC10E155 3.1–26 MC10ELT22 3.1–34 MC10161 3.1–16 MC10E156 3.1–26 MC10ELT24 3.1–35 MC10162 3.1–16 MC10E157 3.1–29 MC10ELT25 3.1–34 MC10163 3.1–17 MC10E158 3.1–27 MC10ELT28 3.1–35 MC10164 3.1–27 MC10E160 3.1–30 MC10H100 3.1–24 MC10165 3.1–18 MC10E163 3.1–27 MC10H101 3.1–23 MC10166 3.1–14 MC10E164 3.1–27 MC10H102 3.1–24 MC10170 3.1–30 MC10E1651 3.1–14 MC10H103 3.1–24 MC10171 3.1–16 MC10E1652 3.1–14 MC10H104 3.1–21 MC10172 3.1–17 MC10E166 3.1–14 MC10H105 3.1–23 MC10173 3.1–29 MC10E167 3.1–18 MC10H106 3.1–24 MC10174 3.1–28 MC10E171 3.1–27 MC10H107 3.1–23 MC10175 3.1–27 MC10E175 3.1–26 MC10H109 3.1–23 MC10176 3.1–19 MC10E193 3.1–30 MC10H113 3.1–23 MC10177 3.1–35 MC10E195 3.1–31 MC10H115 3.1–31 MC10178 3.1–15 MC10E196 3.1–31 MC10H116 3.1–32 MC10180 3.1–9 MC10E197 3.1–27 MC10H117 3.1–23 MC10181 3.1–9 MC10E211 3.1–12 MC10H118 3.1–23 MC10186 3.1–19 MC10E212 3.1–32 MC10H119 3.1–22 MC10188 3.1–25 MC10E241 3.1–33 MC10H121 3.1–22 MC10189 3.1–25 MC10E256 3.1–26 MC10H123 3.1–12 MC10190 3.1–35 MC10E336 3.1–10 MC10H124 3.1–35 MC10191 3.1–35 MC10E337 3.1–10 MC10H125 3.1–35 MC10192 3.1–12 MC10E404 3.1–23 MC10H130 3.1–26 MC10193 3.1–17 MC10E411 3.1–13 MC10H131 3.1–19 MC10195 3.1–25 MC10E416 3.1–31 MC10H135 3.1–19 MC10197 3.1–21 MC10E431 3.1–18 MC10H136 3.1–16 MC10198 3.1–29 MC10E445 3.1–14 MC10H141 3.1–33 MC10210 3.1–24 MC10E446 3.1–14 MC10H145 3.1–32 MC10211 3.1–24 MC10E451 3.1–18 MC10H158 3.1–29 MC10212 3.1–23 MC10E452 3.1–18 MC10H159 3.1–29 MC10216 3.1–31 MC10E457 3.1–29 MC10H16 3.1–14 MC10231 3.1–19 MC10EL01 3.1–22 MC10H160 3.1–30 MC10804 3.1–34 MC10EL04 3.1–22 MC10H161 3.1–16 MC10805 3.1–34 MC10EL05 3.1–22 MC10H162 3.1–16 MC10E016 3.1–15 MC10EL07 3.1–22 MC10H164 3.1–27 MC10E101 3.1–23 MC10EL11 3.1–12 MC10H165 3.1–18 MC10E104 3.1–23 MC10EL12 3.1–25 MC10H166 3.1–14 MC10E107 3.1–23 MC10EL15 3.1–12 MC10H171 3.1–17 MC10E111 3.1–12 MC10EL16 3.1–31 MC10H172 3.1–17 MC10E112 3.1–25 MC10EL31 3.1–18 MC10H173 3.1–28 MC10E116 3.1–31 MC10EL32 3.1–17 MC10H174 3.1–28 MC10E122 3.1–25 MC10EL33 3.1–17 MC10H175 3.1–27 MC10E131 3.1–18 MC10EL34 3.1–13 MC10H176 3.1–19 MC10E136 3.1–14 MC10EL35 3.1–19 MC10H179 3.1–9 MC10E137 3.1–15 MC10EL51 3.1–18 MC10H180 3.1–9 Motorola Master Selection Guide 3.1–37 TTL, ECL, CMOS and Special Logic Circuits Device Index MC10H181 3.1–9 MC12022TSA 3.1–30 MC12430 3.1–13 MC10H186 3.1–19 MC12022TSB 3.1–30 MC12439 3.1–13 MC10H188 3.1–25 MC12022TVA 3.1–30 MC14001B 3.1–24 MC10H189 3.1–25 MC12022TVB 3.1–30 MC14001UB 3.1–24 MC10H209 3.1–23 MC12023 3.1–31 MC14002B 3.1–24 MC10H210 3.1–24 MC12025 3.1–31 MC14002UB 3.1–24 MC10H211 3.1–24 MC12026A 3.1–30 MC14006B 3.1–32 MC10H330 3.1–12 MC12026B 3.1–30 MC14007UB 3.1–25 MC10H332 3.1–10 MC12028A 3.1–30 MC14008B 3.1–9 MC10H334 3.1–12 MC12028B 3.1–30 MC14011B 3.1–22 MC10H350 3.1–35 MC12031A 3.1–31 MC14011UB 3.1–22 MC10H351 3.1–35 MC12031B 3.1–31 MC14012B 3.1–21 MC10H352 3.1–35 MC12032A 3.1–31 MC14012UB 3.1–21 MC10H423 3.1–12 MC12032B 3.1–31 MC14013B 3.1–18 MC10H424 3.1–35 MC12033A 3.1–31 MC14014B 3.1–33 MC10H600 3.1–34 MC12033B 3.1–31 MC14015B 3.1–33 MC10H601 3.1–34 MC12034A 3.1–31 MC14016B 3.1–29 MC10H602 3.1–34 MC12034B 3.1–31 MC14017B 3.1–15 MC10H603 3.1–34 MC12036A 3.1–30 MC14018B 3.1–15 MC10H604 3.1–35 MC12036B 3.1–30 MC14020B 3.1–14 MC10H605 3.1–35 MC12038A 3.1–30 MC14021B 3.1–33 MC10H606 3.1–35 MC12040 3.1–17 MC14022B 3.1–15 MC10H607 3.1–35 MC12052A 3.1–30 MC14023B 3.1–22 MC10H640 3.1–13 MC12053A 3.1–30 MC14023UB 3.1–22 MC10H641 3.1–13 MC12054A 3.1–31 MC14024B 3.1–14 MC10H642 3.1–13 MC12058 3.1–30 MC14025B 3.1–24 MC10H643 3.1–13 MC12061 3.1–29 MC14025UB 3.1–24 MC10H644 3.1–13 MC12066 3.1–30 MC14027B 3.1–19 MC10H645 3.1–13 MC12073 3.1–30 MC14028B 3.1–16 MC10H646 3.1–13 MC12074 3.1–30 MC14029B 3.1–15 MC10H660 3.1–27 MC12075 3.1–30 MC14035B 3.1–33 MC10H680 3.1–34 MC12076 3.1–31 MC14038B 3.1–9 MC10H681 3.1–34 MC12078 3.1–31 MC14040B 3.1–14 MC10SX1125 3.1–9 MC12079 3.1–31 MC14042B 3.1–27 MC10SX1130 3.1–13, 3.1–17 MC12080 3.1–30 MC14043B 3.1–27 MC10SX1189 3.1–13 MC12083 3.1–30 MC14044B 3.1–27 MC12002 3.1–17 MC12089 3.1–31 MC14046B 3.1–30 MC12009 3.1–31 MC12090 3.1–31 MC14049B 3.1–25 MC12011 3.1–31 MC12093 3.1–30 MC14049UB 3.1–25 MC12013 3.1–31 MC12095 3.1–31 MC14050B 3.1–25 MC12014 3.1–15 MC12098 3.1–31 MC14051B 3.1–27 MC12015 3.1–31 MC12100 3.1–29 MC14052B 3.1–28 MC12016 3.1–31 MC12101 3.1–29 MC14053B 3.1–29 MC12017 3.1–31 MC12147 3.1–35 MC14060B 3.1–14 MC12018 3.1–31 MC12148 3.1–29 MC14066B 3.1–29 MC12019 3.1–31 MC12149 3.1–35 MC14067B 3.1–27 MC12022A 3.1–30 MC12179 3.1–34 MC14068B 3.1–21 MC12022B 3.1–30 MC12181 3.1–34 MC14069UB 3.1–25 MC12022LVA 3.1–30 MC12202 3.1–34 MC14070B 3.1–23 MC12022LVB 3.1–30 MC12206 3.1–34 MC14071B 3.1–24 MC12022SLA 3.1–30 MC12210 3.1–34 MC14072B 3.1–24 MC12022SLB 3.1–30 MC12429 3.1–13 MC14073B 3.1–22 TTL, ECL, CMOS and Special Logic Circuits 3.1–38 Motorola Master Selection Guide Device Index MC14075B 3.1–25 MC14549B 3.1–34 MC54HC164 3.1–33 MC14076B 3.1–21 MC14551B 3.1–28 MC54HC164A 3.1–33 MC14077B 3.1–23 MC14553B 3.1–14 MC54HC165 3.1–33 MC14078B 3.1–24 MC14555B 3.1–17 MC54HC174A 3.1–19 MC14081B 3.1–21 MC14556B 3.1–17 MC54HC175 3.1–21 MC14082B 3.1–21 MC14557B 3.1–32 MC54HC175A 3.1–21 MC14093B 3.1–32 MC14558B 3.1–17 MC54HC240A 3.1–11 MC14094B 3.1–33 MC14559B 3.1–34 MC54HC241A 3.1–11 MC14099B 3.1–26 MC14560B 3.1–9 MC54HC244A 3.1–12 MC14106B 3.1–32 MC14561B 3.1–9 MC54HC245A 3.1–12 MC14161B 3.1–14 MC14562B 3.1–32 MC54HC251 3.1–27 MC14163B 3.1–14 MC14566B 3.1–15 MC54HC259 3.1–16 MC14174B 3.1–19 MC14568B 3.1–15 MC54HC27 3.1–24 MC14175B 3.1–21 MC14569B 3.1–15 MC54HC273A 3.1–20 MC14194B 3.1–33 MC14572UB 3.1–23 MC54HC32A 3.1–24 MC14415 3.1–30 MC14580B 3.1–32 MC54HC354 3.1–27 MC14490 3.1–9 MC14583B 3.1–32 MC54HC365 3.1–10 MC14500B 3.1–25 MC14584B 3.1–32 MC54HC366 3.1–10 MC14501UB 3.1–23 MC14585B 3.1–14 MC54HC367 3.1–10 MC14502B 3.1–25 MC14598B 3.1–26 MC54HC373A 3.1–27 MC14503B 3.1–10 MC14599B 3.1–26 MC54HC374A 3.1–20 MC14504B 3.1–35 MC1648 3.1–30 MC54HC390 3.1–15 MC14506UB 3.1–23 MC1650 3.1–14 MC54HC393 3.1–15 MC14508B 3.1–26 MC1651 3.1–14 MC54HC4016 3.1–29 MC14510B 3.1–15 MC1658 3.1–29 MC54HC4040A 3.1–14 MC14511B 3.1–17 MC1660 3.1–23 MC54HC4049 3.1–25 MC14512B 3.1–27 MC1662 3.1–24 MC54HC4050 3.1–25 MC14513B 3.1–17 MC1670 3.1–20 MC54HC4051 3.1–27 MC14514B 3.1–16 MC1672 3.1–23 MC54HC4053 3.1–29 MC14515B 3.1–16 MC1692 3.1–31 MC54HC4060 3.1–14 MC14516B 3.1–15 MC4016 3.1–16 MC54HC4060A 3.1–14 MC14517B 3.1–34 MC4018 3.1–16 MC54HC4066 3.1–29 MC14518B 3.1–15 MC4024 3.1–29 MC54HC4351 3.1–27 MC14519B 3.1–22 MC4044 3.1–17 MC54HC4353 3.1–29 MC14520B 3.1–15 MC4316 3.1–16 MC54HC4538A 3.1–29 MC14521B 3.1–30 MC4324 3.1–29 MC54HC533A 3.1–27 MC14522B 3.1–15 MC4344 3.1–17 MC54HC534A 3.1–20 MC14526B 3.1–15 MC54HC00A 3.1–22 MC54HC540A 3.1–11 MC14527B 3.1–9 MC54HC02A 3.1–24 MC54HC541A 3.1–11 MC14528B 3.1–29 MC54HC04A 3.1–25 MC54HC563A 3.1–27 MC14529B 3.1–28 MC54HC08A 3.1–21 MC54HC573A 3.1–27 MC14530B 3.1–23 MC54HC132A 3.1–32 MC54HC574A 3.1–20 MC14531B 3.1–30 MC54HC138A 3.1–16 MC54HC589 3.1–33 MC14532B 3.1–17 MC54HC139A 3.1–17 MC54HC589A 3.1–33 MC14534B 3.1–14 MC54HC14A 3.1–32 MC54HC595A 3.1–33 MC14536B 3.1–30 MC54HC154 3.1–16 MC54HC597 3.1–33 MC14538B 3.1–29 MC54HC157A 3.1–28 MC54HC597A 3.1–33 MC14539B 3.1–28 MC54HC158 3.1–28 MC54HC640A 3.1–11 MC14541B 3.1–30 MC54HC160 3.1–15 MC54HC646 3.1–12 MC14543B 3.1–17 MC54HC161A 3.1–15 MC54HC688 3.1–14 MC14544B 3.1–17 MC54HC162 3.1–15 MC54HC74A 3.1–19 MC14547B 3.1–17 MC54HC163A 3.1–15 MC54HC86 3.1–23 Motorola Master Selection Guide 3.1–39 TTL, ECL, CMOS and Special Logic Circuits Device Index MC54HC86A 3.1–23 MC74AC163 3.1–16 MC74ACT10 3.1–22 MC54HCT00A 3.1–22 MC74AC174 3.1–19 MC74ACT109 3.1–19 MC54HCT08A 3.1–21 MC74AC175 3.1–20 MC74ACT11 3.1–22 MC54HCT14A 3.1–32 MC74AC190 3.1–16 MC74ACT112 3.1–19 MC54HCT161A 3.1–15 MC74AC194 3.1–33 MC74ACT113 3.1–19 MC54HCT163A 3.1–15 MC74AC20 3.1–21 MC74ACT125 3.1–12 MC54HCT241A 3.1–11 MC74AC240 3.1–11 MC74ACT126 3.1–12 MC54HCT244A 3.1–11 MC74AC241 3.1–11 MC74ACT132 3.1–32 MC54HCT245A 3.1–10 MC74AC244 3.1–11 MC74ACT138 3.1–16 MC54HCT32A 3.1–24 MC74AC245 3.1–10 MC74ACT139 3.1–17 MC54HCT373A 3.1–26 MC74AC251 3.1–27 MC74ACT14 3.1–32 MC54HCT374A 3.1–20 MC74AC253 3.1–28 MC74ACT151 3.1–27 MC54HCT574A 3.1–20 MC74AC256 3.1–26 MC74ACT153 3.1–28 MC660 3.1–18 MC74AC257 3.1–28 MC74ACT157 3.1–29 MC661 3.1–18 MC74AC258 3.1–28 MC74ACT158 3.1–29 MC662 3.1–18 MC74AC259 3.1–26 MC74ACT160 3.1–16 MC663 3.1–19 MC74AC273 3.1–20 MC74ACT161 3.1–16 MC664 3.1–20 MC74AC299 3.1–33 MC74ACT162 3.1–16 MC667 3.1–29 MC74AC32 3.1–24 MC74ACT163 3.1–16 MC668 3.1–25 MC74AC323 3.1–33 MC74ACT174 3.1–19 MC669 3.1–18 MC74AC350 3.1–33 MC74ACT175 3.1–20 MC670 3.1–25 MC74AC352 3.1–28 MC74ACT194 3.1–33 MC671 3.1–25 MC74AC353 3.1–28 MC74ACT20 3.1–21 MC672 3.1–25 MC74AC373 3.1–26 MC74ACT240 3.1–11 MC677 3.1–25 MC74AC374 3.1–20 MC74ACT241 3.1–11 MC678 3.1–25 MC74AC377 3.1–20 MC74ACT244 3.1–11 MC68150*33 3.1–10 MC74AC378 3.1–18 MC74ACT245 3.1–10 MC68150*40 3.1–10 MC74AC4020 3.1–14 MC74ACT251 3.1–27 MC68194 3.1–12 MC74AC4040 3.1–14 MC74ACT253 3.1–28 MC74AC00 3.1–22 MC74AC533 3.1–26 MC74ACT256 3.1–26 MC74AC02 3.1–24 MC74AC534 3.1–20 MC74ACT257 3.1–28 MC74AC04 3.1–25 MC74AC540 3.1–11 MC74ACT258 3.1–28 MC74AC05 3.1–25 MC74AC541 3.1–11 MC74ACT259 3.1–26 MC74AC08 3.1–21 MC74AC563 3.1–26 MC74ACT273 3.1–20 MC74AC10 3.1–22 MC74AC564 3.1–20 MC74ACT299 3.1–33 MC74AC109 3.1–19 MC74AC573 3.1–26 MC74ACT32 3.1–24 MC74AC11 3.1–22 MC74AC574 3.1–20 MC74ACT323 3.1–33 MC74AC112 3.1–19 MC74AC620 3.1–10 MC74ACT350 3.1–33 MC74AC113 3.1–19 MC74AC623 3.1–10 MC74ACT352 3.1–28 MC74AC125 3.1–12 MC74AC640 3.1–10 MC74ACT353 3.1–28 MC74AC126 3.1–12 MC74AC643 3.1–10 MC74ACT373 3.1–26 MC74AC132 3.1–32 MC74AC646 3.1–11 MC74ACT374 3.1–20 MC74AC138 3.1–16 MC74AC648 3.1–11 MC74ACT377 3.1–20 MC74AC139 3.1–17 MC74AC652 3.1–11 MC74ACT378 3.1–18 MC74AC14 3.1–32 MC74AC74 3.1–18 MC74ACT521 3.1–14 MC74AC151 3.1–27 MC74AC810 3.1–23 MC74ACT533 3.1–26 MC74AC153 3.1–28 MC74AC86 3.1–23 MC74ACT534 3.1–20 MC74AC157 3.1–29 MC74ACT00 3.1–22 MC74ACT540 3.1–11 MC74AC158 3.1–29 MC74ACT02 3.1–24 MC74ACT541 3.1–11 MC74AC160 3.1–16 MC74ACT04 3.1–25 MC74ACT563 3.1–26 MC74AC161 3.1–16 MC74ACT05 3.1–25 MC74ACT564 3.1–20 MC74AC162 3.1–16 MC74ACT08 3.1–21 MC74ACT573 3.1–26 TTL, ECL, CMOS and Special Logic Circuits 3.1–40 Motorola Master Selection Guide Device Index MC74ACT574 3.1–20 MC74F243 3.1–12 MC74F657A 3.1–10 MC74ACT620 3.1–10 MC74F244 3.1–11 MC74F657B 3.1–10 MC74ACT623 3.1–10 MC74F245 3.1–10 MC74F74 3.1–19 MC74ACT640 3.1–10 MC74F251 3.1–27 MC74F779 3.1–15 MC74ACT643 3.1–10 MC74F253 3.1–28 MC74F803 3.1–13 MC74ACT646 3.1–11 MC74F256 3.1–26 MC74F823 3.1–10 MC74ACT648 3.1–11 MC74F257A 3.1–29 MC74F827 3.1–10 MC74ACT652 3.1–11 MC74F258A 3.1–29 MC74F828 3.1–10 MC74ACT74 3.1–18 MC74F259 3.1–26 MC74F85 3.1–14 MC74ACT810 3.1–23 MC74F269 3.1–15 MC74F86 3.1–23 MC74ACT86 3.1–23 MC74F280 3.1–30 MC74HC00A 3.1–22 MC74F00 3.1–22 MC74F283 3.1–9 MC74HC02A 3.1–24 MC74F02 3.1–24 MC74F299 3.1–33 MC74HC03A 3.1–22 MC74F04 3.1–25 MC74F32 3.1–24 MC74HC04A 3.1–25 MC74F08 3.1–21 MC74F323 3.1–33 MC74HC08A 3.1–21 MC74F10 3.1–22 MC74F350 3.1–33 MC74HC10 3.1–22 MC74F109 3.1–19 MC74F352 3.1–28 MC74HC107 3.1–19 MC74F11 3.1–22 MC74F353 3.1–28 MC74HC109 3.1–19 MC74F112 3.1–19 MC74F365 3.1–10 MC74HC11 3.1–22 MC74F1245 3.1–10 MC74F366 3.1–10 MC74HC112 3.1–19 MC74F125 3.1–12 MC74F367 3.1–10 MC74HC125A 3.1–12 MC74F126 3.1–12 MC74F368 3.1–10 MC74HC132A 3.1–32 MC74F13 3.1–32 MC74F37 3.1–21 MC74HC133 3.1–21 MC74F132 3.1–32 MC74F373 3.1–26 MC74HC137 3.1–16 MC74F138 3.1–16 MC74F374 3.1–20 MC74HC138A 3.1–16 MC74F139 3.1–17 MC74F377 3.1–20 MC74HC139A 3.1–17 MC74F14 3.1–32 MC74F378 3.1–32 MC74HC147 3.1–18 MC74F148 3.1–18 MC74F379 3.1–21 MC74HC14A 3.1–32 MC74F151 3.1–27 MC74F38 3.1–22 MC74HC151 3.1–27 MC74F153 3.1–28 MC74F381 3.1–9 MC74HC153 3.1–28 MC74F157A 3.1–28 MC74F382 3.1–9 MC74HC154 3.1–16 MC74F158A 3.1–28 MC74F3893A 3.1–34 MC74HC157A 3.1–28 MC74F160A 3.1–15 MC74F398 3.1–29 MC74HC158 3.1–28 MC74F161A 3.1–15 MC74F399 3.1–29 MC74HC158A 3.1–28 MC74F162A 3.1–15 MC74F40 3.1–21 MC74HC160 3.1–15 MC74F163A 3.1–15 MC74F51 3.1–23 MC74HC161A 3.1–15 MC74F164 3.1–33 MC74F521 3.1–14 MC74HC162 3.1–15 MC74F168 3.1–14 MC74F533 3.1–26 MC74HC163 3.1–15 MC74F169 3.1–14 MC74F534 3.1–20 MC74HC164 3.1–33 MC74F174 3.1–19 MC74F537 3.1–16 MC74HC164A 3.1–33 MC74F175 3.1–20 MC74F538 3.1–16 MC74HC165 3.1–33 MC74F1803 3.1–13 MC74F539 3.1–16 MC74HC173 3.1–21 MC74F181 3.1–9 MC74F544 3.1–11 MC74HC174A 3.1–19 MC74F182 3.1–9 MC74F568 3.1–14 MC74HC175 3.1–21 MC74F194 3.1–33 MC74F569 3.1–14 MC74HC175A 3.1–21 MC74F195 3.1–33 MC74F574 3.1–20 MC74HC194 3.1–33 MC74F20 3.1–21 MC74F579 3.1–15 MC74HC195 3.1–33 MC74F21 3.1–21 MC74F620 3.1–11 MC74HC20 3.1–21 MC74F2245 3.1–34 MC74F623 3.1–11 MC74HC237 3.1–16 MC74F240 3.1–11 MC74F64 3.1–22 MC74HC240A 3.1–11 MC74F241 3.1–11 MC74F640 3.1–11 MC74HC241A 3.1–11 MC74F242 3.1–12 MC74F646 3.1–11 MC74HC242 3.1–12 Motorola Master Selection Guide 3.1–41 TTL, ECL, CMOS and Special Logic Circuits Device Index MC74HC244A 3.1–12 MC74HC541A 3.1–11 MC74LCX157 MC74HC245A 3.1–12 MC74HC563A 3.1–27 MC74LCX16240A MC74HC251 3.1–27 MC74HC564A 3.1–20 MC74LCX16244 3.1–9 MC74HC253 3.1–28 MC74HC573A 3.1–27 MC74LCX16245 3.1–34 MC74HC257 3.1–28 MC74HC574A 3.1–20 MC74LCX16373 3.1–26 MC74HC259 3.1–16 MC74HC58 3.1–22 MC74LCX373 3.1–26 MC74HC27 3.1–24 MC74HC589 3.1–33 MC74LCX16374 3.1–20 MC74HC273A 3.1–20 MC74HC589A 3.1–33 MC74LCX16500 3.1–34 MC74HC280 3.1–30 MC74HC595A 3.1–33 MC74LCX16501 3.1–34 MC74HC299 3.1–33 MC74HC597 3.1–33 MC74LCX16543A 3.1–34 MC74HC30 3.1–21 MC74HC597A 3.1–33 MC74LCX240 MC74HC32A 3.1–24 MC74HC640A 3.1–11 MC74LCX244 3.1–9 MC74HC354 3.1–27 MC74HC646 3.1–12 MC74LCX245 3.1–34 MC74HC365 3.1–10 MC74HC688 3.1–14 MC74LCX2952 3.1–34 MC74HC366 3.1–10 MC74HC7266 3.1–23 MC74LCX32 3.1–24 MC74HC367 3.1–10 MC74HC7266A 3.1–23 MC74LCX374 3.1–20 MC74HC368 3.1–10 MC74HC73 3.1–19 MC74LCX540 3.1–9 MC74HC373A 3.1–27 MC74HC74A 3.1–19 MC74LCX541 3.1–9 MC74HC374A 3.1–20 MC74HC75 3.1–26 MC74LCX573 3.1–26 MC74HC390 3.1–15 MC74HC76 3.1–19 MC74LCX574 3.1–20 MC74HC393 3.1–15 MC74HC85 3.1–14 MC74LCX652 3.1–34 MC74HC4002 3.1–24 MC74HC86 3.1–23 MC74LCX86 3.1–23 MC74HC4016 3.1–29 MC74HC86A 3.1–23 MC74LVQ00 3.1–21 MC74HC4017 3.1–15 MC74HCT00A 3.1–22 MC74LVQ04 3.1–25 MC74HC4020A 3.1–14 MC74HCT04A 3.1–25 MC74LVQ125 3.1–10 MC74HC4024 3.1–29 MC74HCT08A 3.1–21 MC74LVQ138 3.1–17 MC74HC4040A 3.1–14 MC74HCT138A 3.1–16 MC74LVQ240 3.1–10 MC74HC4046A 3.1–35 MC74HCT14A 3.1–32 MC74LVQ244 3.1–9 MC74HC4049 3.1–25 MC74HCT157A 3.1–28 MC74LVQ245 3.1–34 MC74HC4050 3.1–25 MC74HCT161A 3.1–15 MC74LVQ32 3.1–24 MC74HC4051 3.1–27 MC74HCT163A 3.1–15 MC74LVQ373 3.1–26 MC74HC4052 3.1–28 MC74HCT174A 3.1–19 MC74LVQ374 3.1–20 MC74HC4053 3.1–29 MC74HCT240A 3.1–11 MC74LVQ541 3.1–9 MC74HC4060 3.1–14 MC74HCT241A 3.1–11 MC74LVQ573 3.1–26 MC74HC4060A 3.1–14 MC74HCT244A 3.1–11 MC74LVQ574 3.1–20 MC74HC4066 3.1–29 MC74HCT245A 3.1–10 MC74LVQ646 3.1–34 MC74HC4075 3.1–25 MC74HCT273A 3.1–20 MC74LVQ652 3.1–34 MC74HC4078 3.1–23 MC74HCT32A 3.1–24 MC74LVX4245 3.1–34 MC74HC42 3.1–16 MC74HCT373A 3.1–26 MC74VHC02 3.1–24 MC74HC4316 3.1–29 MC74HCT374A 3.1–20 MC74VHC04 3.1–25 MC74HC4351 3.1–27 MC74HCT541A 3.1–11 MC74VHC08 3.1–21 MC74HC4353 3.1–29 MC74HCT573A 3.1–27 MC74HC126A 3.1–12 MC74HC4511 3.1–17 MC74HCT574A 3.1–20 MC74VHC125 3.1–12 MC74HC4514 3.1–16 MC74HCT74A 3.1–19 MC74VHC138 3.1–16 MC74HC4538A 3.1–29 MC74HCU04 3.1–25 MC74VHC14 3.1–32 MC74HC4851A 3.1–27 MC74HCU04A 3.1–25 MC74VHC157 3.1–28 MC74HC4852A 3.1–27 MC74LCX00 3.1–21 MC74VHC244 3.1–12 MC74HC4853A 3.1–27 MC74LCX02 3.1–24 MC74VHC245 3.1–12 MC74HC51 3.1–22 MC74LCX04 3.1–25 MC74VHC32 3.1–24 MC74HC533A 3.1–27 MC74LCX08 3.1–21 MC74VHC373 3.1–27 MC74HC534A 3.1–20 MC74LCX125 3.1–9 MC74VHC374 3.1–20 MC74HC540A 3.1–11 MC74LCX138 3.1–17 MC74VHC541 3.1–11 TTL, ECL, CMOS and Special Logic Circuits 3.1–42 3.1–28 3.1–9 3.1–9 Motorola Master Selection Guide Device Index MC74VHC573 3.1–27 MPA1765 3.1–32 SN54LS147 3.1–17 MC74VHC574 3.1–20 MPC903 3.1–12 SN54LS148 3.1–18 MC74VHC595 3.1–33 MPC904 3.1–12 SN54LS15 3.1–22 MC74VHC74 3.1–19 MPC905 3.1–12 SN54LS151 3.1–27 MC830 3.1–21 MPC911 3.1–13 SN54LS153 3.1–28 MC832 3.1–9 MPC930 3.1–13 SN54LS155 3.1–16 MC836 3.1–25 MPC931 3.1–13 SN54LS156 3.1–16 MC837 3.1–25 MPC946 3.1–13 SN54LS157 3.1–28 MC840 3.1–25 MPC947 3.1–12 SN54LS158 3.1–28 MC844 3.1–18 MPC948 3.1–12 SN54LS160A 3.1–14 MC845 3.1–18 MPC948L 3.1–12 SN54LS161A 3.1–14 MC846 3.1–22 MPC949 3.1–13 SN54LS162A 3.1–14 MC88913 3.1–13 MPC950 3.1–13 SN54LS163A 3.1–14 MC88914 3.1–13 MPC951 3.1–13 SN54LS164 3.1–33 MC88915*55 3.1–13 MPC952 3.1–13 SN54LS165 3.1–33 MC88915*70 3.1–13 MPC956 3.1–13 SN54LS166 3.1–33 MC88915T*100 3.1–13 MPC970 3.1–13 SN54LS168 3.1–15 MC88915T*133 3.1–13 MPC972 3.1–13 SN54LS169 3.1–15 MC88915T*160 3.1–13 MPC973 3.1–13 SN54LS170 3.1–32 MC88915T*55 3.1–13 MPC974 3.1–13 SN54LS173A 3.1–18 MC88915T*70 3.1–13 MPC980 3.1–13 SN54LS174 3.1–19 MC88916*70 3.1–13 MPC990 3.1–13 SN54LS175 3.1–21 MC88916*80 3.1–13 MPC991 3.1–13 SN54LS190 3.1–15 MC88920 3.1–13 MPC992 3.1–13 SN54LS191 3.1–15 MC88921 3.1–13 SN54LS00 3.1–22 SN54LS192 3.1–15 MC88LV926 3.1–13 SN54LS01 3.1–22 SN54LS193 3.1–15 MC88PL117 3.1–13 SN54LS02 3.1–24 SN54LS194A 3.1–33 MC936 3.1–25 SN54LS03 3.1–22 SN54LS195A 3.1–34 MC937 3.1–25 SN54LS04 3.1–25 SN54LS196 3.1–14 MC944 3.1–18 SN54LS05 3.1–25 SN54LS197 3.1–14 MC945 3.1–18 SN54LS08 3.1–21 SN54LS20 3.1–21 MC946 3.1–22 SN54LS09 3.1–21 SN54LS21 3.1–21 MC951 3.1–29 SN54LS10 3.1–22 SN54LS22 3.1–21 MC952 3.1–19 SN54LS107A 3.1–19 SN54LS221 3.1–29 MC953 3.1–19 SN54LS109A 3.1–19 SN54LS240 3.1–11 MCCS142233 3.1–32 SN54LS11 3.1–22 SN54LS241 3.1–11 MCCS142235 3.1–32 SN54LS112A 3.1–19 SN54LS242 3.1–12 MCCS142236 3.1–32 SN54LS113A 3.1–19 SN54LS243 3.1–12 MCCS142237 3.1–32 SN54LS114A 3.1–19 SN54LS244 3.1–11 MCCS142238 3.1–32 SN54LS12 3.1–22 SN54LS245 3.1–11 MCCS142239 3.1–32 SN54LS122 3.1–29 SN54LS247 3.1–17 MCH12140 3.1–17 SN54LS123 3.1–29 SN54LS248 3.1–17 MCK12140 3.1–17 SN54LS125A 3.1–12 SN54LS249 3.1–17 MCM10143 3.1–32 SN54LS126A 3.1–12 SN54LS251 3.1–27 MCM10145 3.1–32 SN54LS13 3.1–32 SN54LS253 3.1–28 MCM10146 3.1–31 SN54LS132 3.1–32 SN54LS256 3.1–26 MCM10152 3.1–31 SN54LS133 3.1–21 SN54LS257B 3.1–28 MPA1016 3.1–18 SN54LS137 3.1–16 SN54LS258B 3.1–29 MPA1036 3.1–18 SN54LS138 3.1–16 SN54LS259 3.1–26 MPA1064 3.1–18 SN54LS139 3.1–17 SN54LS26 3.1–21 MPA1100 3.1–18 SN54LS14 3.1–32 SN54LS260 3.1–24 MPA17128 3.1–32 SN54LS145 3.1–16 SN54LS266 3.1–23 Motorola Master Selection Guide 3.1–43 TTL, ECL, CMOS and Special Logic Circuits Device Index SN54LS27 3.1–24 SN54LS670 3.1–32 SN74LS148 3.1–18 SN54LS273 3.1–20 SN54LS682 3.1–14 SN74LS15 3.1–22 SN54LS279 3.1–27 SN54LS684 3.1–14 SN74LS151 3.1–27 SN54LS28 3.1–24 SN54LS688 3.1–14 SN74LS153 3.1–28 SN54LS280 3.1–30 SN54LS73A 3.1–19 SN74LS155 3.1–16 SN54LS283 3.1–9 SN54LS748 3.1–18 SN74LS156 3.1–16 SN54LS290 3.1–15 SN54LS74A 3.1–19 SN74LS157 3.1–28 SN54LS293 3.1–14 SN54LS75 3.1–26 SN74LS158 3.1–28 SN54LS298 3.1–28 SN54LS76A 3.1–19 SN74LS160A 3.1–14 SN54LS299 3.1–33 SN54LS77 3.1–26 SN74LS161A 3.1–14 SN54LS30 3.1–21 SN54LS795 3.1–10 SN74LS162A 3.1–14 SN54LS32 3.1–24 SN54LS796 3.1–10 SN74LS163A 3.1–14 SN54LS322A 3.1–33 SN54LS797 3.1–10 SN74LS164 3.1–33 SN54LS323 3.1–33 SN54LS798 3.1–10 SN74LS165 3.1–33 SN54LS33 3.1–24 SN54LS83A 3.1–9 SN74LS166 3.1–33 SN54LS348 3.1–18 SN54LS848 3.1–18 SN74LS168 3.1–15 SN54LS352 3.1–28 SN54LS85 3.1–14 SN74LS169 3.1–15 SN54LS353 3.1–28 SN54LS86 3.1–23 SN74LS170 3.1–32 SN54LS365A 3.1–10 SN54LS90 3.1–15 SN74LS173A 3.1–18 SN54LS366A 3.1–10 SN54LS92 3.1–15 SN74LS174 3.1–19 SN54LS367A 3.1–10 SN54LS93 3.1–14 SN74LS175 3.1–21 SN54LS368A 3.1–10 SN54LS95B 3.1–33 SN74LS190 3.1–15 SN54LS37 3.1–21 SN74LS00 3.1–22 SN74LS191 3.1–15 SN54LS373 3.1–26 SN74LS01 3.1–22 SN74LS192 3.1–15 SN54LS374 3.1–20 SN74LS02 3.1–24 SN74LS193 3.1–15 SN54LS375 3.1–26 SN74LS03 3.1–22 SN74LS194A 3.1–33 SN54LS377 3.1–20 SN74LS04 3.1–25 SN74LS195A 3.1–34 SN54LS378 3.1–19 SN74LS05 3.1–25 SN74LS196 3.1–14 SN54LS379 3.1–18 SN74LS08 3.1–21 SN74LS197 3.1–14 SN54LS38 3.1–22 SN74LS09 3.1–21 SN74LS20 3.1–21 SN54LS386 3.1–23 SN74LS10 3.1–22 SN74LS21 3.1–21 SN54LS390 3.1–15 SN74LS107A 3.1–19 SN74LS22 3.1–21 SN54LS393 3.1–15 SN74LS109A 3.1–19 SN74LS221 3.1–29 SN54LS398 3.1–29 SN74LS11 3.1–22 SN74LS240 3.1–11 SN54LS399 3.1–29 SN74LS112A 3.1–19 SN74LS241 3.1–11 SN54LS40 3.1–21 SN74LS113A 3.1–19 SN74LS242 3.1–12 SN54LS42 3.1–16 SN74LS114A 3.1–19 SN74LS243 3.1–12 SN54LS47 3.1–17 SN74LS12 3.1–22 SN74LS244 3.1–11 SN54LS48 3.1–17 SN74LS122 3.1–29 SN74LS245 3.1–11 SN54LS490 3.1–15 SN74LS123 3.1–29 SN74LS247 3.1–17 SN54LS51 3.1–23 SN74LS125A 3.1–12 SN74LS248 3.1–17 SN54LS54 3.1–22 SN74LS126A 3.1–12 SN74LS249 3.1–17 SN54LS540 3.1–11 SN74LS13 3.1–32 SN74LS251 3.1–27 SN54LS541 3.1–11 SN74LS132 3.1–32 SN74LS253 3.1–28 SN54LS55 3.1–22 SN74LS133 3.1–21 SN74LS257B 3.1–28 SN54LS569A 3.1–14 SN74LS136 3.1–23 SN74LS258B 3.1–29 SN54LS623 3.1–11 SN74LS137 3.1–16 SN74LS259 3.1–26 SN54LS640 3.1–11 SN74LS138 3.1–16 SN74LS26 3.1–21 SN54LS641 3.1–34 SN74LS139 3.1–17 SN74LS260 3.1–24 SN54LS642 3.1–34 SN74LS14 3.1–32 SN74LS266 3.1–23 SN54LS645 3.1–11 SN74LS145 3.1–16 SN74LS27 3.1–24 SN54LS669 3.1–16 SN74LS147 3.1–17 SN74LS273 3.1–20 TTL, ECL, CMOS and Special Logic Circuits 3.1–44 Motorola Master Selection Guide Device Index SN74LS279 3.1–27 SN74LS378 3.1–19 SN74LS645 3.1–11 SN74LS28 3.1–24 SN74LS379 3.1–18 SN74LS669 3.1–16 SN74LS280 3.1–30 SN74LS38 3.1–22 SN74LS670 3.1–32 SN74LS283 3.1–9 SN74LS386 3.1–23 SN74LS682 3.1–14 SN74LS290 3.1–15 SN74LS390 3.1–15 SN74LS684 3.1–14 SN74LS293 3.1–14 SN74LS393 3.1–15 SN74LS688 3.1–14 SN74LS298 3.1–28 SN74LS395 3.1–33 SN74LS73A 3.1–19 SN74LS299 3.1–33 SN74LS398 3.1–29 SN74LS748 3.1–18 SN74LS30 3.1–21 SN74LS399 3.1–29 SN74LS74A 3.1–19 SN74LS32 3.1–24 SN74LS40 3.1–21 SN74LS75 3.1–26 SN74LS322A 3.1–33 SN74LS42 3.1–16 SN74LS76A 3.1–19 SN74LS323 3.1–33 SN74LS47 3.1–17 SN74LS77 3.1–26 SN74LS33 3.1–24 SN74LS48 3.1–17 SN74LS795 3.1–10 SN74LS348 3.1–18 SN74LS490 3.1–15 SN74LS796 3.1–10 SN74LS352 3.1–28 SN74LS51 3.1–23 SN74LS797 3.1–10 SN74LS353 3.1–28 SN74LS54 3.1–22 SN74LS798 3.1–10 SN74LS365A 3.1–10 SN74LS540 3.1–11 SN74LS83A 3.1–9 SN74LS366A 3.1–10 SN74LS541 3.1–11 SN74LS848 3.1–18 SN74LS367A 3.1–10 SN74LS55 3.1–22 SN74LS85 3.1–14 SN74LS368A 3.1–10 SN74LS569A 3.1–14 SN74LS86 3.1–23 SN74LS37 3.1–21 SN74LS623 3.1–11 SN74LS90 3.1–15 SN74LS373 3.1–26 SN74LS640 3.1–11 SN74LS92 3.1–15 SN74LS374 3.1–20 SN74LS641 3.1–34 SN74LS93 3.1–14 SN74LS375 3.1–26 SN74LS642 3.1–34 SN74LS95B 3.1–33 SN74LS377 3.1–20 Motorola Master Selection Guide 3.1–45 TTL, ECL, CMOS and Special Logic Circuits Ordering Information Device Nomenclatures LS – Low Power Schottky SN VV WW XXXX Y Package Type • N for Plastic (74 Series Only) • J for Ceramic • D for 150 mil Plastic SOIC (74 Series Only) • DW for 300 mil Plastic SOIC (74 Series Only) Standard Prefix Temperature Range • 74 Series (0 to +70°C) • 54 Series (–55 to +125°C) Function Type Family • LS = Low Power Schottky FAST MC VV W XXXX Y Package Type • N for Plastic (74 Series Only) • D for 150 mil Plastic SOIC (74 Series Only) • DW for 300 mil Plastic SOIC (74 Series Only) • SD for Plastic SSOP Motorola Circuit Identifier Temperature Range • 74 Series (0 to +70°C) Function Type Family • F = FAST MECL 10K, MECL 10H/100H MC WWW XXX Package Type • P for Plastic • L for Ceramic • FN for PLCC Motorola Circuit Identifier Temperature Range • 10 = 10K (–30 to +85°C) • 10H = 10H (0 to +75°C) • 100H = 100K Compatible (0 to +85°C) TTL, ECL, CMOS and Special Logic Circuits YY Function Type 3.1–46 Motorola Master Selection Guide ECLinPS, ECLinPS Lite MC WWW XXX YYY ZZ Package Type • FN = PLCC • D = Plastic SOIC • L = Ceramic DIP • P = Plastic DIP Motorola Circuit Identifier • MC = Fully Qualified Circuit • XC = Non Reliability Qualified Function Type • YYY = 3–Digits for ECLinPS • YY= 2–Digits for ECLinPS Lite Compatibility Identifier • 10 = 10H Compatible (0 to +85°C) • 100 = 100K Compatible (0 to +85°C) ECLinPS Family Identifier • E = ECLinPS • EL = ECLinPS Lite • ELT = ECLinPS Lite Translator • LVE = Low Voltage ECLinPS • LVEL = Low Voltage ECLinPS Lite Metal Gate 14000 Series CMOS MC 14XXX YY ZZ Package and Temperature Range • CL for Ceramic –55 to +125°C • CP for Plastic –55 to +125°C • D/DW for Small Outline Package (Plastic) –55 to +125°C • DT for Plastic TSSOP Motorola Circuit Identifier Function Type Identifier (per JEDEC Standard) • B (or Blank)= Buffered Outputs • UB = Unbuffered Outputs High–Speed CMOS MC VV WWW XXXX Y Package Type • N for Plastic (74 Series Only) • J for Ceramic (54 Series Only) • D for 150 mil Plastic SOIC (74 Series Only) • DW for 300 mil Plastic SOIC (74 Series Only) • SD for Plastic SSOP • DT for Plastic TSSOP Motorola Circuit Identifier Temperature Range • 74 Series (–55 to +125°C) • 54 Series (–55 to +125°C) Function Type • XX(X) Same Function and Pin Configuration as LSTTL • 4XXX Same Function and Pin Configuration as CMOS 14000 • 7XX(X) Variation of LSTTL or CMOS 14000 Device High–Speed CMOS Specification Identifier • HC = Buffered High–Speed CMOS • HCU = Unbuffered High–Speed CMOS* • HCT = High–Speed CMOS TTL Compatible *Not Available On All Devices FACT MC WWWWW YY Package Type • N for Plastic • D for Narrow SOIC • DW for Wide SOIC • SD for Plastic SSOP • DT for Plastic TSSOP Motorola Circuit Identifier Temperature Range Family • 74AC = FACT (–40 to +85°C) • 74ACT = TTL Compatible (–40 to +85°C) Motorola Master Selection Guide XXX Function Type 3.1–47 TTL, ECL, CMOS and Special Logic Circuits Other Logic Circuits MC/MCCS WWWWWW X YY Motorola Circuit Identifier • MC = Standard Circuit Identifier • MCCS = Circuit Chip–Set Identifier ZZ Package Type • N for Plastic • D for Narrow SOIC • FN for PLCC • FJ for CLCC Function Type Option Type Option Suffix Indicator MECL III/HTL/DTL MC XXXX Y Package Type • P for Plastic • L for Ceramic • D for Narrow SOIC • FN for PLCC Motorola Circuit Identifier Function Type LCX Products MC 74 LCX YYYYY ZZ Package Type • D for Plastic Narrow JEDEC SOIC • DW for Plastic Wide JEDEC SOIC • M for Plastic EIAJ SOIC • SD for Plastic SSOP • DT for Plastic TSSOP Motorola Circuit Identifier Temperature Range • 74 = –40 to +85°C Function Type Family Identifier • LCX = 5V–Tolerant Low–Voltage CMOS LVQ Products MC 74 LVQ YYYY Package Type • D for Plastic Narrow JEDEC SOIC • DW for Plastic Wide JEDEC SOIC • M for Plastic EIAJ SOIC • SD for Plastic SSOP • DT for Plastic TSSOP Motorola Circuit Identifier Temperature Range • 74 = –40 to +85°C Function Type Family Identifier • LVQ =Low–Voltage Quiet CMOS TTL, ECL, CMOS and Special Logic Circuits ZZ 3.1–48 Motorola Master Selection Guide Motorola Programmable Arrays (MPA) FPGA Nomenclature MPA1 XXX YY Z I Temperature Grade • Blank = Commercial • I = Industrial Motorola Programmable Array (First Series) Circuit Identifier Speed Grade Package Type • FN = 84 PLCC • DD = 128 PQFP • DH = 160 PQFP • DK = 208 PQFP • HI = 181 CPGA • KE = 224 CPGA • HV = 299 CPGA • BG = 256 PBGA Number of Core Cells Physical Number of Cells in 100’s • 016 = 1,600 Cells • 036 = 3,600 Cells • 064 = 6,400 Cells • 100 = 10,000 Cells EPROM/EEPROM Nomenclature MPA17 C XXX YY I Temperature Grade • Blank = Commercial • I = Industrial Motorola EPROM/EEPROM Circuit Identifier PROM Type • Blank = EPROM • C = EEPROM Package Type • D = SOIC • P = PDIP • FN = PLCC Number of Memory Bits (in K) Motorola Master Selection Guide 3.1–49 TTL, ECL, CMOS and Special Logic Circuits Case Outlines 8–Pin Packages P SUFFIX PLASTIC DIP PACKAGE CASE 626–05 ISSUE K 8 5 –B– 1 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4 F –A– NOTE 2 L DIM A B C D F G H J K L M N C J –T– N SEATING PLANE D M K G H 0.13 (0.005) T A M M B M MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–05 ISSUE S D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 8 5 0.25 H E M B M 1 4 h B e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A TTL, ECL, CMOS and Special Logic Circuits S DIM A A1 B C D E e H h L q 3.1–50 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ Motorola Master Selection Guide 8–Pin Packages SD SUFFIX PLASTIC SSOP PACKAGE CASE 940–03 ISSUE B 8X K REF 0.12 (0.005) 0.25 (0.010) T U M S V N S M 8 L/2 N 5 F B L DETAIL E PIN 1 IDENT 1 ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ 4 K –U– A –V– 0.20 (0.008) M T U J J1 K1 S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. SECTION N–N 0.076 (0.003) –T– SEATING PLANE –W– C D DETAIL E H G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.87 3.13 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.113 0.123 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.023 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ 14–Pin Packages L,J SUFFIX CERAMIC DIP PACKAGE CASE 632–08 ISSUE Y –A– 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 9 –B– 1 7 C –T– L K SEATING PLANE F G D N M J 14 PL 0.25 (0.010) Motorola Master Selection Guide M T A S 14 PL 0.25 (0.010) 3.1–51 M T B S DIM A B C D F G J K L M N INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01 TTL, ECL, CMOS and Special Logic Circuits 14–Pin Packages P,N SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE M 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L N C –T– SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 ––– 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 ––– 10_ 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F –T– SEATING PLANE D 14 PL 0.25 (0.010) M K M T B TTL, ECL, CMOS and Special Logic Circuits S A S 3.1–52 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola Master Selection Guide 14–Pin Packages M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965–01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 M_ E HE L 7 1 DETAIL P Z D A e DIM A A1 b c D E e HE 0.50 LE M Q1 Z VIEW P c A1 b 0.13 (0.005) M 0.10 (0.004) MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ––– 1.42 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ––– 0.056 SD SUFFIX PLASTIC SSOP PACKAGE CASE 940A–03 ISSUE B 14X K REF 0.12 (0.005) T U M S V S 0.25 (0.010) N 14 L/2 8 M B L N F PIN 1 IDENT 1 7 DETAIL E –U– A –V– 0.20 (0.008) M T U K J S ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ J1 K1 SECTION N–N 0.076 (0.003) –T– SEATING PLANE –W– C D G H Motorola Master Selection Guide DETAIL E 3.1–53 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.07 6.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 1.08 1.22 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.238 0.249 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.042 0.048 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ TTL, ECL, CMOS and Special Logic Circuits 14–Pin Packages DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G–01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A –V– ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE H G D DIM A B C D F G H J J1 K K1 L M DETAIL E MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 16–Pin Packages L,J SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L –T– K N SEATING PLANE M E F J G D 0.25 (0.010) 16 PL 0.25 (0.010) 16 PL M T A TTL, ECL, CMOS and Special Logic Circuits S 3.1–54 M T B S DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 Motorola Master Selection Guide 16–Pin Packages P,N SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) Motorola Master Selection Guide M T B S A S 3.1–55 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 TTL, ECL, CMOS and Special Logic Circuits 16–Pin Packages DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751G–02 ISSUE A –A– 16 9 –B– 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSIOM D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. B M M 8 16X J D 0.010 (0.25) T A M B S S F DIM A B C D F G J K M P R R X 45 _ C –T– 14X G K M SEATING PLANE MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 966–01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M_ E HE 1 L 8 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M TTL, ECL, CMOS and Special Logic Circuits 0.10 (0.004) 3.1–56 DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ––– 0.78 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ––– 0.031 Motorola Master Selection Guide 16–Pin Packages SD SUFFIX PLASTIC SSOP PACKAGE CASE 940B–03 ISSUE B 16X K REF 0.12 (0.005) T U M S V S 0.25 (0.010) N 16 L/2 9 M N B L F PIN 1 IDENT 1 8 DETAIL E ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ K –U– A –V– 0.20 (0.008) M J T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. J1 DIM A B C D F G H J J1 K K1 L M K1 S SECTION N–N –T– –W– C 0.076 (0.003) SEATING PLANE D G DETAIL E H MILLIMETERS MIN MAX 6.07 6.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.73 0.90 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.238 0.249 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.028 0.035 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ S K K1 2X L/2 16 9 J1 B –U– L PIN 1 IDENT. SECTION N–N J N 8 1 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. M 0.15 (0.006) T U S A –V– N F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE H D Motorola Master Selection Guide DETAIL E G 3.1–57 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ TTL, ECL, CMOS and Special Logic Circuits 18–Pin Packages L,J SUFFIX CERAMIC DIP PACKAGE CASE 726–04 ISSUE G –A– 18 10 1 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. –B– OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18) L C N –T– SEATING PLANE K F M G D 18 PL 0.25 (0.010) J M T A 18 PL 0.25 (0.010) S M T B S DIM A B C D F G J K L M N INCHES MIN MAX 0.880 0.910 0.240 0.295 ––– 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 ––– 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02 P,N SUFFIX PLASTIC DIP PACKAGE CASE 707–02 ISSUE C 18 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B 9 1 A L C N F H D G SEATING PLANE TTL, ECL, CMOS and Special Logic Circuits K M 3.1–58 J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040 Motorola Master Selection Guide 20–Pin Packages L,J SUFFIX CERAMIC DIP PACKAGE CASE 732–03 ISSUE E 20 11 1 10 NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F DIM A B C D F G H J K L M N N H G D J K M SEATING PLANE 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B C –T– K SEATING PLANE M N E F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A –A– 20 11 –B– 10X P 0.010 (0.25) M B M 10 20X T B M DIM A B C D E F G J K L M N 0.010 (0.25) M T A B S S F R X 45 _ C –T– G Motorola Master Selection Guide K SEATING PLANE M 3.1–59 INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. J D 18X M M DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751D–04 ISSUE E 1 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 P,N SUFFIX PLASTICC DIP PACKAGE CASE 738–03 ISSUE E –A– G MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 TTL, ECL, CMOS and Special Logic Circuits 20–Pin Packages M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967–01 ISSUE O 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 M_ E HE 1 L 10 DETAIL P Z D VIEW P e A c A1 b 0.13 (0.005) 0.10 (0.004) M DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ––– 0.81 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ––– 0.032 SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C–03 ISSUE B 20X K REF 0.12 (0.005) M T U S V S 0.25 (0.010) N L/2 20 11 M B L PIN 1 IDENT 1 N F 10 DETAIL E –U– A –V– 0.20 (0.008) M T U ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ K J S J1 K1 SECTION N–N 0.076 (0.003) –T– SEATING PLANE –W– C D G H TTL, ECL, CMOS and Special Logic Circuits DETAIL E 3.1–60 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ Motorola Master Selection Guide 20–Pin Packages DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E–02 ISSUE A 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S ÍÍÍ ÍÍÍ ÍÍÍ K K1 2X L/2 20 11 B L J J1 –U– PIN 1 IDENT SECTION N–N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A –V– N F DETAIL E –W– C D 0.100 (0.004) –T– SEATING G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE Motorola Master Selection Guide 3.1–61 TTL, ECL, CMOS and Special Logic Circuits 20–Pin Packages FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M N S K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M H 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). TTL, ECL, CMOS and Special Logic Circuits 3.1–62 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– Motorola Master Selection Guide 24–Pin Packages J SUFFIX CERAMIC DIP PACKAGE CASE 758–02 ISSUE A B 24 13 1 12 L P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. J –A– N C K –T– SEATING PLANE G DIM A B C D F G J K L N P INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400 MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16 F D 24 PL 0.25 (0.010) M T A M L,J,JW SUFFIX CERAMIC DIP PACKAGE CASE 623–05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 A F C SEATING PLANE L G Motorola Master Selection Guide D N K M 3.1–63 J DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 TTL, ECL, CMOS and Special Logic Circuits 24–Pin Packages N SUFFIX PLASTIC DIP PACKAGE CASE 709–02 ISSUE C 24 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 13 B 1 12 A DIM A B C D F G H J K L M N L C N K H F M SEATING PLANE D G J 24 13 1 12 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. –B– L C –T– NOTE 1 K N E G M J F D 24 PL 0.25 (0.010) 24 PL 0.25 (0.010) P M T A M M P,N,PW SUFFIX PLASTIC DIP PACKAGE CASE 649–03 ISSUE D A 13 24 Q T B M DIM A B C D E F G J K L M N 1 12 H F C L N K D SEATING PLANE TTL, ECL, CMOS and Special Logic Circuits J 3.1–64 M INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. B G INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 P,N SUFFIX PLASTIC DIP PACKAGE CASE 724–03 ISSUE D –A– SEATING PLANE MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 DIM A B C D F G H J K L M N P Q MILLIMETERS MIN MAX 31.50 32.13 13.21 13.72 4.70 5.21 0.38 0.51 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.30 2.92 3.43 14.99 15.49 ––– 10 0.51 1.02 0.13 0.38 0.51 0.76 INCHES MIN MAX 1.240 1.265 0.520 0.540 0.185 0.205 0.015 0.020 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.012 0.115 0.135 0.590 0.610 ––– 10 _ 0.020 0.040 0.005 0.015 0.020 0.030 Motorola Master Selection Guide 24–Pin Packages DW SUFFIX PLASTIC WIDE SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 D 24X J 0.010 (0.25) M T A S B S DIM A B C D F G J K M P R F R X 45 _ C –T– M SEATING PLANE 22X K G MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 SD SUFFIX PLASTIC SSOP PACKAGE CASE 940D–03 ISSUE B 24X K REF 0.12 (0.005) M T U S V S ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ K L/2 24 J 13 K1 B L J1 SECTION N–N PIN 1 IDENT 1 12 0.20 (0.008) M T U 0.25 (0.010) –U– A –V– N M S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. N F DETAIL E 0.076 (0.003) –T– SEATING PLANE –W– C D G H Motorola Master Selection Guide DETAIL E 3.1–65 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 8.07 8.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.317 0.328 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ TTL, ECL, CMOS and Special Logic Circuits 24–Pin Packages DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948H–01 ISSUE O 24X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S 2X 24 L/2 B –U– L PIN 1 IDENT. 12 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. 13 S A –V– DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) –T– SEATING PLANE G D H –W– MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E N ÇÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇÇ ÉÉ 0.25 (0.010) K K1 J1 M N F SECTION N–N J TTL, ECL, CMOS and Special Logic Circuits DETAIL E 3.1–66 Motorola Master Selection Guide 28–Pin Packages FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B M T L–M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S SEATING PLANE K F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). Motorola Master Selection Guide 0.007 (0.180) 3.1–67 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– TTL, ECL, CMOS and Special Logic Circuits 32–Pin Package A –T–, –U–, –Z– FA SUFFIX PLASTIC TQFP PACKAGE CASE 873A–02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– BASE METAL ÉÉ ÉÉ ÉÉ N F 8X M_ R D J M 0.10 (0.004) AC AC T–U Z –AC– 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD TTL, ECL, CMOS and Special Logic Circuits Q_ GAUGE PLANE H 0.250 (0.010) C E 3.1–68 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Motorola Master Selection Guide 40–Pin Packages N SUFFIX PLASTIC DIP PACKAGE CASE 711–03 ISSUE C 40 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 21 B 1 20 L A C DIM A B C D F G H J K L M N N J H G F K D M SEATING PLANE MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 48–Pin Packages J SUFFIX CERAMIC DIP PACKAGE CASE 740–03 ISSUE B –A– 48 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 25 –B– 1 N –T– DIM A B C D E F G J K L M N 24 C L K SEATING PLANE F M E G D J 48 PL 0.25 (0.010) Motorola Master Selection Guide M T A 3.1–69 MILLIMETERS MIN MAX 60.36 61.56 14.64 15.34 3.05 4.31 0.381 0.533 1.27 BSC 0.762 1.397 2.54 BSC 0.204 0.330 2.54 4.19 15.24 BSC 0° 10° 1.016 1.524 48 PL 0.25 (0.010) M INCHES MIN MAX 2.376 2.424 0.576 0.604 0.120 0.127 0.015 0.021 0.050 BSC 0.030 0.055 0.100 BSC 0.008 0.013 0.100 0.165 0.600 BSC 0° 10° 0.040 0.060 M T B M TTL, ECL, CMOS and Special Logic Circuits 48–Pin Packages N SUFFIX PLASTIC DIP PACKAGE CASE 767–02 ISSUE B –A– 48 25 –B– 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). TIP TAPER 24 DETAIL X C –T– L K SEATING PLANE F D 32 PL 0.51 (0.020) G M T A M 48 PL N DETAIL X J 48 PL 0.25 (0.010) S T B M S INCHES MIN MAX 2.415 2.445 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.070 BSC 0.008 0.015 0.115 0.150 0.600 BSC 0_ 15_ 0.020 0.040 DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 61.34 62.10 13.72 14.22 3.94 5.08 0.36 0.55 1.02 1.52 2.54 BSC 1.79 BSC 0.20 0.38 2.92 3.81 15.24 BSC 0_ 15_ 0.51 1.01 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1201–01 ISSUE A 48X K REF 0.12 (0.005) M T U S V K K1 S T U S J J1 48 25 SECTION N–N M 0.254 (0.010) ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. B –U– L N 1 24 A –V– PIN 1 IDENT. N F DETAIL E D C TTL, ECL, CMOS and Special Logic Circuits 0.25 (0.010) –W– 0.076 (0.003) –T– SEATING PLANE M DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 ––– 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 ––– 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 ––– 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 ––– 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ H 3.1–70 Motorola Master Selection Guide 52–Pin Packages FN SUFFIX PLASTIC PLCC PACKAGE CASE 778–02 ISSUE C 0.007 (0.18) B Y BRK –N– U M T L–M 0.007 (0.18) M S N S T L–M N S S D Z –M– –L– W D 52 1 X V A 0.007 (0.18) M T L–M S N S R 0.007 (0.18) M T L–M S N S E C 0.004 (0.100) –T– SEATING J VIEW S PLANE G1 0.010 (0.25) S T L–M S H N F S 0.007 (0.18) M T L–M S N S 0.007 (0.18) M T L–M S N S VIEW S Motorola Master Selection Guide T L–M S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). K1 K S VIEW D–D Z G G1 0.010 (0.25) 3.1–71 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.710 0.730 0.040 ––– MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 18.04 18.54 1.02 ––– TTL, ECL, CMOS and Special Logic Circuits 52–Pin Packages FA SUFFIX PLASTIC TQFP PACKAGE CASE 848D–03 ISSUE D 4X 4X 13 TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N –X– X=L, M, N 52 40 1 CL 39 AB 3X –L– –M– AB B B1 13 V VIEW Y J 26 BASE METAL F PLATING V1 27 14 –N– A1 G VIEW Y ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ U 0.13 (0.005) M D T L–M S N S S1 SECTION AB–AB A ROTATED 90_ CLOCKWISE S 4X C q2 0.10 (0.004) T –H– –T– SEATING PLANE 4X q3 VIEW AA 0.05 (0.002) S W 2X R q1 R1 0.25 (0.010) C2 q GAGE PLANE K C1 E VIEW AA TTL, ECL, CMOS and Special Logic Circuits Z 3.1–72 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 12 _ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 12 _ REF Motorola Master Selection Guide 56–Pin Packages DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1202–01 ISSUE A 56X K K1 K REF 0.12 (0.005) M T U S V ÇÇÇÇ ÉÉ ÇÇÇÇ ÉÉ S T U S J J1 29 0.254 (0.010) M 56 SECTION N–N B –U– L 1 N 28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. A –V– PIN 1 IDENT. N F DETAIL E D C Motorola Master Selection Guide 0.25 (0.010) –W– 0.076 (0.003) –T– SEATING PLANE M DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 13.90 14.10 6.00 6.20 ––– 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.12 ––– 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.547 0.555 0.236 0.244 ––– 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.005 ––– 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ H 3.1–73 TTL, ECL, CMOS and Special Logic Circuits 68–Pin Package FN SUFFIX PLASTIC PLCC PACKAGE CASE 779–02 ISSUE C 0.007 (0.18) B Y BRK –N– M 0.007 (0.18) U T L–M M S N T L–M S S N S D Z –L– –M– W 68 X D 1 V Z 0.007 (0.18) R M M T L–M T L–M S S E C 0.004 (0.10) G 0.010 (0.25) S H –T– J VIEW S G1 T L–M S N SEATING PLANE S 0.007 (0.18) M T L–M S N S K 0.007 (0.18) M T L–M S N S VIEW S TTL, ECL, CMOS and Special Logic Circuits N N S T L–M S N S S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 K1 F S VIEW D–D 0.007 (0.18) A G1 0.010 (0.25) 3.1–74 INCHES MIN MAX 0.985 0.995 0.985 0.995 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.950 0.956 0.950 0.956 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.910 0.930 0.040 ––– MILLIMETERS MIN MAX 25.02 25.27 25.02 25.27 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 24.13 24.28 24.13 24.28 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 23.12 23.62 1.02 ––– Motorola Master Selection Guide Programmable Array 84–Pin Package FN SUFFIX PLASTIC PLCC PACKAGE CASE 780A–01 ISSUE A B 0.18 (0.007) M T N S –P L S S –M S U 0.18 (0.007) –N– M T N –P S S L S –M S Y BRK D Z1 –L– –M– W D 84 1 X V –P– G1 0.25 (0.010) M T N S –P S L S –M S DETAIL D–D A 0.18 (0.007) M T L 0.18 (0.007) M T L Z S –M S N S –P S S –M S N S –P S R E G C G1 0.25 (0.010) S T L 0.100 (0.004) –T– SEATING J S –M H K1 K F S N S –P PLANE DETAIL S S 0.18 (0.007) M T L S –M S N S –P S 0.18 (0.007) M T N S –P S L S –M S 0.18 (0.007) M T L S –M S N S –P S 0.18 (0.007) M T N S –P S L S –M S NOTES: 1. DATUMS –L–, –M–, –N–, AND –P– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PACKAGE BODY AT GLASS PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE GLASS PROTRUSION. ALLOWABLE GLASS PROTRUSION IS 0.25 (0.010) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 1.185 1.195 30.10 30.35 B 1.185 1.195 30.10 30.35 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.021 0.33 0.53 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 1.150 1.156 29.21 29.36 U 1.150 1.156 29.21 29.36 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2_ 10_ 2_ 10_ G1 1.110 1.130 28.20 28.70 K1 0.040 ––– 1.02 ––– Z1 2_ 10_ 2_ 10_ DETAIL S Motorola Master Selection Guide 3.1–75 TTL, ECL, CMOS and Special Logic Circuits Programmable Array 128–Pin Package DD SUFFIX PLASTIC QFP PACKAGE CASE 862A–02 ISSUE B L Y 96 65 97 DETAIL A C A–B 33 1 32 –D– A 0.20 (0.008) M H A–B S D S S D S 0.05 (0.002) A–B S 0.20 (0.008) M C A–B M DETAIL C –H– C E –C– DATUM PLANE 0.10 (0.004) G SEATING PLANE DETAIL B M H ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ W F J U DATUM PLANE N M C A–B T R BASE METAL D 0.20 (0.008) –H– S D K S DETAIL B TTL, ECL, CMOS and Special Logic Circuits X DETAIL C 3.1–76 DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D–TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. Z 128 –A–, –B–, –D– M V 0.20 (0.008) 0.20 (0.008) M B 0.05 (0.002) D –B– L S S H A–B –A– P D D S S 64 Q DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 ––– 4.07 0.30 0.45 3.17 3.67 0.30 0.40 0.80 BSC 0.25 0.35 0.13 0.23 0.65 0.95 24.80 REF 5_ 16 _ 0.13 0.17 0.40 BSC 0_ 7_ 0.13 0.30 30.95 31.45 0.13 ––– 0_ ––– 30.95 31.45 0.40 ––– 1.60 REF 1.60 REF 1.60 REF INCHES MIN MAX 1.098 1.106 1.098 1.106 ––– 0.160 0.012 0.018 0.125 0.144 0.012 0.016 0.032 BSC 0.010 0.014 0.005 0.009 0.026 0.037 0.976 REF 5_ 16 _ 0.005 0.007 0.016 BSC 0_ 7_ 0.005 0.012 1.219 1.238 0.005 ––– 0_ ––– 1.219 1.238 0.016 ––– 0.063 REF 0.063 REF 0.063 REF Motorola Master Selection Guide Programmable Array 160–Pin Package DH SUFFIX PLASTIC QFP PACKAGE CASE 864A–03 ISSUE C Y L 120 81 121 S S D C A–B S –A–, –B–, –D– B B M V 0.20 (0.008) M B L 0.20 (0.008) –B– –A– 0.20 (0.008) A–B H A–B S D 80 P DETAIL A G DETAIL A 41 160 Z 1 40 –D– A 0.20 (0.008) M H A–B S D 0.20 (0.008) A–B N S 0.20 (0.008) M C A–B S D ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ BASE METAL S S J F DETAIL C D –H– 0.13 (0.005) M C A–B S D S SECTION B–B M_ TOP & BOTTOM U_ C E T –H– R Q_ W –C– SEATING PLANE K H X 0.10 (0.004) DETAIL C Motorola Master Selection Guide NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 3.1–77 DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 3.35 3.85 0.22 0.38 3.20 3.50 0.22 0.33 0.65 BSC 0.25 0.35 0.11 0.23 0.70 0.90 25.35 REF 5_ 16_ 0.11 0.19 0.325 BSC 0_ 7_ 0.13 0.30 31.00 31.40 0.13 ––– 0_ ––– 31.00 31.40 0.40 ––– 1.60 REF 1.33 REF 1.33 REF INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 0.152 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5_ 16_ 0.004 0.007 0.013 BSC 0_ 7_ 0.005 0.012 1.220 1.236 0.005 ––– 0_ ––– 1.220 1.236 0.016 ––– 0.063 REF 0.052 REF 0.052 REF TTL, ECL, CMOS and Special Logic Circuits Programmable Array 181–Pin Package HI SUFFIX CERAMIC PGA PACKAGE CASE 768N–01 ISSUE O K A PIN 1 INDENTIFICATION C G F B M TTL, ECL, CMOS and Special Logic Circuits G 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 N L SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. A B C D E F G H J K L M N P R DIM A B C D F G K L M N INCHES MIN MAX 1.555 1.595 1.555 1.595 0.102 0.124 0.016 0.020 0.040 0.060 0.100 BSC 0.110 0.150 0.043 0.057 0.655 0.675 0.090 0.110 MILLIMETERS MIN MAX 39.50 40.51 39.50 40.51 2.59 3.15 0.41 0.51 1.02 1.52 2.54 BSC 2.79 3.81 1.09 1.45 16.64 17.15 2.29 2.79 D 181 PL –T– 0.030 (0.76) M T A 0.015 (0.38) M T 3.1–78 S B S Motorola Master Selection Guide Programmable Array 208–Pin Package DK SUFFIX PLASTIC QFP PACKAGE CASE 872A–01 ISSUE O L Y 156 105 157 0.20 (0.008) –B– DETAIL A S D S 53 208 1 Z 52 –D– A 0.20 (0.008) H A–B M D S S 0.05 (0.002) A–B S 0.20 (0.008) M C A–B S D S DETAIL C M E C –H– –C– SEATING PLANE DATUM PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.38 (0.015). DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z MILLIMETERS MIN MAX 27.90 28.10 27.90 28.10 3.45 4.10 0.14 0.30 3.20 3.60 0.14 0.26 0.50 BSC 0.25 0.35 0.09 0.20 0.70 0.90 25.50 REF 5_ 9_ 0.09 0.18 0.25 BSC 0_ 7_ 0.13 0.30 31.00 31.40 0.13 ––– 0_ ––– 31.00 31.40 0.40 ––– 1.60 REF 1.25 REF 1.25 REF INCHES MIN MAX 1.098 1.106 1.098 1.106 0.136 0.161 0.005 0.012 1.126 0.142 0.005 0.010 0.020 BSC 0.010 0.014 0.003 0.008 0.027 0.036 1.004 REF 5_ 9_ 0.003 0.007 0.010 BSC 0_ 7_ 0.005 0.012 1.220 1.236 0.005 ––– 0_ ––– 1.220 1.236 0.016 ––– 0.063 REF 0.049 REF 0.049 REF 0.10 (0.004) G H C A–B M V 0.20 (0.008) M B 0.05 (0.002) A–B –A– L H A–B S D S 104 DETAIL B M U T BASE METAL P ÇÇÇÇÇ ÉÉÉÉ ÇÇÇÇÇ ÉÉÉÉ ÇÇÇÇÇ ÉÉÉÉ F J –H– R DATUM PLANE N B D –A–, –B–, –D– DETAIL A Motorola Master Selection Guide 0.06 (0.002) M C A–B S D S W B K DETAIL B SECTION B–B ROTATED 7 _ CCW 3.1–79 Q X DETAIL C TTL, ECL, CMOS and Special Logic Circuits Programmable Array 224–Pin Package KE SUFFIX PIN GRID ARRAY PACKAGE CASE 860F–01 ISSUE O C 16X 0.100 A B 0.080 MAX Q E 16X 0.100 A B C D E F G H J K L M N P R T U 0.080 MAX SEATING PLANE 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D A L 224X 0.008 C 0.020 0.016 0.030 M C A 0.010 M C M B M NOTES: 1. DIMENSIONS ARE IN INCHES. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL BE 0.020. DIM A D E L Q TTL, ECL, CMOS and Special Logic Circuits 3.1–80 INCHES MIN MAX 0.070 0.145 1.740 1.780 1.740 1.780 0.100 0.200 0.045 0.075 Motorola Master Selection Guide Programmable Array 256–Pin Package BG SUFFIX PLASTIC BGA PACKAGE CASE 1208A–01 ISSUE O X DETAIL K D M F E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. G DIM A A1 A2 A3 b D E F G e S M Y MILLIMETERS MIN MAX 1.92 2.32 0.50 0.70 0.36 REF 1.12 1.22 0.60 0.90 27.00 BSC 27.00 BSC 24.00 24.70 24.00 24.70 1.27 BSC 0.635 BSC 0.20 S 20X e 3 256X A3 A1 0.35 Z A2 20X S e A B C D E F G H J K L M N P R T U V W Y A 21 20 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Z 0.15 Z 4 DETAIL K ROTATED 90 _CLOCKWISE b VIEW M–M 0.25 Z X Y Motorola Master Selection Guide 3.1–81 TTL, ECL, CMOS and Special Logic Circuits Programmable Array 299–Pin Package HV SUFFIX PIN GRID ARRAY PACKAGE CASE 861B–01 ISSUE O C 16X 0.100 A B 0.080 MAX Q E D 16X 0.100 A B C D E F G H J K L M N P R T U V W Y 0.080 MAX SEATING PLANE 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A L 224X 0.008 C 0.020 0.016 0.030 M C A 0.010 M C M B M NOTES: 1. DIMENSIONS ARE IN INCHES. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL BE 0.020. DIM A D E L Q S TTL, ECL, CMOS and Special Logic Circuits 3.1–82 INCHES MIN MAX 0.070 0.145 2.040 2.080 2.040 2.080 0.100 0.200 0.045 0.075 0.050 BSC Motorola Master Selection Guide Packaging Information Surface Mount stacked closer together and utilize less total volume than insertion populated PC boards. Printed circuit costs are lowered with the reduction of the number of board layers required. The elimination or reduction of the number of plated through holes in the board, contributes significantly to lower PC board prices. Automatic placement equipment is available that can place Surface Mount components at the rate of a few thousand per hour to hundreds of thousands of components per hour. Surface Mount Technology is cost effective, allowing the manufacturer the opportunity to produce smaller units and/or offer increased functions with the same size product. Surface Mount assembly does not require the preparation of components that are common on insertion technology lines. Surface Mount components are sent directly to the assembly line, eliminating an intermediate step. Why Surface Mount? Surface Mount Technology is utilized to offer answers to many problems that have been created in the use of insertion technology. Limitations have been reached with insertion packages and PC board technology. Surface Mount Technology offers the opportunity to continue to advance the state– of–the–art designs that cannot be accomplished with Insertion Technology. Surface Mount Packages allow more optimum device performance with the smaller Surface Mount configuration. Internal lead lengths, parasitic capacitance and inductance that placed limitations on chip performance have been reduced. The lower profile of Surface Mount Packages allows more boards to be utilized in a given amount of space. They are Pin Conversion Tables Dual–in–Line Package to PLCC Pin Conversion Data The following table gives the equivalent I/O pinouts of Dual–In–Line Package (DIP) configuration and Plastic Leaded Chip Carrier (PLCC) packages.* Conversion Tables 8 PIN DIP 1 2 3 4 5 6 7 8 20 PIN PLCC 2 5 7 10 12 15 17 20 14 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 PIN PLCC 2 3 4 6 8 9 10 12 13 14 16 18 19 20 16 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 PIN PLCC 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 20 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 PIN PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 PIN PLCC 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 21 23 24 25 26 27 28 * The MC1648 has a Non–Standard Conversion Table. For more information, refer to the Motorola MECL Data Book, DL122/D. Motorola Master Selection Guide 3.1–83 TTL, ECL, CMOS and Special Logic Circuits Tape and Reel Logic Integrated Circuits Motorola’s tape and reel packaging fully conforms to the latest EIA RS–481A specification. The antistatic embossed tape provides a secure cavity sealed with a peel–back cover tape. Mechanical Polarization Typical PLCC Devices View from tape side PIN 1 Linear direction of travel Typical SOIC Devices View from tape side Linear direction of travel General Information — Reel Size — Tape Width 13 inch (330 mm) Suffix: R2 12 mm to 24 mm (see table) — Units/Reel 500 to 5000 (see table) Ordering Information To order devices which are to be delivered in Tape and Reel, add the suffix R2 to the device number being ordered. Tape and Reel Data Device Type PLCC–20 PLCC–28 SO–8 SO–14 SO–16 SO–16 Wide SO–20 Wide Tape Width (mm) Device/Reel Reel Size (inch) Min Lot Size Per Part No. Tape and Reel 16 24 12 16 16 16 24 1,000 500 2,500 2,500 2,500 1,000 1,000 13 13 13 13 13 13 13 3,000 500 5,000 5,000 5,000 5,000 5,000 TTL, ECL, CMOS and Special Logic Circuits 3.1–84 Motorola Master Selection Guide