TI OPA676KG

®
OPA675
OPA676
Wideband Switched-Input
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● FAST SETTLING: 9ns (1%)
● PROGRAMMABLE-GAIN AMPLIFIER
● WIDE BANDWIDTH: 185MHz (AV = 10)
● FAST 2-INPUT MULTIPLEXER
● LOW OFFSET VOLTAGE: ±250µV
● SYNCHRONOUS DEMODULATOR
● TWO LOGIC SELECTABLE INPUTS
● PULSE/RF AMPLIFIERS
● FAST INPUT SWITCHING: 8ns (TTL)
● VIDEO AMPLIFIERS
● 16-PIN DIP PACKAGE
● ACTIVE FILTERS
DESCRIPTION
“classical” operational amplifier circuit architecture.
Unlike “current-feedback” amplifier designs, the
OPA675/676 may be used in all op amp applications
requiring high speed and precision.
The OPA675 and OPA676 are wideband monolithic
operational amplifiers with two independent differential inputs. Either input can be selected by an external
logic signal. The OPA675 is compatible with ECL logic
while the OPA676 is TTL compatible. Both amplifiers
are externally compensated and feature very fast input
selection speed: ECL = 4ns, TTL = 6ns. This amplifier
features fully symmetrical differential inputs due to its
Low distortion and crosstalk make these amplifiers
suitable for RF and video applications.
The OPA675 and OPA676 are available in KG (0°C to
+70°C) and SG (–55°C to +125°C) grades. All grades
are packaged in a 16-pin DIP.
_
Input A
A
+
Output
_
Compensation
B
Input B
+
TTL: OPA676
ECL: OPA675
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1988 Burr-Brown Corporation
PDS-864D
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At VCC = ±5VDC, RL = 150Ω, and TA = +25°C, unless otherwise noted.
OPA675/676JG, SG
PARAMETER
CONDITIONS
INPUT NOISE(1)
Voltage: fO = 10Hz
fO = 100Hz
fO = 1kHz
fO = 10kHz
fO = 100kHz
fB = 10Hz to 10MHz
Current: fO = 10Hz to 1MHz
OFFSET VOLTAGE(1)
Input Offset Voltage
Average Drift
Supply Rejection
MIN
TYP
MAX
RS = 0Ω
27
10
3.8
2.6
2.4
7.9
2.7
VCM = 0VDC
TA = TMIN to TMAX
±VCC = 4.5V to 5.5V
±500
±3
86
±2mV
±10
65
OPA675/676KG
MIN
TYP
MAX
*
*
*
*
*
*
*
70
UNITS
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
pA/√Hz
±250
±1
*
±1mV
±5
µV
µV/°C
dB
BIAS CURRENT(1)
Input Bias Current
VCM = 0VDC
23
35
*
30
µA
OFFSET CURRENT(1)
Input Offset Current
VCM = 0VDC
0.8
5
*
*
µA
INPUT IMPEDANCE(1)
Differential
Common-Mode
INPUT VOLTAGE RANGE(1)
Common-Mode Input Range
Common-Mode Rejection
4k 2
105 5
*
*
Ω pF
Ω pF
±1.25
75
±2.5
100
*
85
*
*
V
dB
65
70
*
*
dB
100
145
185
60
–100
–80
–68
–35
*
*
*
*
*
*
*
*
MHz
MHz
MHz
MHz
dBC(2)
dBC
dBC
dBC
Gain = +10V/V
0.625V Output Step
–61
–73
44
350
9
15
25
*
*
*
*
*
*
*
dBC
dBC
MHz
V/µs
ns
ns
ns
INPUT SELECTION(3)
Transition Time
50% In to 50% Out
ECL: OPA675
TTL: OPA676
5
7.5
*
*
ns
ns
DIGITAL INPUT
TTL Logic Levels: VIL
VIH
IIL
IIH
ECL Logic Levels: VIL
VIH
IIL
IIH
Logic “LO”
Logic “HI”
Logic “LO”, VIL = 0V
Logic “HI”, VIH = +2.7V
Logic “LO”
Logic “HI”
Logic “LO”, VIL = –1.6V
Logic “HI”, VIH = –1.0V
VIN = ±0.5VDC, VO = ±1.25V
OPEN LOOP GAIN, DC(1)
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Closed-Loop Bandwidth
Crosstalk
Harmonic Distortion: 10MHz
Full Power Response
Slew Rate
Settling Time: 1%
0.1%
0.01%
RATED OUTPUT
Voltage Output
Gain = +2V/V
Gain = +5V/V
Gain = +10V/V
Gain = +50V/V
Gain = +10V/V, f = 100kHz
f = 1MHz
f = 10MHz
f = 100MHz
G = +10V/V, RL= 50Ω, VO = 0.5Vp-p
Second Harmonic
Third Harmonic
VO = 2.5Vp-p, Gain = +10V/V
Gain = +10V/V
1MHz, Open-Loop, CC = 5pF
Gain = +2V/V
Continuous to Gnd
* Same specifications as for JG.
®
OPA675/676
0
+2.0
–0.05
1
–1.81
–1.15
–50
–50
±2.1
+1.25
–0.95
RL = 150Ω
RL = 50Ω
Current Output
Output Resistance
Load Capacitance Stability
Short Circuit Current
25
200
2
±2.6
+1.8
–1.1
±30
5
50
+45
–25
30
240
+0.8
+5
–0.2
20
–1.475
– 0.88
–100
–100
*
*
*
*
*
*
*
*
*
*
–1.0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
V
mA
µA
V
V
µA
µA
V
V
V
mA
Ω
pF
mA
mA
SPECIFICATIONS (CONT)
ELECTRICAL
At VCC = ±5VDC, RL = 150Ω, and TA = +25°C, unless otherwise noted.
OPA675/676JG, SG
PARAMETER
POWER SUPPLY
Rated Voltage
Derated Performance
Current, Quiescent
TEMPERATURE RANGE
Specification
Operating:
θ JA
CONDITIONS
MIN
±VCC
±VCC
IO = 0mADC
4.5
Ambient Temp JG, KG
SG
Ambient Temp JG, KG, SG
0
–55
–55
TYP
OPA675/676KG
MAX
MIN
6.5
30
*
+70
+125
+125
*
5
22
TYP
MAX
UNITS
*
*
VDC
VDC
mA
*
*
*
*
*
125
*
°C
°C
°C
°C/W
* Same specifications as for JG.
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±5VDC, RL = 150Ω, and TA = TMIN to TMAX, unless otherwise noted.
OPA675/676JG, SG
PARAMETER
TEMPERATURE RANGE
Specification
OFFSET VOLTAGE
Average Drift
Supply Rejection
CONDITIONS
MIN
Ambient Temp JG, KG
SG
0
–55
TA = TMIN to TMAX
±VCC = 4.5V to 5.5V
60
TYP
OPA675/676KG
MAX
MIN
+70
+125
*
±3
85
±10
65
TYP
MAX
UNITS
*
°C
°C
±1
*
±5
µV/°C
dB
BIAS CURRENT
Input Bias Current
VCM = 0VDC
29
50
*
*
µA
OFFSET CURRENT
Input Offset Current
VCM = 0VDC
0.8
10
*
*
µA
INPUT VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
VIN = ±0.5VDC, VO = ±1.25V
OPEN LOOP GAIN, DC
Open-Loop Voltage Gain
DIGITAL INPUT
TTL Logic Levels: VIL
VIH
IIL
IIH
ECL Logic Levels: VIL
VIH
IIL
IIH
RATED OUTPUT
Voltage Output
POWER SUPPLY
Current, Quiescent
Logic “LO”
Logic “HI”
Logic “LO", VIL = 0V
Logic “HI”, VIH = +2.7V
Logic “LO”
Logic “HI”
Logic “LO”, VIL = –1.6V
Logic “HI”, VIH = –1.0V
±2.0
60
±2.3
80
*
65
*
*
V
dB
60
68
63
69
dB
0
+2.0
–0.08
5
–1.81
–1.15
IO = 0mADC
*
*
±2.5
+1.6
–1.0
25
*
*
*
V
V
V
*
*
*
*
–0.9
35
*
*
V
V
mA
µA
V
V
µA
µA
*
*
–50
–50
±2.0
+1.25
–0.8
RL = 150Ω
RL = 50Ω
+0.8
+5
–0.4
50
–1.475
–0.88
*
*
*
*
*
*
*
*
mA
* Same specifications as for JG.
NOTES: (1) Specifications are for both inputs (A and B). (2) dBC = Level referred to carrier-input signal. (3) Switching time from application of digital logic signal to
input signal selection.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA675/676
PIN CONFIGURATIONS
OPA675
OPA676
+In A
1
16 +In B
+In A
1
16 +In B
–In A
2
15 –In B
–In A
2
15 –In B
Offset Trim
3
14 DNC
Offset Trim
3
–
+
+
A
–
B
–
+
A
+
–
14 DNC
B
Offset Trim
4
13 CHA (ECL)
Offset Trim
4
13 DNC *
Compensation
Capacitor
5
12 CHA (ECL)
Compensation
Capacitor
5
12 CHA (TTL)
NC
6
11 Common
NC
6
11 Common
+V CC 7
Output
10 –VCC
8
+V CC 7
9 NC
Output
10 –V CC
8
9 NC
*Capacitance on this node slows channel select.
PIN ASSIGNMENTS: OPA675
1
2
3
4
5
6
7
8
+In A
–In A
Offset Trim
Offset Trim
Compensation Capacitor
NC
+VCC
Output
PIN ASSIGNMENTS: OPA676
16
15
14
13
12
11
10
9
+In B
–In B
DNC
CHA (ECL)
CHA (ECL)
Common
–VCC
NC
1
2
3
4
5
6
7
8
NC = No Internal Connection
DNC = Do Not Connect
DNC = Do Not Connect
Supply ............................................................................................. ±7VDC
Differential Input Voltage ............................................................. Total VCC
Input Voltage Range (Analog and Digital) .......................................... ±VCC
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Output Short Circuit to Ground (+25°C) ................... Continuous to ground
Junction Temperature .................................................................... +175°C
Basic Model Number
Performance Grade Code
J, K: 0°C to +70°C
S: –55°C to +125°C
Package Code
G: 16-pin Ceramic DIP
PACKAGE INFORMATION
OPA675/76JG
OPA675/76SG
OPA675/76KG
PACKAGE
PACKAGE DRAWING
NUMBER(1)
16-Pin Hermetic DIP
16-Pin Hermetic DIP
16-Pin Hermetic DIP
109
109
109
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
OPA675/676
16
15
14
13
12
11
10
9
+In B
–In B
DNC
DNC
CHA (TTL)
Common
–VCC
NC
NC = No Internal Connection
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
MODEL
+In A
–In A
Offset Trim
Offset Trim
Compensation Capacitor
NC
+VCC
Output
4
OPA675
( )( )
OPA676
( )( )
DICE INFORMATION
PAD
FUNCTION
PAD
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TTL Set
–InB
+InB
NC
NC
+InA
–InA
NC
VOS Adjust
VOS Adjust
NC
Comp Cap
NC
NC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+VCC
+VCC
VOUT
NC
NC
NC
NC
–VCC
–VCC
Ground
CHA (TTL)
ECLOUT
CHA (ECL)
CHA (ECL)
NC: No Connection (Do Not Connect). OPA675-Do not use
pads 1, 25, 26. OPA676-Connect pad 26 to pad 27. Connect pad
1 to pad 28.
Substrate Bias: –VCC
MECHANICAL INFORMATION
MILS (0.001")
103 x 90 ±5
20 ±3
Die Size
Die Thickness
OPA675/676 DIE TOPOGRAPHY
TYPICAL PERFORMANCE CURVES
LARGE SIGNAL
HARMONIC DISTORTION vs FREQUENCY
SMALL SIGNAL
HARMONIC DISTORTION vs FREQUENCY
–30
Gain = +10V/V
RL = 50 Ω
VO = 0.5Vp-p
2f
–50
3f
–60
–70
Gain = +10V/V
RL = 1k Ω
VO = 2.5Vp-p
–40
0.1
–60
–70
1
10
0.1
100
AV = +10V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
50
φ
25
–45
15
–90
10
–135
5
–180
0
0.3
1
24
10
100
BW = 185MHz
φ = –139.5°
φ
Gain
21
0
20
CC = 6.5pF
27
Gain (dB)
Gain (dB)
φ
Gain
30
30
BW = 60.6 MHz
φ = –60.5°
Phase (°)
35
100
Frequency (MHz)
AV = +50V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
CC = none
10
1
Frequency (MHz)
40
2f
–50
–80
–80
45
3f
18
φ
15
0
12
–45
9
–90
6
–135
3
–180
Phase (°)
–40
Harmonic Distortion (dBC)
Harmonic Distortion (dBC)
–30
0
1000
0.3
Frequency (MHz)
1
10
100
1000
Frequency (MHz)
®
5
OPA675/676
TYPICAL PERFORMANCE CURVES (CONT)
AV = +2V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
AV = +5V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
φ
Gain
14
12
φ
10
8
φ
5
0
–90
3
–90
–135
2
–135
–180
1
–180
4
2
0
0.3
1000
100
6
–45
6
10
φ
4
–45
1
BW = 100.3MHz
φ = –62.5°
Gain
7
0
8
0
0.3
CC = 35pF
9
1
10
1MHz HARMONIC DISTORTION vs POWER OUTPUT
5MHz HARMONIC DISTORTION vs POWER OUTPUT
–20
–20
A V = +10V/V (20dB)
CC = 6.5pF
RL = 50 Ω
f C = 1MHz
–40
A V = +10V/V (20dB)
CC = 6.5pF
RL = 50 Ω
f C = 5MHz
–30
–40
Distortion (dBC)
–30
Distortion (dBC)
1000
100
Frequency (MHz)
Frequency (MHz)
–50
–60
2f
–70
3f
–50
–60
2f
–70
3f
–80
–80
0.125Vp-p
–90
–20
–15
0.25Vp-p
–10
0.5Vp-p
–5
1Vp-p
0.125Vp-p
2Vp-p
+5
0
+10
–90
–20
+15
–15
0.25Vp-p
–10
A V = +10V/V (20dB)
CC = 6.5pF
RL = 50 Ω
f C = 10MHz
–30
–40
–50
2f
–60
3f
–70
+5
2Vp-p
+10
+15
AVV = +10V/V (20dB)
CC = 6.5pF
RL = 50 Ω
fCC = 20MHz
2f
–50
3f
–60
–70
–80
–80
0.125Vp-p
–90
–20
1Vp-p
0
–20
Distortion (dBC)
–40
0.5Vp-p
20MHz HARMONIC DISTORTION vs POWER OUTPUT
10MHz HARMONIC DISTORTION vs POWER OUTPUT
–20
–30
–5
Power Output (dBm)
Power Output (dBm)
Distortion (dBC)
Phase (°)
BW = 145.5MHz
φ = –99.6°
Phase (°)
16
Gain (dB)
10
CC = 16pF
18
Gain (dB)
20
–15
0.25Vp-p
–10
0.5Vp-p
–5
1Vp-p
0
+5
0.125Vp-p
2Vp-p
+10
–90
–20
+15
–10
–5
0.5Vp-p
1Vp-p
0
Power Output (dBm)
Power Output (dBm)
®
OPA675/676
–15
0.25Vp-p
6
+5
2Vp-p
+10
+15
TYPICAL PERFORMANCE CURVES (CONT)
2.5MHz SMALL-SIGNAL
HARMONIC DISTORTION SPECTRUM
CHANNEL-TO-CHANNEL
CROSSTALK vs FREQUENCY
0
0
10.0MHz
–68.3dB
–15
–10
Gain = +10V/V
VOUT = 500mVp-p
RL = 50Ω
–20
Output Power (dBm)
Crosstalk (dBC)
–30
–45
–60
–75
–90
–105
–30
–40
–50
–60
–70
–120
0.3
1
10
100
–80
1000
Frequency (MHz)
–90
2
4
6
8
10
12
Frequency (MHz)
NOMINAL FREQUENCY COMPENSATION vs NOISE GAIN
OPEN-LOOP GAIN, CMR AND PSR vs TEMPERATURE
110
A OL ,PSR, and CMR (dB)
Compensation Capacitor (pF)
35
30
25
20
15
10
CMR
100
90
80
PSR
70
AOL
60
5
0
1
2
3
4 5 6
8 10
20
30
50
–50
50 70 100
Noise Gain (V/V)
–25
0
+25
+50
+75
+100
+125
Temperature (°C)
THEORY OF OPERATION
each input separately allowing a wide range of circuit
applications. The feedback network connected to the selected input operates in a normal op amp fashion while the
feedback network connected to the de-selected input is
totally inactive, appearing only as an additional load to the
amplifier’s output stage.
An OPA675 simplified circuit is shown in Figure 1. It is a
“classical” high-speed op-amp architecture with one important exception — the amplifier has two ECL logic selectable
differential input stages. An appropriate differential ECL
logic signal on A and A (labeled B Select) will turn on either
Q5 or Q6, steering operating (tail) current to either differential input pair Q1 and Q2 or Q3 and Q4. The input pair
receiving the tail current operates as a conventional op-amp
input stage while the de-selected input pair receiving no tail
current appears as an open circuit. The de-selected inputs
have only a few pF parasitic capacitance and in the off
condition exhibit only a very low leakage (bias) current of
about 100pA. Two feedback networks can be connected to
The switched-input op amp (SWOP AMP) circuit of the
OPA676 is basically the same as the OPA675 but a TTL
compatible level shifter (Figure 2) has been added to its input
selection logic circuit.
Standard TTL (OPA676) and ECL (OPA675) logic levels
may be applied to each input selection circuit but only
®
7
OPA675/676
+VCC
Bias
Q7
B
Select
Q8
A
Select
–
A
Q1
B
Q2
+ –
Q3
Q4
+
Comp
Out
Q5
Q6
ITAIL
–VCC
FIGURE 1. OPA675 Simplified Circuit Diagram.
350mV is typically required to switch between inputs. This
logic input sensitivity allows simpler high-speed logic driver
circuitry and it minimizes digital noise coupling into adjacent wideband analog circuitry and allows single ended ECL
inputs to be used with VBB applied to the other input.
range of gains with excellent results. Closed-loop gain/phase
(Bode) plots are shown in the Typical Performance Curves.
OFFSET TRIM
Input offset voltage is low enough for many video applications. If desired, offset voltage can be trimmed with a 1kΩ
potentiometer connected to +VCC. Trimming offset voltage
in this manner will effect both input A and input B;
independent control of input offset will require that trim
adjust current be summed into one or both inputs. This
technique is shown in a few applications circuits on the pages
to follow.
The OPA675 and OPA676 are designed to be frequency
compensated by a single capacitor connected from pin 5 to
ground. Recommended compensation is shown in Typical
Performance Curves. A small variable capacitor may be
trimmed for best bandwidth, settling time, and gain peaking.
This amplifier is designed for optimum performance in gains
of 5V/V to 20V/V, but it can also be used over a far wider
+VCC
FPO
FPO
ECL
Out
TTL
In
ECL
Threshold
FIGURE 2. Internal OPA676 TTL Logic Level Shifter.
FIGURE 3. 1% Settling Time.
®
OPA675/676
8
Tektronix
SG503
10MHz
50mVp-p
100Ω
To Scope
100Ω
100Ω
+0.5V
500Ω
–0.5V
500Ω
1MHz
Square
Wave
2
1
75Ω
1kΩ
2
1
–
+
8
–
16
+
100Ω
8
50Ω
15
+
–
To Scope
OPA676
+
–
11
5
12
RL
100Ω
6.5pf
5
3MHz
TTL
5-30pf
1kΩ
FIGURE 4. OPA675/676 Settling Time Test Circuit.
FIGURE 5. OPA676 Input Selection Transition Time Test
Circuit.
APPLICATION TIPS
6.
Wirewound resistors (even “non-inductive” types) are
absolutely unacceptable in high frequency circuits.
7.
Avoid overloading the output. Remember that output
current must be provided by the amplifier to drive its
own feedback network as well as to drive its “load.”
Lowest distortion is achieved with high impedance
loads.
8.
PC board traces for signal and power lines should be
wide to reduce impedance or inductance.
9.
Don’t forget that these amplifiers use ±5V supplies.
Although they will operate perfectly well with +5V
and –5.2V, the use of ±15V supplies will result in
destruction.
Wideband amplifier circuits require good layout techniques
to be successful. The use of short, direct signal paths and
heavy (2 oz. copper recommended) ground planes are absolutely necessary to achieve the performance level inherent in
the OPA675/676. Oscillation, ringing, poor bandwidth and
settling, gain peaking, and instability are typical problems
that plague all high-speed amplifiers when they are used in
poor layouts. The OPA675 and OPA676 are no different in
this respect—any amplifier with a gain bandwidth product of
a few GHz requires some care be taken in its application.
Points to remember:
1.
2.
3.
Use a heavy copper ground plane on the component side
of your PC board. This provides a low inductance
ground and it also conducts heat from active circuit
package pins into ambient air by convection.
10. Standard commercial test equipment has not been designed to test devices in the OPA675/676 speed range.
Benchtop op amp testers and ATE systems will require
a special test head to successfully test these amplifiers.
Bypass power supply pins directly at the active device.
The use of tantalum capacitors (1 to 10µF/10V) with
very short leads is highly recommended. Supply pins
should not be left unbypassed.
11. High-speed amplifiers can drive only a limited amount
of capacitance. If the load exceeds 10 to 20pF consider
using a fast buffer or a small resistor to isolate the
capacitance from the amplifier’s output. Capacitive
loads will cause loop instability if not compensated for.
Signal paths should be short and direct. Feedback
resistors, compensation capacitors, termination resistors, etc., should have lead lengths no longer than 1/4
inch (6cm).
4.
Surface-mount components (chip resistors, capacitors,
etc.) have low inductance and are therefore recommended. Parasitic inductance and capacitance should be
avoided if best performance is to be achieved.
5.
Resistors used in feedback networks should have values
of a few hundred ohms for best performance. Shunt
capacitance problems limit the acceptable range to about
1kΩ or on the high resistance end and to a value that is
within the amplifier’s output drive limits on the low end.
Metal film and carbon compensation resistors will be
satisfactory.
12. Terminate transmission line loads. Unterminated lines,
such as coaxial cable, can appear to the amplifier to be
a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the
amplifier’s load then appears as a purely resistive
impedance.
13. For clean, fast input selection the logic input pins should
be terminated with appropriate resistors. Resistors should
be connected from input selection pins to ground plane
with short leads. Failure to terminate long lines will
result in ringing and poor high frequency switching.
14. Plug-in prototype boards and wire-wrap boards will not
be satisfactory. A clean layout using RF techniques is
required; there is no shortcut.
®
9
OPA675/676
1kΩ
100Ω
10MHz
50mVp-p
2
–
31
+
8
To Scope
OPA675
16
100Ω
MC10105
5
13
6.5pF
2
5
3MHz
ECL
15
12
4
11
+
–
3
1kΩ
50Ω
300Ω
300Ω
–5.2V
FIGURE 6. OPA675 Input Selection Transition Time Test Circuit.
499Ω
+5V
10kΩ
49.9Ω
2
–
49.9Ω
5kΩ
1
49.9Ω
+
OPA676
16
+
40.2Ω
15
10Ω
11
A
+10
0
8
12
B
–
1MHz TTL CARRIER FEEDTHROUGH vs FREQUENCY
To 50Ω
Oscilloscope
or
Spectrum
Analyzer
Carrier Feedthrough (dBm)
Offset Trim
–5V
5
50
Ω
5-30pF
TTL
499Ω
Input:
+2.8V
+0.4V
–10
–20
–30
–40
–50
–60
–70
–80
0
TTL rise and fall time = 10ns
Frequency = 1MHz
2
4
6
8
10
Frequency (MHz)
FIGURE 7. OPA676 Carrier Feedthrough and Switching
Transient Test Circuit.
FIGURE 9. Carrier Feedthrough from 1MHz TTL Logic.
Offset Trimmed for Maximum Carrier Rejection
316Ω
+5V
+
50Ω
Input
7
49.9Ω
2
1
Offset
Trim
2.2µF
10V*
–
+ A
3
50Ω
Output
1kΩ
4
8
OPA676
16
15
12
+
2.2µF
10V*
–5V
12pF
* Tantalum
FIGURE 10. OPA676 Used as a Conventional Op Amp: A
10dB Gain Wideband Video Amplifier with
50Ω Input/Output Impedance.
®
OPA675/676
11
+ B
–
10
FIGURE 8. OPA676 Switching Transient. Top Trace: TTL
Input (2V/cm). Bottom Trace: Amplifier Output
(2mV/cm). Input B Offset Voltage has been
Trimmed to Match Input A Offset Voltage.
49.9Ω
5
10
301Ω
20Ω
100 Ω
+5V
2
Input
1
3
–
+ A
16
15
+ B
–
+5V
TTL
Offset Trim
3
1kΩ
4
2
Input
8
49.9
Ω
Output
5
11
3pF
1
4.7µF*
+
4
16
8
11
+ B
–
ADC603
7
OPA676
15
20Ω
10k Ω
–
+ A
12
OPA676
301Ω
100 Ω
4.7µF* 39 pF
+
10
12
20Ω
-5V
59 Ω
301Ω
45
Signal
Input
46
Analog
Common
5
412 Ω
Bandwidth = ~200MHz
* Tantalum
Gain Select (TTL)
FIGURE 11. Very Fast Programmable Gain Amplifier with
Voltage Gains of +1V/V and +16V/V (0dB and
24dB).
FIGURE 12. Programmable-Gain +2V/V (6dB) or +8V/V
(18dB) Buffer Amplifier for Floating-Point
Conversion.
3
+
6
OPA621
–
2
200Ω
Differential
Input
1
200Ω
2
200Ω
1kΩ
100Ω
+
OPA621
6
100Ω
TTL
–
3
2
1kΩ
1
–
+ A
12
OPA676
OPA675
1kΩ
16
15
3
+ B
–
8
Out
5
11
~5pF
+
100Ω
6
OPA621
–
2
100Ω
1kΩ
200Ω
Differential
Input
2
200Ω
2
200Ω
+
OPA621
6
–
3
FIGURE 13. High Input Impedance Differential Input Multiplexer with Gain of 30V/V (30dB).
®
11
OPA675/676
40Ω
200Ω
–5V 5kΩ +5V
TTL
2
40Ω
1
8
Out
50Ω
RF or IF
In
100Ω
15
5
11
16pF
2
10kΩ
Offset Trim
5
+ B
–
15
+5v
50Ω
RF or IF
Out
49.9Ω
8
OPA676
16
10kΩ
12
49.9Ω
Gain
Trim
10Ω
Noise
Blanking
49.9Ω Pulse
Input
–
+ A
1
200Ω
95.3Ω
TTL In
10Ω
16
+
–
909Ω
90.9Ω
12
+
OPA676
In
4.99kΩ
–
6.5pF
11
49.9Ω
909Ω
–5v
100Ω
FIGURE 14. Synchronous Modulator/Demodulator with Carrier Balance Trim (Gain = ±5V/V).
51.1 Ω
383 Ω
FIGURE 16. Receiver Noise Blanker: A Wideband Gated
Video Amplifier.
383 Ω
+5V
Offset Trim
3
2
Input
A
49.9
Ω
1
4
–
+ A
15
49.9
Ω
+ B
–
–
ADC603
In 1
7
Diff ECL
100Ω
A
+
8
11
45
5
2
Signal
Input
1kΩ
1
46
12
16
Analog
Common
1kΩ
15
51.1 Ω
–5V
383 Ω
–
+ A
A
12
13
8
OPA676
4.7µF* 4.7 pF
+
10
1kΩ
100Ω
4.7µF*
+
OPA675
OPA676
16
Input
B
10k Ω
+ B
–
Output
5
~5pF
11
+
383 Ω
100Ω
In 2
–
* Tantalum
Input Select (TTL)
FIGURE 17. Differential Input Multiplexer with Gain of
10V/V (20dB).
FIGURE 15. Multiplexed Input +16V/V Gain (24dB) Buffer
Amplifier.
R1
1kΩ
100Ω
R2
TTL
2
In
1
–
12
+
8
OPA676
16
15
+
–
R1
Out
5
11
CC
R2
FIGURE 18. Programmable-Gain Amplifier.
®
OPA675/676
12
VOLTAGE GAIN
(V/V)
R1
(Ω)
R2
(Ω)
CC
(pF)
+2
+5
+10
200
49.9
22.1
200
200
200
35
16
6.5
(Carrier Suppression)
Offset Trim
+5V
5kΩ
–5V
455kHz
Carrier
Input
4.99kΩ
909Ω
90.2Ω
300Hz
to 3kHz
Audio
Input
1kΩ
1kΩ
10Ω
Diff ECL
A
2
+
OPA620
–
+ A
1
–
A
+
12
49.9Ω
OPA620
13
8
OPA675
16
1kΩ
1kΩ
+ B
–
15
100Ω
5
1.5kΩ
455kHz
BP
Filter*
–
50Ω
RF
Out
6.5pF
11
1.5kΩ
* Murata Erie
CFS455C
909Ω
FIGURE 19. Single Sideband Suppressed Carrier Generator.
R1
R2
TTL
2
–
+
In 1
1
12
16
In 2
5
+
–
15
Out
8
OPA676
11
CC
R1
VOLTAGE GAIN
(V/V)
R1
(Ω)
R2
(Ω)
CC
(pF)
+2
+4
+8
+16
+32
200
75
28
20
10
200
226
196
301
309
35
22
10
3
0
R2
FIGURE 20. Two-Input Multiplexer (with gain).
R1
R2
TTL
2
1
–
+
12
8
OPA676
In
16
+
–
5
11
15
R3
Out
CC
VOLTAGE GAIN
(V/V)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
CC
(pF)
±2
±5
±10
100
40
20
200
200
200
200
50
25
200
200
225
35
16
6.5
R4
FIGURE 21. Synchronous Modulator/Demodulator (with gain).
®
13
OPA675/676