AND8173/D Termination and Interface of ON Semiconductor ECL Devices With CML (Current Mode Logic) OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Introduction Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD TERMINATED 50 W PER LINE TO VCC SECTION 3.Cap Coupled (AC) CML LOAD TERMINATED 50 W PER LINE TO Vterm SECTION 4.CML INTERFACE INTERCONNECTS This document will discuss general termination and interface interconnection of On Semiconductor ECL devices with Current Mode Logic (CML) OUTPUT Structures. ECL has a long history of using a coupled emitter differential pair output structure with an Emitter Follower (EF) as shown in Figure 2. This classic EF output displays about 6 W − 8 W internal impedance in both LOW and HIGH output states. A constant internal current, ICS, is steered through one side or the other by the two switching transistors. Now, some devices are available using CML outputs structures with internal impedance of 50 W as shown in Figures 1. On Semiconductor ECL CML devices offer back source termination to 50 W impedance and a potential reduction in external components. Information regarding the Termination of ECL Devices with Emitter Follower (EF) OUTPUT Structure may be found in AND8020. CML Output Driver EF Output Driver VCC VCC Q Q Q Q ICS ICS VEE VEE Figure 2. ECL with Emitter Follower Output, Output Structures Figure 1. ECL with CML, Current Mode Logic Output Structures © Semiconductor Components Industries, LLC, 2008 October, 2008 − Rev. 3 1 Publication Order Number: AND8173/D AND8173/D SECTION 1. UNLOADED CML DRIVER OUTPUT VOLTAGE LEVELS (DC OPEN) This coupled emitter differential pair output structure incorporates an internal 16 mA constant source bias, ICS, as “tail current”. The unloaded open output voltages, VOPEN, result from the internal current, ICS, steered through each 50 W, RC, collector resistor by the output transistors per Figures 3 and 4. The two output states, VoutOPEN HIGH and VoutOPEN LOW, are complementary. One output side of the differential pair will present an output voltage of VCC − 800 mV, or VoutOPEN LOW due to the 16 mA ICS, drawn through its RC. The complementary output side, VoutOPEN HIGH has essentially no current flow, IOFF, and so will drop essentially 0 V across its RC, thus remaining near VCC. Switching is accomplished by steering the constant 16 mA ICS tail current from one side to the other. Where: ICS = Constant Current Source Bias RC = Output Transistor Collector Resistor Unloaded (open) CML Outputs Q and Q will present either a VoutOPEN HIGH voltage level near VCC or a VoutOPEN LOW voltage level of VCC − 800 mV. An active complementary signal pair will produce characteristic parameters per Table 1. Table 1. CML DRIVER LEVELS (with Open, Unloaded Outputs) Parameter VoutOPEN HIGH VoutOPEN HIGH + VCC * (IOFF @ RC) + VCC * 0 (eq. 1) VoutOPEN LOW + VCC * (ICS @ RC) + VCC * 800 Level (eq. 2) Unit VCC VoutOPEN CM VCC − 400 mV VoutOPEN LOW VCC − 800 mV VoutOPEN SE (Note 1) 800 mVpp VoutOPEN DIFF 1600 mVpp 1. Each line measured single−ended. Unloaded CML Output Driver VCC RC1 50 W RC2 50 W 16 mA 0 mA Unloaded CML Output Driver VCC Q Q VoutOPEN HIGH = VCC VoutOPEN LOW = VCC − 800 mV RC1 50 W RC2 50 W 0 mA 16 mA Q Q VCS VCS ICS = 16 mA ICS = 16 mA VEE VoutOPEN LOW = VCC − 800 mV VoutOPEN HIGH = VCC VEE Figure 3. CML Open Output Driver Currents and Levels (Q HIGH, Q LOW) Figure 4. CML Open Output Driver Currents and Levels (Q LOW, Q HIGH) http://onsemi.com 2 AND8173/D SECTION 2. DIRECT CONNECT (DC) CML LOAD TERMINATED 50 W PER LINE TO VCC 50 W to VCC as shown in Figures 5 and 6. Both output lines in a differential pair should have equal loads to maintain balanced dynamic signal loading to the driver. The complementary side draws essentially zero current, Ioff and remains near VCC. When the output is connected to a current source (loaded), the driver’s internal constant 16 mA tail current, ICS, now draws from the active side transistor through the internal 50 W, RC (collector resistor), and also through the receiver’s 50 W (RT) termination to a current source. A typical receiver termination (internal or external termination resistor) is CML Receiver VCC Loaded CML Output Driver VCC RC1 50 W RC2 50 W 8 mA Q 0 mA VoutLOADED HIGH = VCC Z0 = 50 W D RT2 50 W D RT1 50 W 0 mA VoutLOADED LOW = VCC − 400 mV Q Z0 = 50 W 8 mA VCS ICS = 16 mA VEE Figure 5. CML Output (with Direct Connect Load Termination of 50 W per line to VCC), Currents and Levels (Q HIGH, Q LOW) CML Receiver VCC Loaded CML Output Driver VCC 8 mA RC2 50 W RC1 50 W VoutLOADED LOW = VCC − 400 mV Q 0 mA Q Z0 = 50 W D RT1 50 W 8 mA VoutLOADED HIGH = VCC Z0 = 50 W D RT2 50 W 0 mA 16 mA VCS VEE Figure 6. CML Output (with Direct Connect Load Termination of 50 W per line to VCC), Currents and Levels (Q LOW, Q HIGH) http://onsemi.com 3 AND8173/D With differential CML Output lines loaded and each terminated 50 W (RT) to VCC at the driver, the voltage levels present either a VoutLOADED HIGH level of VCC or VoutLOADED LOW of VCC − 800 mV at the receiver. An active complementary signal pair produces the characteristic parameters per Table 2. The driver 50 W RC is in parallel to the receiver 50 W (RT) to VCC, presenting a R(EQ) of 25 W to the active side’s constant 16 mA tail current, and will drop a total of about 400 mV below VCC as the VoutLOADED LOW. The complementary output side, VoutLOADED HIGH, has essentially no current flow, IOFF, remains near VCC. VoutLOADED HIGH + VCC * (IOFF @ R(EQ)) + VCC * 0 Table 2. CML DRIVER LEVELS (with Direct Connect Load Termination of 50 W to VCC) (eq. 3) VoutLOADED LOW + VCC * (ICS @ R(EQ)) + VCC * 400 Parameter (eq. 4) VoutLOADED HIGH Where: ICS = Constant Source Bias IOFF = Zero Current Side RC = Output Transistor Collector Resistor Unit VCC VoutLOADED CM VCC − 200 mV VoutLOADED LOW VCC − 400 mV VoutLOADED SE (Note 2) 400 mVpp VoutLOADED DIFF 800 mVpp 2. Each line measured single−ended. http://onsemi.com 4 Level AND8173/D SECTION 3. Cap Coupled (AC) CML LOAD TERMINATED 50 W PER LINE TO Vterm A driver and receiver using a cap, Cx, coupled (AC) differential interconnect and receiver side 50 W termination (RT) requires a DC receiver side rebiasing, Vterm, to the signal lines as shown in Figure 7. The coupling cap, Cx, value and the load impedance constitute an RC network affecting the signal edges. Cap coupling (AC) restricts low frequency response and may require coding to maintain a sufficient crossing density. This AC coupled pair in Figure 7 will produce characteristic signal levels per Table 3. Table 3. CML DRIVER LEVELS (with Cap Coupled Termination of 50 W per line to VCC) Parameter Receiver Level Unit Vterm + 200 mV Vterm mV VoutAC LOADED HIGH VoutAC LOADED CM VoutAC LOADED LOW Vterm − 200 mV VoutAC LOADED SE (Note 3) 400 mVpp VoutAC LOADED DIFF 800 mVpp 3. Each line measured single−ended. CML Receiver Vterm CML Driver VCC RC1 50 W RC2 50 W Q Q C2 Z0 = 50 W Z0 = 50 W C1 Z0 = 50 W Z0 = 50 W D RT2 50 W D RT1 50 W VoutACLOADED HIGH = Vterm +200 mV VCS VoutACLOADED LOW= Vterm −200 mV ICS = 16 mA VEE Figure 7. CML Output with Cap Coupling (AC) and Load Termination of 50 W to Vterm Vterm SUPPLY External Vterm The Vterm DC bias supply associated with the CML receiver in Figure 7 needs to accommodate the receiver common mode range and bypassed to enhance rejection of common mode noise. Typically, the Vterm bias supply may be connected directly from the receiver RT pins whether internal or external to the driver. When internal, the pin connect to the fixed value 50 W (RT) resistors may be singulated or combined. If external, the termination resistor (RT) value may be changed to accommodate the specific transmission line impedance. An external DC reference supply, Vterm, may be generated by a resistor divider network spanning from the VCC to VEE supplies, with appropriate bypass capacitance, CBP, as shown in Figure 8. Typically bypass capacitor value may range from 0.01 mF to 0.001 mF. Resistors R1 and R2 should generate an appropriate common mode voltage for the receiver. Current through R2 should be at least 10X the receiver typical input current for both lines. VCC R1 Vterm R2 CBP VEE Q CML Driver Q C2 C1 Z0 = 50 W RT2 50 W Z0 = 50 W RT1 50 W D Receiver D Figure 8. Typical Vterm Supply Divider Network http://onsemi.com 5 AND8173/D LVPECL receivers offer a wide range of accepted common mode value solutions for inputs operating in a differential interconnect. Selecting a common mode value of VCC − 1.3 V would satisfy any standard ECL receiver. Table 4 gives values for the typical pullup resistor to VCC (R1 or R1’), the pulldown resistor to VEE (R2 or R2’), and the resulting Vrebias voltage when using VCC − 1.3 common mode voltage and impedance matching to transmission media with Z0 = 50 W. Alternatively, a receiver without internal 50 W (RT) resistors may be terminated and DC biased by using a Thevenin parallel equivalent network. Both impedance matching and DC rebias are simultaneously accomplished by a solution of a R1 resistor to VCC and a R2 resistor to VEE as shown in Figure 9, on each of the complementary lines. See AND8020, Section 3 Thevenin Equivalent Parallel Termination for equations generating the values of R1 and R2. External Vterm VCC Q CML Driver C2 Z0 = 50 W R1 R1‘ D Vrebias Q C1 Z0 = 50 W Receiver Vrebias R2 D R2‘ VEE Figure 9. Thevenin Parallel Termination Scheme Table 4. Typical VCC − 1.3 REBIAS AND IMPEDANCE MATCHING RESISTOR NETWORK VALUES @ Z0 = 50 W Resistor |VCC − VEE |= 5.0 V |VCC − VEE | = 3.3 V |VCC − VEE | = 2.5 V Unit R1 (R1’) 68 83 96.15 W R2 (R2’) 192 127 104.16 W Vrebias 3.7 2.0 1.2 V http://onsemi.com 6 AND8173/D SECTION 4. CML INTERFACE INTERCONNECTS CML Driver Direct Connect (DC) to LVPECL typical LVPECL receiver input on similar power supplies. A direct (DC) interface interconnect is shown in Figure 10. The ON Semiconductor ECL Logic Devices with CML OUTPUT Structures easily interconnects directly (DC) to a LVPECL Receiver Vterm (Internal or External) CML Driver VCC RC1 50 W RC2 50 W Q Z0 = 50 W Q Z0 = 50 W D RT2 50 W D RT1 50 W VCS VoutLOADED HIGH = Vterm ICS = 16 mA VoutLOADED LOW = VCC − 400 mV VEE Figure 10. CML Output with Direct (DC) Interconnect and Termination of 50 W to Vterm Vterm supply. A lower Vterm supply affects the receiver VoutHIGH and VoutLOW levels. A typical On Semiconductor ECL Device with CML OUTPUT Structure, directly (DC) driving an internally terminated LVPECL input with various Vterm values, produces a characteristic swing amplitude, VoutPP (each line is measured single ended), and a common mode voltage, VoutCM, presented in Table 5. Both CML driver and LVPECL receiver were supplied VCC @ 3.3 V. Note the insensitivity of the output swing to changes in the Vterm supply as it ranges from VCC to VCC − 2.0 V, the typical VTT termination voltage for Emitter Follower ECL structures. A receiver may have either internal or external 50 W (RT) termination resistors, and these resistors may be singulated or combined for pinout. If external, the termination resistors (RT) value may be changed to accommodate the transmission line impedance. The Vterm supply (Figure 8) connects to the 50 W (RT) termination resistors and determines the receiver DC bias level. A proper Vterm DC bias must be selected for the receiver to comply with common mode specifications, such as VIHCMR or VCMR. Most devices will tolerate Vterm at VCC while others may spec a signal HIGH level, VIHmax (consult device data sheet) requiring an appropriately lower Table 5. CML DRIVER LEVELS (WITH DIRECT CONNECT TERMINATION OF 50 W PER LINE TO Vterm) VoutCM VoutHIGH VoutLOW VoutPP (Note 4) Unit 3.3 3.1 3.25 2.95 0.300 V 3.0 2.95 3.10 2.85 0.300 V 2.5 2.75 2.85 2.55 0.295 V 2.0 2.45 2.60 2.30 0.280 V Vterm 4. Each line measured single−ended http://onsemi.com 7 AND8173/D CML Driver Cap Coupled (AC) to Various Supplied ECL: PECL, LVPECL, LVNECL, NECL (AC) to ECL type receiver inputs operating with different supply modes such as shown in Figures 11, 12, and 13. A Vterm supply is used to DC bias the receiver input lines. See also Vterm Supply, Figure 8 and Table 4. The On Semiconductor ECL Devices with CML OUTPUT Structures easily interconnect with cap coupling Vterm = 5.0 V CML Driver VCC VCC = 5.0 V RC2 50 W RC1 50 W PECL Receiver Q Q RT2 50 W C2 Z0 = 50 W Z0 = 50 W RT1 50 W C1 Z0 = 50 W Z0 = 50 W D D VEE = 0 V VHIGH = 5.0 V +200 mV VLOW = 5.0 V −200 mV VCS ICS = 16 mA Figure 11. CML to PECL (VCC = Vterm = 5.0 V, VEE = 0 V) Vterm = 3.3 V CML Driver VCC RC1 50 W LVPECL Receiver VCC = 3.3 V RC2 50 W Q Q RT2 50 W C2 Z0 = 50 W Z0 = 50 W C1 Z0 = 50 W RT1 50 W Z0 = 50 W D D VEE = 0 V VHIGH = 3.3 V +200 mV VLOW = 3.3 V −200 mV VCS ICS = 16 mA Figure 12. CML to LVPECL (VCC = Vterm = 3.3 V, VEE = 0 V) http://onsemi.com 8 AND8173/D Vterm = 0 V CML Driver VCC 50 W NECL or LVNECL Receiver VCC = 0 V 50 W Q Q 50 W C2 Z0 = 50 W Z0 = 50 W 50 W C1 Z0 = 50 W Z0 = 50 W VEE = −5.0 V or −3.3 V VHIGH = 0 V +200 mV VLOW = 0 V −200 mV VCS Figure 13. CML to NECL (Vterm = 0 V, VEE = −5.0 V or −3.3 V) http://onsemi.com 9 AND8173/D CML Driver Cap Coupled (AC) to LVDS A CML Driver interconnect to an LVDS (LVDS, BLVDS, M−LVDS, GLVDS, or LVDM) compliant receiver requires a cap coupled (AC) interface. Typically, a 50 W (RT) per line impedance matching termination to Vterm is used as shown in Figure 14, and will produce a VHIGH of about 1.33 V, a VLOW of 1.0 V, with an amplitude of 330 mVpp (each line measured single−ended). The VCM is set to 1.2 V by the Vterm reference. If the two 50 W (RT) per line impedance matching termination resistors are external, the termination resistor scheme may be modified by using a Thevenin parallel scheme as shown in Figure 9. The Thevenin parallel impedance matching resistor network values and rebias voltage for an LVDS cap coupled receiver with Z0 = 50 W are given in Table 6. Table 6. LVDS IMPEDANCE MATCHING RESISTOR NETWORK VALUES AND REBIAS VOLTAGE Resistor |VCC − VEE| = 5.0 V |VCC − VEE| = 3.3 V |VCC − VEE| = 2.5 V Unit R1 (R1’) 210 138 104 W R2 (R2’) 66 79 96 W Vrebias 1.2 1.2 1.2 V CML Driver VCC 50 W LVDS Receiver 50 W 50 W Q 50 W Q Vterm = 1.2 V VHIGH = X1.33 V VLOW = X1.00 V VCS Figure 14. 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