IRFI7536GPbF
HEXFET® Power MOSFET
D
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
60V
2.7m:
3.4m:
86A
D
G
D
S
TO-220
Full-Pak
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C
IDM
PD @TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
VGS
TJ
TSTG
Gate-to-Source Voltage
Operating Junction and
Storage Temperature Range
c
EAS
IAR
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
EAR
Repetitive Avalanche Energy
Symbol
RθJC
RθJA
1
A
820
75
0.5
W
W/°C
V
°C
Avalanche Characteristics
Thermal Resistance
Units
86
73
± 20
-55 to + 175
300 (1.6mm from case)
10lbf in (1.1N m)
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
c
Max.
c
Parameter
ij
Junction-to-Case
Junction-to-Ambient (PCB Mount)
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x
d
x
738
See Fig. 14, 15, 22a, 22b
mJ
A
mJ
Typ.
Max.
Units
–––
–––
2.87
65
°C/W
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IRFI7536GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
gfs
RG
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Internal Gate Resistance
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
60
–––
–––
2.0
88
–––
–––
–––
–––
–––
–––
29
2.7
–––
–––
0.79
–––
–––
–––
–––
Conditions
–––
V VGS = 0V, ID = 250µA
––– mV/°C Reference to 25°C, ID = 1.0mA
3.4
mΩ VGS = 10V, ID = 75A
4.0
V VDS = VGS, ID = 150µA
–––
S VDS = 25V, ID = 75A
–––
Ω
20
µA VDS = 60V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 125°C
250
100
nA VGS = 20V
-100
VGS = -20V
c
f
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Min. Typ. Max. Units
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
130
31
42
88
22
77
55
64
6600
720
400
1080
1400
195
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
nC
Conditions
ID = 75A
VDS = 30V
VGS = 10V
ID = 75A, VDS =0V, VGS = 10V
VDD = 39V
ID = 75A
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 48V
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 48V , See Fig. 11
VGS = 0V, VDS = 0V to 48V
f
ns
pF
f
h
g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
86
A
MOSFET symbol
ISM
(Body Diode)
Pulsed Source Current
–––
–––
820
A
showing the
integral reverse
d
(Body Diode)
Diode Forward Voltage
Peak Diode Recovery
VSD
dv/dt
trr
e
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.26mH,
RG = 50Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 890A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS .
2
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–––
–––
–––
–––
–––
–––
–––
–––
3.3
43
53
58
65
2.4
1.3
–––
–––
–––
–––
–––
–––
D
G
p-n junction diode.
V TJ = 25°C, IS = 75A, VGS = 0V
V/ns TJ = 25°C, IS = 75A, VDS = 60V
ns TJ = 25°C
VR = 51V,
TJ = 125°C
IF = 75A
di/dt = 100A/µs
nC TJ = 25°C
TJ = 125°C
A TJ = 25°C
S
f
f
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
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IRFI7536GPbF
1000
1000
VGS
15V
12V
10V
6.0V
5.0V
4.75V
4.50V
4.25V
100
BOTTOM
VGS
15V
12V
10V
6.0V
5.0V
4.75V
4.50V
4.25V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
4.25V
10
BOTTOM
4.25V
10
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
1
0.01
0.1
1
10
100
0.01
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
100
2.2
T J = 175°C
T J = 25°C
10
VDS = 25V
≤60µs PULSE WIDTH
1.0
ID = 75A
VGS = 10V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 75A
C oss = C ds + C gd
C, Capacitance (pF)
1
Fig 2. Typical Output Characteristics
1000
10000
Ciss
Coss
Crss
1000
12.0
VDS= 48V
VDS= 30V
10.0
VDS= 12V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
3
0.1
V DS, Drain-to-Source Voltage (V)
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0
20
40
60
80 100 120 140 160 180
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFI7536GPbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
1000
1msec
100
10msec
10
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.0
0.1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.1
VSD, Source-to-Drain Voltage (V)
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID, Drain Current (A)
80
50
100
72
ID = 1.0mA
70
68
66
64
62
60
-60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C)
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
2.0
EAS , Single Pulse Avalanche Energy (mJ)
3000
1.8
ID
8.6A
12A
BOTTOM 75A
TOP
2500
1.6
1.4
Energy (µJ)
10
Fig 8. Maximum Safe Operating Area
100
25
1
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
2000
1.2
1.0
1500
0.8
1000
0.6
0.4
0.2
0.0
500
0
0
10
20
30
40
50
60
70
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100µsec
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25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFI7536GPbF
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Avalanche Current (A)
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τj = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
tav (sec)
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
800
700
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 75A
600
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
5
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4.0
16
3.5
14
3.0
12
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
IRFI7536GPbF
2.5
2.0
ID = 150µA
ID = 1.0mA
1.5
IF = 30A
V R = 51V
TJ = 25°C
TJ = 125°C
10
8
6
ID = 1.0A
4
1.0
2
0.5
-75
-25
25
75
125
0
175
200
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
500
16
IF = 45A
V R = 51V
14
IF = 30A
V R = 51V
400
TJ = 25°C
TJ = 125°C
QRR (nC)
12
IRRM (A)
400
diF /dt (A/µs)
T J , Temperature ( °C )
10
8
TJ = 25°C
TJ = 125°C
300
200
6
100
4
2
0
0
200
400
600
800
1000
0
200
400
600
800
1000
diF /dt (A/µs)
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
500
IF = 45A
V R = 51V
QRR (nC)
400
TJ = 25°C
TJ = 125°C
300
200
100
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFI7536GPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
7
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
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IRFI7536GPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRFI7536GPbF
Qualification information†
Cons umer
Qualification level
Moisture Sensitivity Level
(per JE DE C JE S D47F
TSOP-6
RoHS compliant
†
††
†††
††
†††
guidelines )
MS L1
†††
(per IPC/JE DE C J-S T D-020D
Yes
)
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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