AND8078/D A Simple Low-Cost Non-Isolated Universal Input Off-Line Converter Prepared by: Roland Saint–Pierre Field Applications Engineer http://onsemi.com APPLICATION NOTE INTRODUCTION Switch–mode off–line power conversion typically entails a means of galvanic isolation from primary to secondary. In most instances it includes a step–down high frequency transformer, which aids in the voltage conversion necessary from the high DC bulk voltage generated from the bridge rectifier to the lower output DC voltage required by the end application. If isolation is not a requirement of the application, in which safety can be insured by mechanical means, the additional cost of the transformer and opto–coupler can be saved. The circuit describe herein is proposed as a simple and low cost means to convert the AC mains voltage to a lower DC voltage which may be used in R1 include a Circuit Description The circuit shown below is a very low cost, universal AC input, non–isolated converter employing a buck–boost topology. The simple half–wave rectified AC input provides a DC voltage to the bulk capacitor (C1), which is then converted, to the semi–regulated DC voltage required on the output. For this power level an LC –filter was chosen to meet conducted EMI requirements. This example describes the design and analysis of a converter providing 8.0 VDC at 0.4 A. C6 2.2 D2 1N5924B 9.1 V 680 pF R3 L1 2.2 H D1 a variety different applications which pre–regulator for a linear voltage regulator. 220 + D3 1N4937 1N4006 C1 10 F 400 V C2 10 F 400 V U1 L3 120 H 8 HV 100–250 VAC 50/60 Hz NCP1200P60 C3 470 pF 2 GATE Q2 2N3904 L2 2.2 H R2 2.2 8 VDC @ 0.4 A VCC 6 C4 0.01 F 5 IS 3 C7 100 F 10 V GND 4 C6 22 F Q1 R4 C5 220 pF 1 kV STD2NB60 – 1 Figure 1. Non–Isolated Universal Input Buck–Boost Converter Employing the 60 kHz–NCP1200 Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 0 1 Publication Order Number: AND8078/D AND8078/D NCP1200 At the heart of the converter is the NCP1200 off–line current–mode PWM converter IC. This controller features a Dynamic Self–Supply (DSS) that allows it to be powered directly from the high voltage rectified line voltage. This IC Adj 8 1 HV Current Source 75.5 k FB also features a current–mode controller with skip cycle capability, an internally set fixed frequency oscillator (available in 40 kHz, 60 kHz and 100 kHz), extremely low no–load standby power, and built–in frequency jittering for reduced EMI. 1.4 V + 2 HV Skip Cycle Comparator UVLO High and Low Internal Regulator Internal VCC - 7 NC 29 k Current Sense Ground 8k 4 + - Vref 5.3 V Q Flip–Flop DCmax = 80% Q 6 Reset VCC + 60 k 20 k Set 40, 60 or 100 kHz Clock 250 ns L.E.B. 3 5 1V Drv ±110 mA Overload? Fault Duration Figure 2. NCP1200 – Internal Circuit Architecture Buck–Boost Topology The basic Buck–Boost topology, shown below in Figure 3, is typically attributed as an inverting circuit since the output has the reverse polarity of the input voltage. More commonly the isolated version of this converter (Flyback) is used. with two or more winding and repositions the switch to the low side to facilitate gate drive, which reveals the more common off–line circuit topology. PWM PWM Figure 4. Flyback Converter The converter shown in Figure 1 is essentially the same topology as Figure 3 except that the switching device has been placed on the bottom rail and the polarity of the input and output voltage has been reversed to produce a positive output voltage from a negative input source. Figure 3. Buck–Boost Topology The magnetic element in the Flyback converter simply replaces the inductor in Figure 3 with a coupled inductor http://onsemi.com 2 AND8078/D Derivation of the Output Characteristic Equation This converter was designed to operate in discontinuous conduction mode (DCM). As with all switched–mode converter topologies the characteristics equation relating the input to output voltage made be derived from a fundamental analysis of the topological modes of the converter. The modes of the converter are examined by redrawing the circuit for each of the distinct cases of conduction of the active and passive switches. information can be used to derive the input–output voltage characteristic equation that is valid for both continuous and discontinuous conduction–mode. Vin · ton Vo · toff (1) Vo ton Vin toff (2) Idealized converter waveforms for the all the pertinent active and passive devices are shown in Figure 6. The average diode current (ID) is the output load current (Io); an expression for the output current may be derived as: MODE I Io toff · Ipk 2 · Ts (3) Where Ts is the switching period, and Ipk is given as: Ipk Vin · ton L (4) Combining terms and rearranging equation (3) and (4), we can solve the “off–time” as a function of input voltage (Vin), switch “on–time” (ton ), switching period (Ts), inductance (L) and load current (Io). MODE II toff 2 · Ts · L · Io Vin · ton (5) The “off–time” can also be expressed as a function of the switching period (Ts), inductance (L) and load resistance (Ro). Simply substitute Ipk from equation (4) into the equation for Io; equation (3), which yields: t ·t Io Vin · on off 2 · Ts · L MODE III (6) Solving for |Vin| in equation (2) and substituting it into (6) yields: Io Vo · toff 2 · 1 2 · Ts · L (7) Rearranging (7) and substituting Ro for Vo/Io, we find that the “off–time” may be expressed as: toff Figure 5. Topological Modes of the Buck–Boost Converter in DCM Ts · L 2 · Ro (8) Another essential parameter of this converter is the duty cycle (αD), which is the ratio of “on–time” to the switching period (ton /Ts). The equation for the duty cycle is by solving for the “on–time” in equation (2), and substituting the result of toff from equation (5): In DCM, there are three distinct operating modes. In mode I, the switch is “on” and the input source is connected to the inductor, the output load is supported by the output capacitor since the rectifier in this case is reverse–biased. During mode II, the main switch (Q1) is turned off and the inductor voltage acts as a source polarity switch and reverses it voltage. This in turns causes D1 to conduct and the load current is supported by the stored energy in the inductor. In the third mode, neither the switch nor diode is conducting since the inductor current has fallen to zero. In equilibrium the volt–time product across the inductor during the first two modes must be equal (shaded regions on Figure 6), this D 1 · Vin 2 · VoTs· Io · L (9) Since, α = ton / Ts and (1–α) is toff / Ts, the expression for the duty–cycle (αC) of a buck–boost converter is continuous conduction mode (CCM) is load independent and may be derived from (2) as: C http://onsemi.com 3 Vo Vin Vo (10) AND8078/D Input Stage Design A half–wave rectified input stage was selected to reduce cost and overall part count. This basic circuit comprises of a standard recovery rectifier and single high voltage capacitor. The only constraint of this circuit is peak–to–peak voltage ripple on the bulk capacitor and its affect on the output. A smaller bulk capacitor will allow higher 120 Hz ripple on the DC bulk voltage and depending on the loop dynamics a higher amount of this frequency component on the output voltage. Using the technique outlined in [1], we find that a total bulk capacitance of 20 F will suffice for this circuit. Please note that a capacitor of with roughly half of this capacitance would have been required had we opted to use a full bridge rectifier. Figure 7 shows the PSPICE simulation results for the bulk capacitor voltage with a half–wave rectified input source at 100 VAC/60 Hz into the input filter arrangement shown in Figure 1 with a constant 4.7 W load (assumes 75% efficiency). The following chart tabulates the results of this simulation for high and low line conditions maximum rated load. Ipk Drain Current Ipk Diode Current Inductor Current Vin + Vo ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Table 1. Input Filter Simulation Summary Vin Drain–Source Voltage Vo Vin 100 VAC/60 Hz 250 VAC/50 Hz Vmin 78.3 V 339 V Vmax 112.8 V 352.2 V VavgDC 96.4 V 344.7 V Inductor Voltage –Vin ton toff td TS Figure 6. Idealized Converter Waveforms 120 110 V(VDC) 100 90 80 70 32 36 40 44 48 TIME (ms) 52 56 60 Figure 7. Simulation Plot of the Bulk DC Capacitor at Low Line http://onsemi.com 4 64 AND8078/D Current Sense Resistor Again using the guidelines from [1], we find that a suitable value for the sense resistor is 1.0 Ω. The peak switch current limit neglecting the propagation delay of the NCP1200 will be approximately 0.9 V/1.0 Ω = 0.9 A. This value is confirmed in the simulation results and breadboard example of the circuit, which are discussed in subsequent sections. DC Analysis The expected duty cycle of the converter can be computed over the operating line range using the expressions we derived above. The converter can be expected to operate over a relatively broad range of duty–cycles, which span the expected line and load range. At no–load and light load conditions, the NCP1200 will enter into a skip–cycle mode whereby the input power and peak current limit will be significantly reduced. The inductor value was chosen to maintain DCM operation for all operating conditions. An expression for the critical inductance (inductance value at the border between CCM and DCM) may be derived from solving for L in equation 8: Lc Vo · (1 )2 · Ts Io Device Selection The only design constraints for the MOSFET are its drain–source voltage and drain current ratings. For this design, the minimum VDS rating is VinMAX + Vo = 353 + 8 = 361 V, and minimum drain current rating of 1.0 Apk. The breadboard example utilizes a ST–Micro STD2NB60E, which has a VDS rating of 600 V, ID = 2.2 A with an rDSon of 3.6 Ω. The output rectifier must be rated to handle the average output load current of 0.4 A, a peak current of 0.9 A, and a breakdown voltage of 293 V. A low cost leaded ultrafast rectifier (1N4937) was chosen, which is rated at 600 V/1.0 A. (11) Solving the critical inductance equation above for low line conditions (Vin = 96.4 VDC) and our load current and output voltage, we find that the desired inductance to remain in DCM must be less than 142 H. Using this inductance will cause the converter to operate at critical conduction–mode; the operating duty cycle (α) at low line is 7.7% (ton = 1.28 sec). The design value of the inductor in this example was chosen to be 120 H. We can also find that the peak switch and inductor current will stay relatively constant over the line range at our rated load. The peak switch current using an inductance of 120 H (not accounting for circuit losses) is 0.94 A. Output Voltage Regulation The output voltage of this converter is regulated using a zener diode and NPN transistor. The output voltage is the zener voltage + the Vbe voltage–drop of the transistor. A more precise output voltage can be achieved using a TL431, which will also allow traditional loop compensation techniques. Figure 8 depicts a possible implementation of the TL431 shunt regulator for precise output voltage regulation. + 1N4937 3 k 120 H 100 F 8 HV NCP1200P60 18.7 k 200 k 680 pF 2 VCC 6 GATE 0.01 F 5 IS 3 8 VDC @ 0.4 A GND 4 22 F TL431 8.45 k MTP1N60E 1 220 pF 1 kV Figure 8. TL431 Implementation for Precise Output Voltage Regulation http://onsemi.com 5 – AND8078/D Simulation Results The following plots are results of a transient simulation performed on PSPICE. The simulation schematic is shown in Figure 9, followed by plots of the output voltage, drain–source voltage, current sense resistor voltage and inductor current. Compensating the zener regulator can be achieved by adding an RC network from collector to base of the transistor and/or adding a parallel capacitor to the resistor which is between the zener and transistor base. This resistor not only sets the bias conditions for the transistor and zener, but also sets the open–loop gain of the circuit. The additional capacitor across the base–collector of the transistor will help roll off its inherent high frequency gain and more importantly the converter. D7 Vin Vout D1N4937 – V1 + D19 D1N5242 C1 100 F, IC = –8 353 R5 20 HV 2 U1 Vfb C6 470 p C4 1n adj 1 2 8 Isns 3 6 5 4 L1 120 H gate C2 22 F, IC = –12.1 NCP1200 NCP1200 FS = 60 k fbe Q1 Q2N3904 0 1 Vcc R1 1 R3 0.2 M1 MTD1N60E R2 C5 1 0 220 p Figure 9. PSPICE Simulation Schematic http://onsemi.com 6 R4 0.1 C3 680 p R6 220 AND8078/D 1 1.0V 2 8.0V I(L1) 0.8V V(VOUT) 0.6V 7.5V 0.4V 7.0V 0.2V V(ISNS) 0V 6.5V 327 330 340 350 360 370 380 TIME (s) Figure 10. Simulation Results – Output Voltage, Current Sense Voltage, and Inductor Current Vin = 96.4 VDC, Ro – 20 120V 100V V(HV,ISNS) 80V 60V 40V 20V 0V 370 375 380 385 390 395 400 405 TIME (s) Figure 11. Simulation Results – MOSFET Drain–Source Voltage Vin = 96.4 VDC, Ro – 20 http://onsemi.com 7 410 415 AND8078/D 1 9.0V 2 1.4V V(VOUT) 1.0V 8.5V 0.5V 8.0V I(L1) V(ISNS) 0V 7.5V –0.2V 423.2 430.0 440.0 450.0 460.0 470.0 TIME (s) Figure 12. Simulation Results – Output Voltage, Current Sense Voltage, and Inductor Current Vin = 353 VDC, Ro – 20 380V 300V 200V 100V 0V 380.0 384.0 388.0 392.0 396.0 400.0 404.0 408.0 412.0 TIME (s) Figure 13. Simulation Results – MOSFET Drain–Source Voltage Vin = 353 VDC, Ro – 20 http://onsemi.com 8 416.0 AND8078/D Actual Hardware Oscillographs and Performance Summary The circuit shown in Figure 1 was built to validate the analysis and verify operating specifications. The following plots show the output voltage at full load and no–load, as well as the drain–source voltage, current sense resistor voltage, and bulk DC voltage at full load. A figure showing regulation voltage over the line and load range is shown in Figure 18. Figure 14. Hardware Oscillograph – Current Sense Resistor Voltage Vin = 100 VAC/60 Hz, Ro – 20 Figure 15. Hardware Oscillograph – VD Voltage Waveform Vin = 100 VAC/60 Hz, Ro – 20 Figure 16. Hardware Oscillograph – Output Voltage Vin = 100 VAC/60 Hz, Ro – 20 Figure 17. Hardware Oscillograph – Bulk DC Voltage with Respect to Circuit GND Vin = 100 VAC/60 Hz, Ro – 20 http://onsemi.com 9 AND8078/D 8.75 OUTPUT VOLTAGE (VDC) 8.65 85 VAC/60 Hz 120 VAC/60 Hz 8.55 8.45 2.0 mA 8.35 50 mA 8.25 240 VAC/60 Hz 10 mA 8.15 265 VAC/60 Hz 200 mA 8.05 7.95 7.85 400 mA 7.75 0 50 100 150 200 250 300 350 400 450 500 550 LOAD RESISTANCE () Figure 18. Hardware Operating Characteristics (Line/Load Regulation) PCB The complete bill of material and PCB component silkscreen and artwork layers are shown for the NCP1200 design example. The PCB is a single sided CEM1 chosen for its low manufacturing cost. BILL OF MATERIAL Ref Des Part No. R1, R2 – R3 Part Description Manufacturer Geometry 2.2 1/4 W Metal Film Leaded – Axial – 220 , 1/8 W Metal Film Leaded – Axial R4 – 1.0 , 1/2 W – Axial C1, C2 URS2G100MHA Nichicon 16 x 15 mm C3 – 470 pF, 50 V, Monolithic Ceramic Disc – – C4 – 0.01 F, 50 V, Monolithic Ceramic Disc – – C5 – 220 pF, 1.0 kV, Monolithic Ceramic Disc – – C6 UHC1C220MDR 22 F, 16 V, Alum. Electrolytic Nichicon 5 x 7 mm C7 UHC1C101MDR 100 F, 16 V, Alum. Electrolytic Nichicon 6.3 x 11 mm L1, L2 9130–28 2.2 H, 395 mA, RDC = 0.4 , Axial Leaded Molded RF Choke JW Miller Magnetics www.jwmiller.com Axial L3 – – – D1 1N4006 Standard Recovery 800 V, 1.0 A On Semiconductor Case 59–03 D2 1N5924B Zener Voltage Regulator, 9.1 V, 3.0 W On Semiconductor Case 59–04 D3 1N4937 Fast Recovery Diode, 600 V, 1.0 A On Semiconductor Case 59–03 Q1 STD2NB60 N–Channel MOSFET, 600 V/3.6 STMicroelectronics I–PAK Q2 2N3904A General Purpose, NPN, 30 V/100 mA On Semiconductor TO–92 U1 NCP1200 Off–Line Current Mode PWM Controller IC On Semiconductor DIP–8 10 F, 400 V, Alum. Electrolytic 120 H, 1.5 A http://onsemi.com 10 AND8078/D TP1 D1 W1 L1 C2 C1 R1 TP5 TP3 R4 TP7 L2 TP2 R3 D2 TP9 C5 C3 JP1 Q2 C4 U1 R2 TP4 C7 TP11 TP12 TP13 C5 TP6 TP10 D3 L3 C6 W2 W4 W3 TP6 Q1 REV A ONS 1001 Figure 19. PCB Silkscreen and Artwork Alternate Embodiment The circuit shown in Figure 1 is a non–isolated off–line converter with a key deficiency is some applications, in the fact that both the line (hot) and neutral AC inputs are switched. The MOSFET drain (switching node) is connected to the neutral and the line (hot) is tied to a rectifier, necessary to develop the required DC voltage for conversion. This configuration has potentially serious safety issues. For safety, the circuit shown below maintains a ground referenced neutral line and which is common to the output return. + Line (Hot) 3 CS 5 DRV 2 FB + NCP1200 + GND VCC 4 6 HV 8 + Nuetral AC – (GND) Figure 20. common–mode voltage potentials between the output and FB pin of the control IC. This is due to the fact that the NCP1200 is now referenced to the rectified AC line (hot). In this circuit transformation, the MOSFET source is tied to the line and the neutral is at ground potential. In order to regulate the output voltage, an opto–coupler must be used in the feedback loop to overcome differences in the http://onsemi.com 11 AND8078/D Conclusion This paper detailed the design and analysis, including device selection criteria, for a non–isolated off–line buck–boost converter. The NCP1200 series offers sufficient R1 D1 1N4006 C1 10 F 400 V 100–250 VAC 50/60 Hz flexibility to configure this topology for various output voltage and power requirements. Alternatively, the NCP105x series of off–line gated–oscillator ICs may also be used in this topology. C6 2.2 R3 L1 2.2 H 220 + D3 1N4937 C2 10 F 400 V L2 2.2 H D2 1N5924B 9.1 V 680 pF U1 2 Control NCP1052B C4 0.01 F Q2 2N3904 5 L3 120 H VCC 1 C6 22 F C7 100 F 10 V 8 VDC @ 0.1 A 3, 6–8 Switch GND – R2 2.2 Figure 21. Adaptation with the NCP1052B Acknowledgments The NCP105x series feature an on–chip 700 V power switch, a unique dual–edge gated oscillator for extremely fast loop response, high voltage start–up and operation, frequency dithering for reduced EMI filtering, and an internally set frequency options (44, 100 and 136 kHz). The distinct advantage of this IC in this converter is the lower overall part count since the MOSFET and current sensing resistor are internalized. The NCP105x series and its derivatives are offered in a wide variety and combinations of switching frequency and peak current limits. In either case whether it be a NCP1200 or NCP105x, the key features and attributes of these ICs make them uniquely suitable to configure this topology for very low cost off–line power conversion. The author would like to acknowledge Douglas K. Thomson, Sr. Design Engineer with ABB Automation Inc., in Raleigh, NC, for inspiring this application note as well as the insightful conversions relating to this topic. References 1. AN8023/D, “Implementing the NCP1200 in Low–Cost AC/DC Converters”, Christophe Basso, October 2000. 2. AN8038/D, “Implementing the NCP1200 in a 10W AC/DC Wall Adapter”, Christophe Basso, October 2000. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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