PD - 95369A
IRFR2405PbF
IRFU2405PbF
Surface Mount (IRFR2405)
l Straight Lead (IRFU2405)
l Advanced Process Technology
l Dynamic dv/dt Rating
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
l
HEXFET® Power MOSFET
D
VDSS = 55V
RDS(on) = 0.016Ω
G
Seventh Generation HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
ID = 56A
S
D-Pak
IRFR2405
I-Pak
IRFU2405
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
56
40
220
110
0.71
± 20
130
34
11
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
1.4
50
110
°C/W
* When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to application note #AN-994
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1
12/03/04
IRFR/U2405OPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
–––
–––
2.0
30
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
0.052 ––– V/°C Reference to 25°C, ID = 1mA
0.0118 0.016
Ω
VGS = 10V, ID = 34A
––– 4.0
V
VDS = 10V, ID = 250µA
––– –––
S
VDS = 25V, ID = 34A
––– 20
VDS = 55V, VGS = 0V
µA
––– 250
VDS = 44V, VGS = 0V, TJ = 150°C
––– 200
VGS = 20V
nA
––– -200
VGS = -20V
70 110
ID = 34A
16
23
nC
VDS = 44V
19
29
VGS = 10V
15 –––
VDD = 28V
130 –––
ID = 34A
ns
55 –––
RG = 6.8Ω
78 –––
VGS = 10V
D
Between lead,
4.5 –––
6mm (0.25in.)
nH
G
from package
7.5 –––
and center of die contact
S
2430 –––
VGS = 0V
470 –––
pF
VDS = 25V
100 –––
ƒ = 1.0MHz, See Fig. 5
2040 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
350 –––
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
350 –––
VGS = 0V, VDS = 0V to 44V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.22mH
R G = 25Ω, IAS = 34A.
ISD ≤ 34A, di/dt ≤ 190A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 56
showing the
A
G
integral reverse
––– ––– 220
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 34A, VGS = 0V
––– 62
93
ns
TJ = 25°C, IF = 34A
––– 170 260
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A
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IRFR/U2405PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
100
100
4.5V
4.5V
20µs PULSE WIDTH
TJ = 25 °C
10
0.1
1
10
10
0.1
100
Fig 1. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
2.5
TJ = 25 ° C
TJ = 175 ° C
100
V DS = 25V
20µs PULSE WIDTH
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
5.0
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
10
4.0
20µs PULSE WIDTH
TJ = 175 ° C
10.0
ID = 56A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U2405OPbF
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
3200
Ciss
2400
1600
800
Coss
20
VGS , Gate-to-Source Voltage (V)
4000
ID = 34A
VDS = 44V
VDS = 27V
VDS = 11V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
Crss
0
1
10
0
100
0
VDS , Drain-to-Source Voltage (V)
60
80
100
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
40
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10
V GS = 0 V
0.8
10us
100
TJ = 175 ° C
TJ = 25 ° C
1
0.4
1.2
1.6
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
20
2.4
100us
10
1ms
TC = 25 ° C
TJ = 175 ° C
Single Pulse
1
1
10ms
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U2405PbF
60
V DS
LIMITED BY PACKAGE
VGS
50
D.U.T.
RG
I D , Drain Current (A)
RD
+
-VDD
40
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
30
Fig 10a. Switching Time Test Circuit
20
VDS
10
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
PDM
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
IRFR/U2405OPbF
240
TOP
200
BOTTOM
160
120
80
40
0
25
tp
ID
14A
24A
34A
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
QGS
QGD
12V
.2µF
.3µF
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
6
Fig 13b. Gate Charge Test Circuit
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IRFR/U2405PbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFR/U2405OPbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRF R120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 1999
IN T HE AS S EMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in ass embly line position
indicates "Lead-F ree"
IRFU120
12
916A
34
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
IRF U120
12
AS S EMBLY
LOT CODE
8
34
DAT E CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 16
A = AS S EMBLY S IT E CODE
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IRFR/U2405PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H ASSEMBLY
LOT CODE 5678
ASSE MBLE D ON WW 19, 1999
IN T HE ASSEMBLY LINE "A"
PART NUMBER
INTE RNAT IONAL
RECT IF IER
LOGO
IRFU120
919A
56
78
ASSEMBLY
LOT CODE
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
PART NUMBE R
INT ERNAT IONAL
RECTIF IER
LOGO
IRFU120
56
AS SEMBLY
LOT CODE
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78
DATE CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WE EK 19
A = ASS EMBLY SIT E CODE
9
IRFR/U2405OPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/