Key Steps to Design an Interleaved PFC Stage Driven by the NCP1631

AND8407/D
Key Steps to Design an
Interleaved PFC Stage
Driven by the NCP1631
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APPLICATION NOTE
Furthermore, if the two stages are operated out-of-phase,
the current ripple is significantly reduced. In particular, the
input current looks like that of a Continuous Conduction
Mode (CCM) one and the rms current within the bulk
capacitor is dramatically reduced. These characteristics are
detailed in application note AND8355 [1].
This paper gives the main equations that are useful to
design an interleaved PFC stage driven by the NCP1631.
The process is illustrated by the following 300-W, universal
mains application:
 Maximum Output Power: 300 W
 Input Voltage Range: from 90 Vrms to 265 Vrms
 Regulation Output Voltage: 390 V
Interleaved PFC is an emerging solution that becomes
particularly popular in applications where a strict form
factor has to be met like for instance, in slim notebook
adapters or in LCD TVs. Interleaving consists in paralleling
two “small” stages in lieu of a bigger one, which may be
more difficult to design. Practically, two 150-W PFC stages
are combined to form our 300-W PFC pre-regulator. This
approach has several merits like the ease of implementation,
the use of more but smaller components or a better heat
distribution.
Also, Interleaving extends the power range of Critical
Conduction Mode (CrM) that is an efficient and
cost-effective technique (no need for low trr diodes). Even,
as reported by NCP1631EVB/D [3], when associated to the
Frequency Clamped Critical conduction Mode (FCCrM),
this technique yields particularly high efficiency levels
(about 95% over a large load range at 90 Vrms in a 300-W
application).
The computations relevant to the power components are
based on the assumption that the current is perfectly shared
between the two branches. This assumption is valid if the
two coil inductances properly match [2].
Vin
Vout
Rbo1
Rovp1
Vaux2
Rfb1
Rfb2
Rt
OVPin
AC Line
Rbo2
Rovp2
EMI
F ilte r
Cin
Rzcd2
1
16 Rzcd1
2
15
3
14 pfcOK
Cosc
4
13
Cp
5
RFF 6
12
7
10
8
9
Rz
Cbo2
Icoil1
Cz
OVPin
11
Rocp
Vcc
L2
L1
Vaux2
D1
M1
Icoil2
Vout
D2
LOAD
M2
Cbulk
+
Rsense
Iin
The “pfcOK” signal enables the downstream
converter when the PFC is ready
Figure 1. Generic Application Schematic
 Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. 2
1
Publication Order Number:
AND8407/D
AND8407/D
INTRODUCTION
A “pfcOK” Signal
The NCP1631 integrates a dual MOSFET driver for
interleaved, 2-phase PFC applications. It drives the two
branches in so-called Frequency Clamped Critical
conduction Mode (FCCrM) where each phase operates in
Critical conduction Mode (CrM) in the most stressful
conditions and in Discontinuous Conduction Mode (DCM)
otherwise, acting as a CrM controller with a frequency
clamp (given by the oscillator). According to the conditions,
the PFC stage actually jumps from DCM to CrM (and vice
versa) with no discontinuity in operation and without
degradation of the current shape.
Furthermore, the circuit incorporates protection features
for a rugged operation together with some special circuitry
to lower the power consumed by the PFC stage in no-load
conditions. More generally, the NCP1631 is ideal in systems
where cost-effectiveness, reliability, low stand-by power
and high power factor are the key parameters:
The circuit detects when the PFC stage is in steady state
or if on the contrary, it is in a start-up or fault condition. In
the first case, the “pfcOK” pin (pin15) is in high state and
low otherwise. This signal is to disable the downstream
converter unless the bulk capacitor is charged and no fault
is detected. Finally, the downstream converter can be
optimally designed for the narrow voltage provided by the
PFC stage in normal operation.
Safety Protections
The NCP1631 permanently monitors the input and output
voltages, the input current and the die temperature to protect
the system from possible over-stresses and make the PFC
stage extremely robust and reliable. In addition to the
aforementioned OVP protection, one can list:
Maximum Current Limit:
The circuit permanently senses the total input current and
prevents it from exceeding the preset current limit, still
maintaining the out-of-phase operation.
Fully Stable FCCrM and Out-Of-Phase Operation
Unlike master/slave controllers, the NCP1631 utilizes an
interactive-phase approach where the two branches operate
independently. Hence, the two phases necessarily operate in
FCCrM, preventing risks of undesired dead-times or
continuous conduction mode sequences. In addition, the
circuit makes them interact so that they run out-of-phase.
The NCP1631 unique interleaving technique substantially
maintains the wished 180 phase shift between the 2
branches, in all conditions including start-up, fault or
transient sequences.
In-rush Detection:
The NCP1631 prevents the power switches turn on for the
large in-rush currents sequence that occurs during the
start-up phase.
Under-Voltage Protection:
This feature is mainly to prevent operation in case of a
failure in the OVP monitoring network (e.g., bad
connection).
Optimized Efficiency Over the Full Power Range
Brown-Out Detection:
The circuit stops operating if the line magnitude is too low
to protect the PFC stage from the excessive stress that could
damage it in such conditions.
The NCP1631 optimizes the efficiency of your PFC stage
in the whole line/load range. Its clamp frequency is a major
contributor at nominal load. For medium and light load, the
clamp frequency linearly decays as a function of the power
to maintain high efficiency levels even in very light load.
The power threshold under which frequency reduces is
programmed by the resistor placed between pin 6 and
ground. To prevent any risk of regulation loss at no load, the
circuit further skips cycles when the error amplifier reaches
its low clamp level.
Thermal Shutdown:
The circuit stops pulsing when its junction temperature
exceeds 150C typically and resumes operation once it
drops below about 100C (50C hysteresis).
Fast Line/Load Transient Compensation
Characterized by the low bandwidth of their regulation
loop, PFC stages exhibit large over and under-shoots when
abrupt load or line transients occur (e.g. at start-up). The
NCP1631 dramatically narrows the output voltage range.
First, the controller dedicates one pin to set an accurate
Over-Voltage Protection level and interrupts the power
delivery as long as the output voltage exceeds this threshold.
Also, the NCP1631 dynamic response enhancer drastically
speeds-up the regulation loop when the output voltage is
4.5% below its desired level. As a matter of fact, a PFC stage
provides the downstream converter with a very narrow
voltage range.
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AND8407/D
POWER COMPONENTS
Defining the oscillator frequency of the NCP1631 is a
prerequisite step before dimensioning the PFC stage. In the
presented application, we choose to clamp the switching
frequency at around 120 kHz in each phase, because this
frequency is generally a good trade-off when considering
the following aspects:
 A high switching frequency reduces the size of the
storage elements. In particular, it is well known that the
higher the switching frequency, the lower the inductor
core. That is why, one should set the switching
frequency as high as possible,
 On the other hand, increasing the switching frequency
has two major drawbacks:
1. The switching rate increasing, the associated
losses grow up. In addition, all parasitic capacitors
charge at a higher frequency and generate more
heat...
2. EMI filtering is tougher: the switching generates
high EMI rays at the switching frequency and
close harmonic levels. Most power supplies have
to meet the CISPR22 standard that applies to
frequencies above 150 kHz. That is why SMPS
designers often select FSW = 130 kHz so that the
fundamental keeps below 150 kHz and then out of
the regulation scope. Often, 65 kHz is also chosen
to not to have to damp harmonic 2 too.
Where:
(Vin,rms)LL is the lowest line rms voltage
(Pin,avg)max is the maximum level of the input average
power
Vout,nom is the nominal output voltage (regulation level)
In our application,
(Vin,rms)LL = 90 V
Vout,nom = 390 V
(Pin,avg)max = 325 W (assuming a 92 % global efficiency
that is a conservative value that offers some margin)
As aforementioned, the frequency clamp for the two
branches is set to about 120 kHz. The inductor must be large
enough so that Critical conduction Mode is obtained at low
line, full load where the conditions are the most severe.
This constraint leads to the equation below (where
fsw(max) is the 120-kHz clamp frequency):
Lw
Lw
ǒIL(pk)Ǔ
MAX
+
ǒVin(rms)Ǔ
P bridge +
MAX
ǒIL(pk)Ǔ
Ǹ6
Ǔ
2
I M(rms) +
@
Ǹ3
(eq. 1)
LL
MAX
(eq. 4)
(P in,avg) max
4 Ǹ2
@ Vf @
^
p
(V
)
in(rms) LL
(eq. 5)
Assuming a 1-V forward voltage per diode (Vf = 1 V), the
bridge approximately dissipates 6.5 W.
For each branch, the MOSFET is selected based on the
peak voltage stress (Vout(max) + margin) and on the rms
current flowing through it (IM(rms)):
+
ǒ
325
Ǔ
(P in,avg) max
Ǹ3 @ 90
2
(V in(rms)) LL
@
@
Ǹ
1*
8 @ Ǹ2 @ (V in(rms)) LL
Ǹ
3 @ p @ V out,nom
Ǹ
1 * 8 @ 2 @ 90 ^ 1.8 A
3 @ p @ 390
+
(eq. 6)
Using a 600-V, 0.4-W FET (SPP11N60), will give
conduction losses of (assuming that RDS(on) increases by
80% due to temperature effects):
And:
+
^ 139 mH
^ 1.8 @ V f @ 325 ^ 6.5 @ V f
90
Ǹ2 @ 325
+
^ 5.1 A
90
ǒIL(rms)Ǔ
325 @ 390 @ 120 @ 10 3
The bridge diode should be selected based on the peak
current rating and the power dissipation given by:
(Pin,avg) max
+
90 2 @ ǒ 390 * (Ǹ2 @ 90) Ǔ
Power Semiconductors
In CrM and in FCCrM (assuming CrM operation at low
line, full load), the (maximum) peak and rms inductor
currents within one branch are:
2
(eq. 3)
Finally, a 150 mH/6 Apk/2.5 Arms coil was selected.
Inductor Selection
ǒ
(P in,avg) max @ V out,nom @ f sw(max)
In our application, this leads to:
The oscillator frequency is the double of the clamp
frequency in each phase. The oscillator frequency is then set
to approximately 240 kHz .
Basically, Two 150-W FCCrM PFC stages are to be
designed. This chapter will not detail the dimensioning of
the power components in very deep details since their
computation is traditional. However, the main selection
criteria and equations are reminded.
2 Ǹ2 @
(V in,rms) LL 2 @ (V out * Ǹ2 @ (V in,rms) LL)
^ 5.1 + 2.1 A
Ǹ6
P cond + I M(rms) 2 @ R DS(on) +
(eq. 2)
+ 1.8 2 @ 0.4 @ 1.8 ^ 2.3 W
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(eq. 7)
AND8407/D
Bulk Capacitor Design
This computation is valid for one branch. As there are two
phases to consider, the total MOSFETs conduction losses are
actually twice (4.6 W).
Switching losses are hard to predict. They are not
computed here. As a rule of the thumb, we generally reserve
a loss budget equal to that of the conduction ones. One can
anyway note that the NCP1631 limits this source of
dissipation by clamping the switching frequency (that can
never exceed the oscillator one – 120 kHz in each branch in
our case). To further improve the efficiency, the MOSFET
opening can be accelerated using the schematic of Figure 2,
where the Q1 small npn transistor (TO92) amplifies the
MOSFET turn off gate current.
DRV
R2
R1
D2
The output capacitor is generally designed considering
three factors:
1. The maximum permissible low frequency ripple of
the output voltage. The input current and voltage
being both sinusoidal, PFC stages deliver a
squared sinusoidal power that matches the load
power demand in average only. As a consequence,
the output voltage exhibits a low frequency ripple
(e.g., 100 Hz ripple in Europe or 120 Hz in USA)
that is inherent to the PFC function.
2. The rms magnitude of the current flowing through
the bulk capacitor. Based on this computation, one
must estimate the maximal permissible ESR not to
cause an excessive heating.
3. The hold-up time. It can be specified that the
power supply must provide the full power for a
short mains interruption that is the so called
hold-up time. The hold-up time is generally in the
range of 10 or 20 ms.
M1
1N4148
R10
10 kW
Q1
The output voltage ripple is given by:
DV out(p−p) +
Figure 2. Q1 Speeds Up the MOSFET Turn Off
ǒ
Ǔ
I C(rms) +
ǒ
Ǹ
(eq. 9)
16 @ Ǹ2 @ P out 2
9 @ p @ (V in(rms)) LL @ V out @ h 2
t hold−up +
*
ǒ
P out
Ǔ
2
V out,nom
C bulk @ (V out 2 * V out(min) 2)
2 @ P out
(eq. 10)
Where Vout(min) is the minimal bulk voltage necessary to the
downstream converter to keep properly feeding the load.
Ǔ
The hold-time being not considered here, a 100-mF
capacitor was chosen to satisfy the other above conditions.
The peak-peak ripple is 25 V (3% of Vout) and the rms
current is 1.4 A.
Ǔ
I LOAD @ V f
2
(eq. 8)
Finally the following equation expresses the hold−up
time:
I
I D(tot)
I D(tot) I
I D(tot) (avg)
P out
(avg)
(avg)
LOADI LOADP out P out
I D1(avg)
^ 0.39 A
+ + I D2(avg)
++LOAD
++ +
+ + +
2
2 2 2 @2 V out2
2 2 @ V out
2 @ V out
So, the losses are about
2p @ f line @ C bulk @ V out,nom
The capacitor rms current is given by (assuming a
resistive load):
The input bridge that rectifies the line voltage and the
MOSFETs of the two branches share the same heat-sink.
Based on above computations, the total power to be
dissipated is in the range of: (6.5 + 4.6 + 4.6 ^ 16 W). A
2.9-C/W heat-sink (ref. 437479 from AAVID
THERMALLOY) is implemented. It limits the rise of the
case temperature (of the input bridge and MOSFETs applied
to it) to about 50 compared to the ambient temperature.
Interleaved PFC requires two boost diodes (one per
branch). No reverse recovery issues to worry about. Simply,
they must meet the correct voltage rating (Vout(max) +
margin) and exhibit a low forward voltage drop. Supposing
a perfect current sharing, the average diode current is the
half of the load one:
ǒ
P out
per diode, i.e., less than 500 mW per diode using MUR550
rectifiers. For each phase, the peak current seen by the diode
will be the same as the corresponding inductor peak current.
Two axial MUR550 are selected.
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AND8407/D
OSCILLATOR FREQUENCY SETTING
The NCP1631 clamps the maximum frequency of the PFC
stage without power factor degradation. This feature
prevents the switching frequency from reaching excessive
levels at light load. As detailed in the NCP1631 data sheet,
the clamp frequency in each phase is actually half the
oscillator one.
Hence:
f sw(max)1 + f sw(max)2 + f sw(max) +
f OSC
2
fOSC(nom) and each branch operates with a nominal clamp
frequency (fsw(max))nom given by:
(f sw(max)) nom +
f OSC(nom)
2
^ 26 @ 10
C pin4
−6
(eq. 12)
For instance, a 220-pF capacitor leads to the following
clamp frequency:
−6
(f sw(max)) nom ^ 26 @ 10 ^ 118 kHz
220 @ 10 −9
(eq. 11)
Where:
fsw(max)1 is the frequency clamp for the first branch of the
interleaved PFC and fsw(max)2, that of the second one
fsw(max)1 and fsw(max)2 being equal, fsw(max) stands for the
clamp frequency for any of the two phases
fOSC is the oscillator frequency
(eq. 13)
Frequency Fold-back
The NCP1631 features the frequency fold-back function
to improve the light load efficiency. Practically, the
oscillator charge and discharge currents are not constant but
proportional to power when the load drops below a
programmable level, as shown by Figure 3.
fOSC (kHz)
In the absence of frequency foldback (heavy load in
general), the oscillator swings at its nominal frequency
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
fOSC(nom) = 118 kHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Vregul (V)
Figure 3. Frequency Fold-back
Programming the Power Threshold for Frequency
Fold-back
Pin6 of the NCP1631 pins out the signal VREGUL that is
proportional to the power that is delivered. The resistor
(RFF) placed between pin 6 and ground, adjusts the pin6
current (IFF) as follows:
I FF +
V REGUL
R FF
If
ǒ
V REGUL
R FF
v 105 mA
VREGUL varies between 0 and 1.66 V. Since the power
that can be delivered is proportional to VREGUL, the power
threshold for frequency fold-back is:
(P in) FF +
Ǔ
^
As a matter of fact, the clamp frequency is also an
increasing function of VREGUL until it reaches a maximum
value for (IOSC = 105 mA):
f OSC +
V REGUL
R FF @ 105 m
1.66 V
R FF
15 810
@ (P in) HL ^
(eq. 14)
@ (P in) HL
Where:
(Pin)FF is the input power below which the frequency
reduces
(Pin)HL is the power highest level that can virtually be
delivered by the PFC stage. This value results from the
timing resistor selection (see the “maximum power
adjustment” section) and is generally set 25% or 30%
higher than the application maximum power to offer some
margin.
I FF + 105 mA otherwise
f OSC + f OSC(nom)
R FF @ 105 mA
If ǒ V REGUL w R FF @ 105 mA Ǔ
@ f OSC(nom) If ǒ V REGUL v R FF @ 105 mA Ǔ
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AND8407/D
Forcing a Minimum Frequency
The NCP1631 reduces the frequency down to virtually
zero. As detailed in the data sheet and shown by the
simplified oscillator representation of Figure 4, the circuit
lowers the frequency by diminishing the IFF current. When
this current is near zero, a 35-mA current source is still
available for charging the oscillator capacitor but the
discharge current is near zero leading to an extremely long
discharge time and a very low frequency.
It is wise to prevent the frequency from dropping below
16 kHz to avoid audible noise issues. A simple means
consists of placing a resistor (RFmin) between the “OSC” pin
and ground to force a minimum oscillator discharge current
(see Figure 4).
In our application, a 4.7-kW resistor is implemented on pin
6 (RFF = 4.7 kW). Hence, the frequency folds back when the
input power drops below the following (Pin)FF threshold:
(P in) FF + 4.7 @ 10 @ (P in) HL ^ 30% @ (P in) HL
15 810
3
(eq. 15)
In our application, the maximum input power is 325 W. It
is recommended to design the PFC stage so that it can
produce at least 25% more than the maximum power it
targets. In practice, ((Pin)HL ^ 494 W) has been selected.
As a matter of fact, the frequency folds back when the input
power goes below (30%  (Pin)HL) that is about 147 W.
IFF
35 mA
CLK1
CLK2
OSC
RFmin
(Pin 4)
COSC
IFF
Oscillator
Control
Block
DRV1
DRV2
Figure 4. Adjustment of the Minimum Frequency
Remark: Ground pin6 to inhibit the frequency foldback. If
pin6 is grounded (accidently or not), the circuit operates
with the nominal clamp frequency over the whole load
range.
Assuming that the internal IFF current is zero, the
oscillator period can be computed considering the 35-mA
charge current, the permanent leakage current generated by
RFmin and the 1 V swing across COSC (swing when the
oscillator is clamping the switching frequency).
Doing this calculation, we can deduce the minimum
clamp frequency (for each branch) forced by RFmin:
ǒfsw(max)Ǔ
min
+
+
f OSC(min)
2
+
(eq. 16)
ǒ
1
2 @ R Fmin @ C OSC @ 0.22 ) In
ǒ
R
*114000
Fmin
R Fmin*143000
ǓǓ
In our application, (RFmin = 270 kW) forces a minimum
frequency of about 20 kHz.
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AND8407/D
BROWN-OUT CIRCUITRY
BO_NOK
Circuitry for
Brown-out Detection
integrate the ac line ripple so that a portion of the (VIN)
average value is applied to the brown-out pin.
Reset
R
Q
Reset
Reset
Tdelay
100-ms
Delay
S
Rbo2
EMI
Filter
AC Line
Rcs
Cin
Vin
Cbo
Rt
Rbo1
Rt
BO
Vbo
Vbo
IBO
Vdd
7 mA
1V
IBO
Current
Mirror
OPAMP
LBO
100-ms
Delay
Vbo (BO Pin Voltage)
IBO Charges the Timing
Capacitor for Both Phases
Feed-forward
Circuitry
The brown-out terminal (pin7) typically receives a
portion of the PFC input voltage (VIN). As during the PFC
operation, VIN is a rectified sinusoid, a capacitor must
Figure 5. Brown-out Block
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7
AND8407/D
Figure 6). As a consequence, the input voltage
is approximately flat and nearly equates the ac
line amplitude:
As sketched by Figure 5, the brown-out block has two
functions:
1. Feed-forward: The brown-out pin voltage is
buffered to generate an internal current IBO
proportional to the input voltage average value in
conjunction with the pin3 resistor (Rt). This
current is squared to form the current that charges
the internal timing capacitors that control the
on-time in the two branches. As a matter of fact,
the on-time is inversely proportional to the square
of the line magnitude. This feed-forward feature
makes the transfer function and the power delivery
independent of the ac line level.
2. Detection of the line magnitude being too low.
A 7-mA current source lowers the BO pin voltage
when a brown-out condition is detected, for
hysteresis purpose as required by this function. In
traditional applications, the sensed voltage
dramatically varies depending on the PFC stage
state:
 Before operation, the PFC stage is off and the
input bridge acts as a peak detector (refer to
V IN + Ǹ2 @ V in,rms
where Vin,rms is the rms voltage of the line.
Hence, the voltage applied to pin7 is:
V pin7 + Ǹ2 @ V in,rms @
R bo2
R bo1 ) R bo2
 After the PFC stage has started operation, the
input voltage becomes a rectified sinusoid and
the voltage applied to pin7 is:
2 @ Ǹ2 @ V in,rms
R bo2
p
R bo1 ) R bo2
V pin7 +
i.e., about 64% of the previous value.
Therefore, in traditional applications, the same line
magnitude leads to a BO pin voltage that is 36% lower when
the PFC is working. That is why a large hysteresis is
required.
Start of PFC Operation
400
Ǹ2 @ V
in,rms @ sin(wt)
V in(t)
200
Ǹ2 @ V
in,rms
0
Figure 6. Typical Input Voltage of a PFC Stage
Computing Cbo, Rbo1 and Rbo2 of Figure 5
Where (Vin,avg)boH is the average input voltage above which
the circuit turns on and Vbo(th) is the BO internal threshold
(1 V typically).
Hence:
1. Define the line levels at which the circuit should detect
a brown-out and recover operation:
Our application being specified to operate from 90 Vrms,
it can make sense to select the following thresholds:
 The system starts operating when the line voltage is
above (Vin,rms)boH = 81 V (90% of 90 V)
 The system detects a fault when the line voltage goes
below (Vin,rms)boL = 72 V (80% of 90 V)
ǒVin,avgǓ
R bo1 ) R bo2
@ ǒV in,avgǓ
boH
*
ǒ
R bo1 @ R bo2
R bo1 ) R bo2
Ǔ
@ I HYST
+
ǒ
R bo2
(eq. 18)
Ǔ
@ V bo(th) ) ǒR bo1 @ I HYSTǓ
As long as the line is above the BO threshold, the internal
current source (IHYST = 7 mA typically) is off and the BO pin
voltage is:
ǒ
2. Define the average input voltage when Vpin7 (BO pin
voltage) crosses the BO thresholds (Vpin7 rising and
falling):
When the line voltage is below the BO threshold, the
internal current source (IHYST = 7 mA, typically) is activated
to offer some hysteresis and the circuit recovers operation
when:
R bo2
boH
R bo1 ) R bo2
V pin7 + k BO @ V in,avg @ 1 *
Ǔ
f BO
3 @ f line
Where:
(Vin,avg) is the average input voltage
fline is the line frequency
fBO is the sensing network pole frequency
(eq. 17)
ǒ
+ V bo(th)
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f BO +
Ǔ
R bo1 ) R bo2
2p @ R bo1 @ R bo2 @ C bo
(eq. 19)
AND8407/D
kBO is scale down factor of the BO sensing network
ǒ
k BO +
The term
ǒ
3. Calculation:
From Equation 20, we can deduce the following
expression of the brown-out scale down factor:
Ǔ
R bo2
R bo1 ) R bo2
1*
K BO +
Ǔ
f BO
3 @ f line
(V in,avg) boH +
A brown-out fault is detected when the BO pin voltage
goes below Vbo(th) (BO internal threshold that is 1 V
typically). Hence, the BO protection triggers when the
average voltage goes below the (Vin,avg)boL level expressed
by the following equation:
ǒVin,avgǓ
boL
+
ǒ
Ǔ
f
k BO @ 1 * BO
3@fline
f BO +
ǒ
Ǔ
f
(V in,avg) boL @ 1 * BO
3@f line
(eq. 21)
ǒ
ǒ
(V in,avg) boL @ 1 *
f BO
ǓǓ
3 @ f line
(eq. 22)
) (R bo1 @ I HYST)
We can then deduce the following expression of Rbo1:
(V in,avg) boH *
ǒ
(eq. 20)
ǒ
(V in,avg) boL @
R bo1 +
1*
ǓǓ
f BO
3@fline
I HYST
(eq. 23)
Re-using the above Rbo1 expression, one can deduce Rbo2
from Equation 21:
R bo2 +
Where (Vin,avg)boL is the average input voltage below which
the circuit turns off, fBO is the sensing network pole
frequency
ǒ
V BO(th)
Substitution of Equation 21 into Equation 18 leads to:
of Equation 19 enables to take into account the BO pin
voltage ripple (first harmonic approximation).
V BO(th)
R bo2
+
R bo1 ) R bo2
Ǔ
R bo1 ) R bo2
2p @ R bo1 @ R bo2 @ C bo
R bo1
ǒ
(Vin,avg)boL
V BO(th)
ǓǓ
ǒ
f
@ 1 * BO
3@fline
(eq. 24)
*1
If as a rule of the thumb, we will assume that
ǒf
and fline is the line frequency.
BO
+
Ǔ
f line
10
that is 6 Hz in the case of a 60-Hz line, we obtain:
(V in,avg) boH
R bo1 +
R bo2 +
ȡ
*ȧ(V
Ȣ
ȡ f10
@ȧ1 *
3@f
Ȣ
line
in,avg) boL
ȣȣ
ȧȧ
ȤȤ
line
^
I HYST
ǒ
R bo1
(V in,avg)boL
VBO(th)
ǒ
ǓǓ
f
@ 1 * BO
3@f line
^
*1
(V in,avg) boH * ǒ0.967 @ (V in,avg) boLǓ
R bo1
ǒ
0.967 @
As an example, we will consider the traditional PFC stage
where the average value of the input voltage is 36% lower
when the circuit operates (as illustrated by Figure 6).
So if we select:
 The system starts operating when the line voltage is
above
(eq. 25)
I HYST
Ǔ
(Vin,avg) boL
VBO(th)
(eq. 26)
*1
The corresponding average input voltage thresholds are:
(V in,avg) boH + Ǹ2 @ (V in,rms) boH + Ǹ2 @ 81
(eq. 27)
And:
2 Ǹ2
2 Ǹ2
(V in,avg) boL + p @ (V in,rms) boL + p @ 72 (eq. 28)
We have then to solve:
(V in,rms) boH + 81 V
ǒǸ2 @ 81Ǔ *
 The system detects a fault when the line voltage goes
below
R bo1 ^
(V in,rms) boL + 72 V
R bo2 ^
9
2Ǹ2
0.967 @ p @ 72
Ǔ
7 @ 10 −6
7410 @ 10 3
^ 120 kW
2Ǹ2
0.967@ p @72
*1
1
ȡ
ȧ
Ȣ
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ǒ
ȣ
ȧ
Ȥ
(eq. 29)
^ 7410 kW
(eq. 30)
AND8407/D
C bo +
^
R bo1 ) R bo2
f
2p @ R bo1 @ R bo2 @ line
10
In practice, four 1.8-MW resistors are placed in series for
Rbo1 (for a global 7.2-MW resistor) and we use a 120-kW
resistor for Rbo2 and 220-nF capacitor for Cbo.
One should note that the NCP1631 brown-out circuitry
incorporates a 50-ms blanking delay to help meet hold-up
times requirement (see data sheet).
^
7410 k ) 120 k
2p @ 7410 k @ 120 k @ 60
10
(eq. 31)
^
^ 225 nF
MAXIMUM POWER ADJUSTMENT
The instantaneous line current is the averaged value (over
the switching frequency) of the total current absorbed by the
two branches of the PFC stage. It is given by the following
formula:
I in(t) +
Where:
Since VREGUL is clamped to 1.66 V, the maximum power
((Pin)HL) that can be virtually delivered by the PFC stage is:
(eq. 35)
(P in) HL +
(R t) 2 @ V REGUL
V in(t)
(eq. 32)
@
L
26.9 @ 10 12 @ k BO 2 @ V in,rms 2
ǒ
(R t) 2 @ V REGUL
26.9 @ 10 12 @ k BO 2 @ V in,rms 2
Hence:
R t ^ 4025 @ 10 3 @ k BO @ ǸL @ (P in) HL
Ǔ
k BO +
ǒ
(eq. 37)
Ǔ
(R t) 2 @ V REGUL
26.9 @ 10 12 @ L @ k BO 2
Ǔ
R t ^ 4025 @ 10 @ 1 @ Ǹ150 @ 10 −6 @ 400 ^ 16 @ 2 kW
61
A 18-kW resistor is selected that leads to
(P in) HL +
(eq. 33)
And averaging the instantaneous power over the line
period gives the following expression of the mean input
power:
P in,avg +
R bo2
+ 1
61
R bo1 ) R bo2
3
R bo2
R bo1 ) R bo2
(R t) 2 @ V REGUL @ V in 2(t)
26.9 @ 10 12 @ L @ k BO 2 @ V in,rms 2
k BO +
Hence:
Multiplying Iin by Vin, one can deduce the instantaneous
power:
P in(t) +
(eq. 36)
For the sake of a welcome margin, ((Pin)HL) should be
selected about 25% higher than the expected maximal input
power that is: (125%  325 W ^ 400 W) in the application
of interest.
In our case,
 L = 150 mH
 Since Rbo1 = 7,200 kW and Rbo2 = 120 kW,
is the expression of the on-time in each branch
 (VREGUL) is an internal signal linearly dependent of
the output of the regulation block (VCONTROL).
(VREGUL) varies between 0 and 1.66 V.
 Iin(t) and Vin(t) are the instantaneous line current and
voltage respectively.
 Vin,rms is the line rms voltage
 L is the coil inductance
 kBO is scale down factor of the BO sensing network
ǒ
(R t) 2 @ 1.66
(R t) 2
^
12
2
26.9 @ 10 @ L @ k BO
16.2 @ 10 12 @ L @ k BO 2
(eq. 34)
As a result of the feed-forward, the delivered power does
not depend on the line magnitude but is the only function of
the coil inductance, of the input voltage sensing network
(used and dimensioned for the brown-out detection) and of
Rt capacitor, that is, the timing resistor that is applied to pin3.
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10
(18 @ 10 3) 2 @ 61 2
^ 496 W
16.2 @ 10 12 @ 150 @ 10 −6
AND8407/D
FEED-BACK NETWORK
The NCP1631 embeds a trans-conductance error amplifier
that typically features a 200-mS trans-conductance gain and
a 20-mA maximum capability (see Figure 7). The output
voltage of the PFC stage is externally scaled down by a
resistors divider and monitored by the feed-back input
(pin2). The bias current is minimized (less than 500 nA) to
allow the use of a high impedance feed-back network. The
output of the error amplifier is pinned out for external loop
compensation (pin5).
V out,nom +
R fb1 ) R fb2
Compensation
The NCP1631 uses the brown-out input voltage to provide
some feed-forward. This allows the small-signal transfer
function of PFC stage to be independent of the ac line
amplitude. More specifically, the bulk capacitor ESR being
neglected:
^
V out
^
V REGUL
R fb2
+
V out,nom
*1
V REF
ǒ
V out,nom
*1
V REF
(eq. 40)
Ǔ
(eq. 41)
We target a 390-V regulation level, hence:
ǒ
Ǔ
R fb1 + 27 kW @ 390 * 1 + 4185 kW
2.5
ǒ
@ L @ k BO 2 @ V out,nom
1
s@
R out@C bulk
2
Ǔ
@
(eq. 44)
However, PFC stages must exhibit a very low regulation
bandwidth, in the range of or lower than 20 Hz to yield high
power factor ratios. Hence, sharp variations of the load
generally result in excessive over and under-shoots. The
NCP1631 limits over-shoots by the Over-Voltage Protection
(see OVP section). To contain under-shoots, an internal
comparator monitors the feed-back (Vpin2) and when Vpin2
is lower than 95.5% of its nominal value, it connects a
220-mA current source to speed-up the charge of the
compensation capacitors. Finally, it is like if the comparator
multiplied the error amplifier gain by about 10 (Note 1).
The implementation of this dynamic response enhancer
together with the accurate and programmable over-voltage
protection, guarantees a reduced spread of the output voltage
in all conditions included sharp line/load transients.
Hence, in most applications, it can be sufficient to place
a low frequency pole that drastically limits the bandwidth.
However, it is recommended to implement a type2
compensation as represented by the following figure:
In practice, (Rfb2 = 27 kW) was selected for our
application. Following Equation 39, Rfb1 is given by:
R fb1 + R fb2 @
53.8 @
10 12
Where:
Cbulk is the bulk capacitor
Rout is the load equivalent resistance
Rt is the pin3 external capacitor
L is the PFC coil inductance
KBO is the brown-out scale-down factor
Vout,nom is the regulation level of the PFC output0
(eq. 39)
V REF
+ 25 kW
100 mA
(R t) 2 @ R out
1)
(eq. 38)
Another constraint on the feed-back resistors is the power
it dissipates. Rfb1 and Rfb2 being biased by the PFC output
high voltage (in the range of 390 V typically), they can easily
consume several hundreds of mW if their resistance is low.
Targeting a bias current in the range of 100 mA generally
gives a good trade-off between losses and noise immunity.
This criterion leads to:
R fb2 +
+
@
Or:
R fb1
(eq. 43)
1800 k ) 1800 k ) 560 k ) 27 k
@ 2.5 V
27 k
^ 388 V
A resistor divider consisting of Rfb1 and Rfb2 of Figure 7
must provide pin2 with a voltage proportional to the PFC
output voltage so that Vpin2 equates the internal reference
voltage (VREF = 2.5 V) when the PFC output voltage is
nominal. In other words:
@ V out,nom + V REF
@ V REF
R fb2
+
Computation of the Feed-back/Regulation External
Components
R fb2
R fb1 ) R fb2
(eq. 42)
Like for the input voltage sensing network, several
resistors should be placed in series instead of a single Rfb1
resistor. In our application, we choose a (1,800 kW +
1,800 kW + 560 kW) network. This selection together with
(Rfb2 = 27 kW) leads to:
1. The circuit disables this capability (dynamic response enhancer) until the PFC stage output voltage has reached its target level (that is when
the “pfcOK” signal of the block diagram, is high). This is because, at the beginning of operation, the pin5 compensation network must charge
slowly and gradually for a soft start-up.
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11
AND8407/D
Vout
Rfb1
FB
(Pin2)
Rfb2
2R
VREGUL
Vcontrol
Cz
Rz
GEA = 200 mS
+
OTA
+
VREF
2.5 V
R
(Pin5)
Cp
Figure 7. Regulation Trans-conductance Error Amplifier, Feed-back and Compensation Network
The output to control transfer function brought by the
type-2 compensator is:
^
V control
^
V out
+
1 ) sR zC z
ǒ
Ǔ
 fp0 is the frequency of the origin pole:
f p0 +
(eq. 45)
C z@Cp
sR o(C z ) C p) 1 ) sR z
C z)Cp

Where:
R0 +
V ref @ G EA
f p1 + 4 2 @ f z
Actually, The NCP1631 PWM section does not directly
use Vcontrol but VREGUL. Taking into the (5/9) resistors
divider that links Vcontrol and VREGUL, it comes:
^
^
V out
1 ) sR zC z
+
s
ǒ
Ǔ
Cz@Cp
9@Ro
@ (C z ) C p) 1 ) sR z
5
Cz)Cp
V out,nom
V ref @ G EA
Place the Zero and the High Frequency Pole:
We can obtain a 60 phase boost and hence, a 60 phase
margin by placing the compensation zero at (fc/4) and the
high frequency pole at (4  fc), where fc is the selected
crossover frequency.
From this, it comes that:
V out,nom
GEA being the gain of the trans-conductance error amplifier
(OTA), Vout,nom, the output nominal voltage (Vout regulation
level) and VREF, the OTA 2.5-V voltage reference.
V REGUL
R0 +
5
18p @ R 0 @ ǒC p ) C zǓ
Substitution of the fp1 and fz expressions into Equation 48
leads to:
(eq. 46)
1)
^
^
V out
+
ǒ
s
2p@fz
Ǔ
(eq. 47)
s
1) s
2p@fp0
2p@fp1
Go +
 fp1 is the frequency of the compensator high frequency
pole:
1
2p @ R z @
ǒ
Cp@Cz
Cp)Cz
C z + 15 @ C p
(eq. 50)
53.8 @
(R t) 2 @ R out
@ L @ k BO 2 @ V out,nom
10 12
(eq. 51)
If fc is the desired crossover frequency, the pole at the
origin must be placed at the load that would set the boost
converter pole at the selected compensation zero.
Hence:
1
2p @ R z @ C z
f p1 +
(eq. 49)
Place the Pole at the Origin to Have the Proper
Bandwidth:
Equation 44 instructs that the static gain of the PFC boost
is:
Where:
 fz is the frequency of the compensator zero:
fz +
Cp @ Cz
C
+ z
16
Cp ) Cz
Hence:
Hence, we have:
V REGUL
(eq. 48)
ǒ Ǔ
Ǔ
−20 @ log
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12
fc
f p0
ǒ |ǒ
+ −20 @ log G
(eq. 52)
R out +
4
p @ C bulk @ f c
ǓǓ
AND8407/D
Or:
f p0 +
G0
|R
fc
(eq. 53)
4
out +
Practically, we will use 68-nF capacitor that is a close
standard value.
C z + 15 @ C p + 1020 nF
p@Cbulk@f c
In practice, a 1-mF standard capacitor is selected.
Finally,
This leads to:
f p0 +
fc
4@Rt 2
(eq. 54)
Rz +
p @ 53.8 @ 10 12 @ L @ C bulk @ k BO 2 @ f c @ V out,nom
p @ 53.8 @ 10 12 @ L @ C bulk @ k BO 2 @ f c 2 @ V out,nom
4 @ Rt 2
Where kBO is scale down factor of the BO sensing network
k BO +
Ǔ
R bo2
R bo1 ) R bo2
ǒff Ǔ * arctanǒff
Replacing fp0 by its expression of Equation 55, it comes:
5
+
18p @ R 0 @ (C p ) C z)
+
18p @
ǒ
5
Ǔ
V out,nom
@ (16 @ C p)
Vref@GEA
F m + arc tan
+
fz +
Replacing GEA and Vref by their typical value (200 mS
and 2.5 V, respectively, we can write the following equation
that gives Cp:
2
p @ Cz @ fc
(eq. 58)
(eq. 59)
(eq. 60)
(eq. 61)
(eq. 62)
In our application,
Cp +
1.06 @ 10 −6 @ 497
^ 86 nF
100 @ 10 −6 @ 20 2 @ 390 2
ǒ
Cp@Cz
Cp)Cz
Ǔ
(f z ^ 5 Hz), (f p1 ^ 37 Hz), (F m ^ 76 o * 28 o + 48 o)
Finally, from the above computations, we can deduce the
following equations to design the compensation network.
Rz +
(eq. 66)
Finally, a 150-nF capacitor is selected for Cp, leading to:
The compensation zero being placed at (fc/4), it comes:
C z + 15 @ C p
1
2p @ R z @
Computing Rz
1.06 @ 10 −6 @ (P in) HL
C bulk @ f c 2 @ (V out,nom) 2
Ǔ
1
2p @ R z @ C z
f p1 +
Replacing Rt by this expression of Equation 36, the
precedent equation simplifies:
Cp ^
p1
pole:
(eq. 57)
f
1
+ c
4
2p @ R z @ C z
c
z
 fp1 is the frequency of the compensator high frequency
V ref @ G EA @ R t 2
Cp ^
12
7646.2 @ 10 @ L @ C bulk @ k BO 2 @ f c 2 @ (V out,nom) 2
fz +
c
Where:
 fz is the frequency of the compensator zero:
p @ 53.8 @ 10 12 @ L @ C bulk @ k BO 2 @ f c 2 @ V out,nom
(eq. 56)
4 @ Rt 2
1.06 @ 10 −6 @ (P in) HL
Cp ^
C bulk @ f c 2 @ (V out,nom) 2
(eq. 65)
The compensation is computed to have a phase margin in
the range of 60. The high frequency pole can be set at a
lower frequency. Practically, Cp can be increased up to 4
times the proposed value (without changing Rz and Cz) to
reduce the ripple on the Vcontrol pin and further improve the
THD. The crossover frequency is unchanged. This is just at
the cost of a diminution of the phase margin that can drop as
low as 30. More specifically:
(eq. 55)
ǒ
2
^ 31.8 kW
p @ 1 @ 10 −6 @ 20
A 33-kW resistor is implemented.
This expression simplifies as follows:
f p0 +
(eq. 64)
(eq. 63)
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13
EMI
Filter
Figure 8. Current Sense Block
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14
RCS
ROCP
CS
CIN
9
IIN
Negative
Clamp
ICS
IIN
Curre nt M irror
IZCD = 20 mA
ICS
ICS
(ICS is Proportional
to the Coil Current)
IOCP = 200 mA
ICS
The CS block performs the over-current protection and detects the in-rush currents.
ICS
VIN
Qzcd1
Qzcd2
(from ZCD block)
In − r u s h
OCP
DRV1
Vaux1
M1
L1
Vaux2
M2
D1
DRV2
L2
D2
+
CBULK
VOUT
AND8407/D
CURRENT SENSE NETWORK
LOAD
AC Line
AND8407/D
The circuit compares ICS to an internal 210-mA current
reference for a cycle by cycle current limitation. Hence, the
maximum coil current is:
The NCP1631 is designed to monitor a negative voltage
proportional to the coil current. Practically, a current sense
resistor (RCS of Figure 8) is inserted in the return path to
generate a negative voltage proportional to the total current
absorbed by the two branches. The circuit incorporates an
operational amplifier that sources the current necessary to
maintain the CS pin voltage null (refer to Figure 8). By
inserting a resistor ROCP between the CS pin and RCS, we
adjust the pin9 current as follows:
* (R CS @ I in) ) (R OCP @ I pin9) + V pin9 ^ 0
I in,max +
I in,max
R OCP
+
R CS
210 mA
(eq. 67)
R CS
I
R OCP in
(eq. 68)
(P in,avg) max
(V in,rms) LL
I in,max + 2 Ǹ2 @
ȡ
ȧ
Ȣ
@ 1*
(P in,avg) max
(V in,rms) LL
V out,nom
ǒ
4 @ V out,nom * ǒǸ2 @ (V in,rms) LL
@
ǒ
1*
V out,nom
Ǹ
4 @ 2 @ (V in,rms) LL
I in,max
ǒ
in,rms) LL
in,rms LL
V out,nom
2 Ǹ2
(V in,rms) LL + 90 v
(eq. 71)
V out,nom
2 Ǹ2
if (V in,rms) LL w
ȡ
V
ȧ
(V
)
* ǒǸ2 @ (V
)
Ȣ 4 @ ǒV
ȡ
ȣ
390
+ 2 Ǹ2 @ 325 @ȧ1 *
ȧ^ 6.4 A
90
Ȣ 4 @ ǒ390 * ǒǸ2 @ 90ǓǓȤ
(P in,avg) max
v
(eq. 72)
Ǔ
V out,nom
+ 390 ^ 138
2 Ǹ2
2 Ǹ2
Hence:
out,nom
@ 1*
out,nom
in,rms LL
ȣ
ȧ
ǓǓȤ
(eq. 73)
(eq. 74)
Finally:
 Selecting ROCP and RCS:
If we neglect the input current ripple, the RCS losses
are given by the following simplified equation:
P Rcs + R CS @
Ǔ
ȣ
ȧif (V
ǓǓȤ
In our case,
Where:
(Vin,rms)LL is the lowest level of the line rms voltage.
(Pin,avg)max is the maximum level of the input power.
Vout,nom is the nominal level of the output voltage
(or the output regulation voltage)
I in,max + 2 Ǹ2 @
(eq. 70)
As we have two external components to set the current
limit (ROCP and RCS), the current sense resistor can be
optimized to have the best trade-off between losses and
noise immunity.
 Maximum current drawn by the two branches:
As shown in [1], the following equations give the total
current that is absorbed by the interleaved PFC.
Where Iin is the total current drawn by the two phases of the
interleaved PFC stage.
I in,max + 2 Ǹ2 @
(eq. 69)
Finally, the ratio (ROCP/RCS) sets the over-current limit
in accordance with the following equation:
Which leads to:
I CS + I pin9 +
R OCP
@ 210 mA
R CS
ǒ Ǔ
P in,avg
R CS +T @
2
R OCP + R CS @
One can choose RCS as a function of its relative impact on
the PFC stage efficiency at low line and full power. If  is
the relative percentage of the power that can be consumed
by RCS, this criterion leads to:
T @ (P in,avg) max + R CS @
ǒ
(P in,avg) max
(V in,rms) min
Ǔ
(P in,avg) max
(eq. 77)
And:
(eq. 75)
V in,rms
(V in,rms) min 2
I in,max
210 mA
(eq. 78)
Generally ( = 0.2%) gives a good trade-off between
losses and noise immunity (0.2% of the power is lost in the
RCS at low line).
2
(eq. 76)
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15
AND8407/D
This criterion leads to the following RCS value:
R cs + 0.2% @
90 2
325
This selection results in the following ROCP resistor:
(eq. 79)
^ 50 mW
R OCP + 50 m @
6.4 A
^ 1.5 kW
210 mA
(eq. 80)
ZERO CURRENT DETECTION (ZCD)
A resistor, RZCD1 is to be added between the phase 1 ZCD
winding and pin 16 for branch 1 and another one RZCD2
between the phase 2 ZCD winding and pin1 for branch 2.
RZCD1 and RZCD2 limit the current into or out of pins 1 and
16. This current is preferably set in the range of 2 mA (sink
and source). In general, the pins are the most stressed by the
sink current obtained at high line. Hence, RZCD1 and RZCD2
must be selected high enough so that:
For each phase, a winding taken off of the boost inductor
gives the zero current detection (ZCD) information. When
the switch is on, the ZCD pin voltage is equal to:
V zcd + *
V in
N
(eq. 81)
Where Vin is the instantaneous ac line voltage and N, the
turns ratio (ratio number of turns of the primary winding
over the number of turns of the ZCD auxiliary winding)
When the switch is off, the ZCD pin voltage is equal to:
V zcd +
V out * V in
N
R ZCD1 + R ZCD2 w
(eq. 82)
I ZCD @ N
+
(eq. 83)
Ǹ2 @ 265
+
^ 19 kW
2 m @ 10
The NCP1631 incorporates two ZCD comparators:
1. A first one senses pin1 that is to receive the ZCD
voltage from branch 2
2. A second one monitors pin16 that receives the
ZCD signal for branch1.
A 22-kW was selected.
However, the value of this resistor and the small parasitic
capacitance of the ZCD pin also determine when the ZCD
winding information is detected and the next drive pulse
begins. Ideally, the ZCD resistor will restart the drive at its
valley. This will minimize switching losses by turning the
MOSFET back on when its drain voltage is at a minimum.
The value of RZCD1 and RZCD2 to accomplish this is best
found experimentally. Too high of a value could create a
significant delay in detecting the ZCD event. In this case, the
controller would operate in discontinuous conduction mode
(DCM) and the power factor would suffer. Conversely, if the
ZCD resistor is too low, then the next driver pulse would
start when the voltage is still high and switching efficiency
would suffer.
The ZCD comparators have a 0.5-V threshold (rising,
with a 250-mV hysteresis). Therefore, N must be sized such
that at least 0.5 V is obtained on the ZCD pin during the
demagnetization in all operating conditions. The voltage
obtained on the ZCD pin is minimal in high line and at the
top of the sinusoid, leading to:
Nv
Ǹ2 @ (V
in,rms) HL
V out * ǒǸ2 @ (V in,rms) HLǓ
0.5
With ((Vin,rms)HL = 265 V) and (Vout = 390 V), N must
be lower than 30. A turns ratio of 10 was selected for this
design.
OVER-VOLTAGE PROTECTION
The NCP1631 dedicates one specific pin for the
under-voltage and over-voltage protections. The NCP1631
configuration allows the implementation of two separate
feed-back networks (see Figure 10):
Vout (Bulk Voltage)
Rout1
Rout3
Rout2
FB
1
2
3
4
5
6
7
8
OVP
 One for Regulation Applied to Pin 4 (Feed-back Input)
 Another One for the OVP Function
Vout (Bulk Voltage)
Vout (Bulk Voltage)
16
15
14
13
12
11
10
9
Figure 9. Configuration with
One Feed-back Network for
Both OVP and Regulation
Rfb1
Rovp1
1
FB 2
Rfb2
Rovp2
OVP
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 10. Configuration with Two
Separate Feed-back Networks
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16
Rovp
Rfb1
1
FB 2
Rfb1
Rfb2
3
4
5
6
7
Rfb2
OVP
8
16
15
14
13
12
11
10
9
Figure 11. Another Configuration
with Two Separate Feed-back
Networks
AND8407/D
The double feed-back configuration offers some
redundancy and hence, an up-graded safety level as it
protects the PFC stage even if there is a failure of one of the
two feed-back arrangements.
However, the regulation and the OVP function have the
same reference voltage (VREF = 2.5 V) so that if wished,
one single feed-back arrangement is possible as portrayed
by Figure 9. The regulation and OVP blocks having the
same reference voltage, the resistance ratio Rout2 over Rout3
adjusts the OVP threshold. More specifically,
 The bulk regulation voltage is:
R
) R out2 ) R out3
V out,nom + out1
@ V REF
R out2 ) R out3
R ovp1 + R ovp2 @
ǒ
V out,ovp
+1)
R out3
R out2
V out,ovp +
(eq. 84)
(eq. 88)
Ǔ
(eq. 89)
R ovp1 ) R ovp2
R ovp2
@ V REF
(eq. 90)
1800 k ) 1800 k ) 820 k ) 27 k
@ 2.5 V
27 k
Remark:
As illustrated by Figure 11, another effective means to
dimension the OVP sensing network is, to select:
 Rovp2 = Rfb2
 Rovp1 = Rfb1 + Rovp, where Rovp is a part of the upper
resistor of the OVP sensing network.
(eq. 86)
Note that:
V out,nom +
V out,ovp +
+
R fb1 ) R fb2
R fb2
@ V REF
R ovp1 ) R ovp2
R ovp2
@ V REF +
R fb1 ) R ovp ) R fb2
R fb2
@ V REF
Combining two precedent equations, it comes:
Again, a bias current in the range of 100 mA generally
gives a good trade-off.
V out,ovp + V out,nom )
R ovp
@ V REF
R fb2
In other words, the OVP protection trips when the
overshoot exceeds:
Hence:
V ref
+ 25 kW
100 mA
Ǔ
^ 412 V
(eq. 85)
For instance, (Rout3 = 5%  Rout2) leads to (Vout,ovp =
105%  Vout,nom).
As soon and as long as the circuit detects that the output
voltage exceeds the OVP level, the power switch is turned
off to stop the power delivery.
In our application, the option that consists of two separate
Vout sensing networks is chosen (configuration of
Figure 10). Like for the regulation network, the impedance
of the monitoring resistors must be:
1. high enough to limit the losses that if excessive,
may not allow to comply with the stand-by
requirements to be met by most power supplies
2. low enough for a good noise immunity
R ovp2 +
*1
For safety reason, several resistors should be placed in
series instead of a single Rovp1 one. In our application, we
choose a (1,800 kW + 1,800 kW + 820 kW) network.
The exact OVP level is then:
 The ratio OVP level over regulation level is:
V out,nom
V REF
R ovp1 + 27 kW @ 410 * 1 + 4401 kW
2.5
+
R out1 ) R out2 ) R out3
@ V REF
R out2
V out,ovp
In our application, our 410-V target leads to:
 The (bulk) OVP level is:
V out,ovp +
ǒ
ǒ
(eq. 87)
In practice, (Rovp2 = 27 kW) was selected and as a
consequence:
Ǔ
R ovp
@ V REF
R fb2
CONCLUSIONS
application note shows that the efficiency can remain as high
as almost 95% at 90 Vrms from 20% to 100% of the load,
despite the relatively high switching frequency range that
was selected (120-kHz nominal clamp frequency).
The following table summarizes the key equations useful
to design a NCP1631 driven interleaved PFC. Another table
reports the results of these computations for our 300-W
application of interest.
This application note proposes a systematic approach for
the eased design of an efficient 2-phase, interleaved PFC.
More specifically, this paper provides the key equations and
design criteria necessary to dimension the PFC stage. The
practical implementation of a 300-W, wide mains
application illustrates the process.
For detailed information on the performance of a 300-W
interleaved PFC designed according to the proposed
method, you can refer to NCP1631EVB/D [3]. This
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17
AND8407/D
Table 1. GENERAL EQUATIONS − SUMMARY
Lw
(V in,rms) LL 2 @ ǒV out,nom * Ǹ2 @ (V in,rms) LLǓ
(P in,avg) max @ V out,nom @ f OSC(nom)
Coil Selection
(I L,pk) max + Ǹ2 @
(P in,avg) max
(V in,rms) LL
(P in,avg) max
(I L,rms) max + 1 @
Ǹ3 (V in,rms) LL
Power
Components
MOSFET
Conduction Losses
(P on) max + 1 @ R DS(on) @
3
ǒ
(P in,avg) max
(V in,rms) LL
(dV out) pk−pk +
C bulk w
Bulk Capacitor
(I C,rms) max +
Ǹǒ
BO Filtering Capacitor
Timing Resistor
ƫ
P out,max
C bulk @ w @ V out,nom
Ǔ ǒ
ǒ
ǒ
(V in,avg) boL @ 1 *
Ǔ
2
ǓǓ
fBO
3@fline
ǒ
R bo1
(V in,avg)boL
V BO(th)
ǒ
@ 1*
ǓǓ
fBO
3@fline
*1
R bo1 ) R bo2
2p @ R bo1 @ R bo2 @ f BO
R t + 4026 @ 10 3 @ k BO @ ǸL @ (P in) HL
Pin3 Resistor
f OSC(nom) ^ 52 @ 10
C OSC
Clamp Frequency
per Branch
ǒfsw(max)Ǔ
Fold−Forward
Power Threshold
Minimum Frequency
(per Branch)
3p @ V out,nom
(P in,avg) max 2
(P out) max
16 Ǹ2
@
*
9p
(V in,rms) LL @ V out,nom
V out,nom
C bo +
Oscillator Frequency
(No Frequency Foldback)
Oscillator
8 Ǹ2 @ (V in,rms) LL
I HYST
R bo2 +
BO Bottom Resistor
1*
V out,nom 2 * V out,min 2
R bo1 +
Brown-out Block
@
2 @ P out,max @ t HOLD−UP
(V in,avg) boH *
BO Upper Resistor
Ǔ ƪ
2
nom
+
(P in) FF +
ǒfsw(max)Ǔ
min
f OSC(nom)
2
2 @ R Fmin @ C OSC @
R fb2 +
Feedback
Resistors
Feedback Upper Resistor
R fb1 + R fb2 @
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18
^ 26 @ 10
C OSC
−6
R FF
@ (P in) HL
15810 W
+
Feedback Bottom Resistor
−6
ǒ
ǒ
1
ǒ
0.22 ) In
V REF
I FB
Ǔ
V out,nom
*1
V REF
ǓǓ
RFmin*114000
RFmin*143000
AND8407/D
Table 1. GENERAL EQUATIONS − SUMMARY (continued)
OVP Bottom Resistor
R ovp2 +
OVP Resistors
OVP Upper Resistor
R ovp1 + R ovp2 @
Cp Capacitor of the
Type2 Compensation
Loop
Compensation
Cp ^
ǒ
V out,ovp
V REF
Ǔ
*1
1.06 @ 10 −6 @ (P in) HL
C bulk @ f c 2 @ (V out,nom) 2
Cz Capacitor of the
Type2 Compensation
C z + 15 @ C p
Rz Resistor of the
Type2 Compensation
Rz +
I in,max + 2 Ǹ2 @
(P in,avg) max
(V in,rms) LL
ȡ
ȧ
Ȣ
2
p @ Cz @ fc
@ 1*
ǒ
V out,nom
4 @ V out,nom * ǒǸ2 @ (V in,rms) LL
if (V in,rms) LL v
Maximum Level of the
Input Current
I in,max + 2 Ǹ2 @
Current Limitation
V REF
I FB
(P in,avg) max
(V in,rms) LL
@
ǒ
1*
R CS +
Current Sense Resistor
Over Current Resistor





foldback
(fsw(max)) is the nominal clamp frequency for each
branch (in the absence of frequency foldback), that is
ǒ
Ǔ
f OSC(nom)
2

 (fsw(max))min is the minimum clamp frequency for each










branch resulting from frequency foldback
Vout,nom is the nominal output voltage of the PFC stage
(regulation level)
(Vin,rms)LL is the lowest level of the line rms voltage
(Pin,avg)max is the maximum level of the average input
power
(IL,pk)max is the maximum peak current absorbed by
one branch of the interleaved PFC (normal operation)
(IL,rms)max is the maximum rms current drawn by one
branch of the interleaved PFC (normal operation)
Pon are the MOSFET conduction losses (in one branch)
RDS(on) is the MOSFET on-time resistor (for one branch)
(dVout)pk−pk is the output peak to peak ripple
w is the line angular frequency (w = 2p  fline)
Ǔ
V out,nom
2 Ǹ2
P Rcs @ (V in,rms) LL 2
R OCP +
 fOSC(nom) is the oscillator frequency without frequency
V out,nom
2 Ǹ2
V out,nom
Ǹ
4 @ 2 @ (V in,rms) LL
if (V in,rms) LL w
ȣ
ȧ
ǓǓȤ
(P in,avg) max 2
R CS @ I in,max
210 @ 10 −6
fline is the line frequency
Cbulk is the bulk capacitor
tHOLD−UP is the specified hold−up time
(IC,rms)max is the rms current of the bulk capacitor. Its
given computation assumes a resistive load.
Vout,min is the minimum level of the output voltage that
is acceptable for the downstream converter
(Pin)HL is the maximum level that can be virtually
delivered by the PFC stage as allowed by the timing
resistor selection. For the sake of a welcome margin,
((Pin)HL) should be selected about 30% higher than the
expected maximal input power that is:
ǒ(Pin)HL + 130% @ (Pin,avg)maxǓ
 (Pin)FF is the input power level below which the circuit


starts to reduce the switching frequency (Frequency
Fold-back)
RFF is the resistor to be placed between pin6 and
ground to control the frequency fold-back characteristic
RFmin is the resistor that can be placed between the
oscillator pin and ground to adjust a minimum
frequency. The moderate impact on the fOSC(nom) value
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19
AND8407/D






is not taken into account in the given fOSC(nom)
computation equation.
Rfb1 and Rfb2 are the feedback sensing resistors.
Rovp1 and Rovp2 are the OVP sensing resistors.
Vout,ovp is the OVP output voltage.
VREF is the internal 2.5-V voltage reference.
Rbo1 and Rbo2 are the Brown-out sensing resistors.
kBO is the Brown-out scaling down factor
ǒ
k BO +
 PRcs are the losses across Rsense. 0.2% of the maximum

Remark Regarding the Compensation:
The compensation is computed to have a phase margin in
the range of 60. The high frequency pole can be set at a
lower frequency. Practically, Cp can be increased up to 4
times the proposed value (without changing Rz and Cz) to
reduce the ripple on the Vcontrol pin and further improve the
THD. This is at the cost of a diminution of the phase margin
that can drop as low as 30.
Ǔ
R bo2
R bo1 ) R bo2
 fBO is the frequency pole created by the BO pin


external capacitor (Cbo) together with Rbo1 and Rbo2
IHYST is the internal 7-mA internal current source used
for hysteresis
(Vin,avg)boH is the averaged input voltage at which the
circuit starts operation.
Example 1: 300-W, Wide Mains Application
We select a 120-kHz frequency clamp per branch. The
maximum output power being 300 W, we estimate that the
input power can be as high as around 325 W (92% efficiency
at the lowest line – conservative figure that offers some
margin). The power capability ((Pin)HL) is set 125% higher
at 400 W.
The minimum input voltage being 90 Vrms, the brown-out
block is dimensioned so that the circuit starts operating when
the line rms voltage exceeds 81 V and a brown-out fault is
detected when the line magnitude goes below 72 V.
The regulation level is set to 390 V (Vout,nom = 390 V) and
the OVP level to 410 V (Vout,ovp = 410 V).
A 100-mF bulk capacitor is implemented.
The current resistor is selected so that it does not consume
more than about 0.2% of the maximum power (PRsense =
0.2%  (Pin,avg)max).
ǒ(Vin,avg)boH + Ǹ2 @ Vin,rmsǓ
in a traditional PFC stage.
 (Vin,avg)boL is the averaged input voltage below which
the Brown-out protection trips.
ǒ




2 Ǹ2
(V in,avg) boH + p @ V in,rms
power generally gives a good trade-off between noise
immunity and efficiency.
ROCP is the resistor that placed between the CS pin and
RCS, sets the maximum level of the input current (total
current absorbed by the two branches).
Ǔ
in a traditional PFC stage.
VBO(th) is the internal 1-V brown-out voltage reference.
Rz, Cz and Cp are the compensation components.
fc is the crossover frequency.
RCS is the current sense resistor.
Table 2. EQUATIONS − SUMMARY
Lw
90 2 @ ǒ390 * Ǹ2 @ 90Ǔ
^ 140 mH
320 @ 390 @ 120 k
(I L,pk) max + Ǹ2 @ 320 ^ 5.0 A
90
(I L,rms) max + 1 @ 320 ^ 2.1 A
Ǹ3 90
Coil Selection
A 150−mH ń 6 Apk ń 2.5 A rms coil was selected
Power
Components
MOSFET
Conduction Losses
ǒ Ǔ
(P on) max + 1 @ R DS(on) @ 320
90
3
(dV out) pk−pk +
Bulk Capacitor
ƪ
@ 1*
ƫ
8 Ǹ2 @ 90
^ 3 @ R DS(on)
3p @ 390
300
^ 20 V
100 m @ 2p @ 60 @ 390
C bulk w
(f line + 60 Hz)
2 @ 300 @ t HOLD−UP
^ 0.014 @ t HOLD−UP
390 2 * 330 2
(I C,rms) max +
http://onsemi.com
20
2
Ǹǒ
Ǔ
2
16 Ǹ2
@ 325
* 300
9p
90 @ 390
390
ǒ Ǔ
2
^ 1.3 A
AND8407/D
Table 2. EQUATIONS − SUMMARY (continued)
BO Upper Resistor
Brown-out Block
BO Bottom Resistor
BO Filtering Capacitor
ǒ
ǓǓ
ǒ
115 * 65 @ 1 * 10%
3
R bo1 +
−6
7 @ 10
R bo2 +
C bo +
ǒ
å 7200 kW
^ 7450 kW
7200 @ 10 3
^ 116 kW
65 @ 1 * 10% * 1
1
3
ǓǓ
ǒ
å 120 kW
−6
7200 k ) 120 k
^ 13.5 @ 10 ^ 220 nF
f line
2p @ 7200 k @ 120 k @ 10% @ f line
(f line + 60 Hz)
Timing Resistor
Pin3 Resistor
R t + 4026 @ 10 3 @
Oscillator Frequency
(No Frequency Foldback)
−6
f OSC(nom) ^ 52 @ 10 −12 ^ 236 kHz
220 @ 10
Clamp Frequency
per Branch
Oscillator
Fold-Forward
Power Threshold
Minimum Frequency
(per Branch)
Feedback
Resistors
ǒfsw(max)Ǔ
(P in) FF +
ǒfsw(max)Ǔ
min
+
nom
+
f OSC(nom)
2
^ 118 kHz
R FF
4700 W
@ (P in) HL +
@ 494 ^ 147 W
15810 W
15810 W
ǒ
1
ǒ
270 k*114 k
2 @ 270 k @ 220 p @ 0.22 ) In
270 k*143 k
Feedback Bottom Resistor
R fb2 + 2.5 ^ 27 kW
92 m
Feedback Upper Resistor
R fb1 + 27 k @ 390 * 1 + 4185 kW
2.5
OVP Bottom Resistor
R ovp2 + 2.5 ^ 27 kW
92 m
OVP Upper Resistor
R ovp1 + 27 k @ 410 * 1 ^ 4400 kW
2.5
Cp Capacitor of the
Type2 Compensation
Cp ^
Cz Capacitor of the
Type2 Compensation
C z + 15 @ 68 n ^ 1.02 mF
Rz Resistor of the
Type2 Compensation
Rz +
Maximum Level of the
Input Current
I in,max + 2 Ǹ2 @ 325 @ 1 *
90
ǒ
OVP Resistors
Loop
Compensation
120 k
@ Ǹ150 m @ 400 ^ 16.2 kW å 18 kW
7200 k ) 120 k
å (P in) HL + 494 W
Ǔ
ǒ
Current Limitation
Ǔ
1.06 @ 10 −6 @ 494
^ 86 nF
100 @ 10 −6 @ 20 2 @ 390 2
390
4 @ 390 * ǒǸ2 @ 90Ǔ
ǒ
Over Current Resistor
ȣ
^ 6.4 A
Ǔȧ
Ȥ
å 50 mW
−3
R OCP + 50 @ 10 @−66.4 ^ 1.52 kW
210 @ 10
å 1.5 kW
http://onsemi.com
21
å 33 kW
@ 90 + 49.8 mW
R CS + 0.2% @ 325
325 2
2
Current Sense Resistor
å 68 nF
å 1.0 mF
2
^ 31.8 kW
p @ 1.0 m @ 20
ȡ
ȧ
Ȣ
ǓǓ
^ 19.8 kHz
KBU6K
U1
R31
1800 kW
R32
1800 kW
VOUT
R41
+
C18
680 nF


Vaux2
D4
MUR550
X1
Icoil1


R15
22 kW
R14
22 kW
R18
820 kW
C22
1 nF
R39
R42
C12
4.7 nF
Type = Y1
R38
1800 kW 1800 kW
R43
IN
CM1
D15
1N4148
R11
10 kW
D14
1N4148
pfc OK
L4
+
R7
2.2 W
Q1
2N2907
VCC
C30
100 nF
D21
15 V
16 15 14 13 12 11 10
1 2 3 4 5 6 7
R33
18 kW
C25
1 mF
C15
220 pF
C20
150 pF
+
C2x
100 mF/450 V
X6
SPP11N60E
R20
10 kW
R17
2.2 W
OVP
in
R44
C1
100 nF
1800 kW 1800 kW 1800 kW 1800 kW
Type = X2
Q2
2N2907
DRV 2
R40
1800 kW
27 kW
C13
4.7 nF
Type = Y1
R122
680 kW
http://onsemi.com
22
−
C32
100 mF
C33
100 nF
C34
10 nF
R2
1 kW
DRV 2
R1
1.8 kW
R121
680 kW
C6
1 mF
150 mH
Figure 12. Application Schematic
R24
50 mW
(3 W)
9
8
OVP
in
R37
4.7 kW
R36
39 kW
C27 1 nF
R45
C28 220 nF
120 kW
−
R122
680 kW
Earth
N
L
90−265 VAC
Diodes D16 and D17 are implemented to derive the in-rush current that can take place during the start-up phase. D17 is actually optional. It should be added only if the voltage
across the current sense resistor can become so huge during the in-rush current, that it causes the current sense current (Ipin9) to exceed 10 mA.
If placed, the D17 forward voltage must be high enough not to clamp the current sense voltage (R24 voltage) in normal operation. In our application, the R24 voltage is lower than
(50 mW  6.4 A), i.e., 320 mV which is far below the D17 forward voltage.
D21, R2 and C34 are to latch off the part when VCC exceeds 17.5 V (15 V of the Zener diode + the 2.5 V of the internal comparator threshold). When a fault is detected, the circuit is
permanently shutdown until the part is reset. If such a protection is not necessary, these components can be removed and pin 10 can be grounded.
R23x
15 V
1N5406
Icoil2
D5
MUR550
VOUT
D17
X7
X4
SPP11N60
+
IIN
1N5406
VIN
R34
270 kW
Vaux2
R25
27 kW
IIN
D16
AND8407/D
390 V
−
AND8407/D
REFERENCES
[1] Joel Turchi, “Characteristics of Interleaved PFC
Stages”, Application Note AND8355,
http://www.onsemi.com/pub/Collateral/AND8355−D
.PDF
[2] Joel Turchi, “Designing a high-efficiency, 300-W,
wide mains interleaved PFC”, Application Note
AND8354,
http://www.onsemi.com/pub/Collateral/AND8354−D
.PDF
[3] Stephanie Conseil, “Performance of a 300-W, wide
mains interleaved PFC driven by the NCP1631”,
NCP1631EVB/D,
http://www.onsemi.com/pub/Collateral/NCP1631EV
B−D.PDF
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AND8407/D