AND9218/D 5 Key Steps to Designing a Compact, High‐Efficiency PFC Stage Using the NCP1602 Description www.onsemi.com This paper describes the key steps to rapidly design a Discontinuous Conduction Mode PFC stage driven by the NCP1602. The process is illustrated in a practical 160-W, universal mains application: • Maximum Output Power: 160 W • Rms Line Voltage Range: from 86 V to 265 V • Regulation output voltage: 400 V • Frequency Fold-Back when the Line Current is Less than 400 mA APPLICATION NOTE Introduction Housed in a TSOP−6 package, the NCP1602 is designed to optimize the efficiency of your PFC stage throughout the load range. Incorporating protection features for rugged operation, it is ideal in systems where cost-effectiveness, reliability, low stand-by power and high efficiency are key requirements: • Valley Synchronized Frequency Fold-Back (VSFF): The circuit operates in Critical conduction Mode (CrM) when the VCTRL pin voltage is above a preset level. When the VCTRL pin voltage goes lower than the preset level, the controller enters a Discontinuous conduction Mode and starts adding dead-time after the inductor demagnetization phase. The lower the VCTRL pin voltage, the higher the value of the dead time added. As a result, switching frequency linearly decays to about 33 kHz. • Skip Mode: SKIP Mode is optional, versions NCP1602−[B**] and NCP1602−[D**] have the SKIP mode feature, but versions NCP1602−[A**] and NCP1602−[C**] have the SKIP mode feature disabled. To optimize the Power Efficiency at low output power, a controller version using a SKIP Mode is available. When VCTRL pin voltage gets lower than the SKIP Mode threshold voltage, the power MOSFET drive is disabled. As a result the output voltage of the controller goes down, making in turn the VCTRL voltage go up and eventually above the SKIP mode threshold. VCTRL pin voltage being now above the SKIP mode threshold, the power MOSFET drive is enabled. • Low Start-Up Current and Large VCC Range: The extra low start-up consumption of the NCP1602−[**A]&[**B] versions allows the use of high-value resistors for charging the VCC capacitor. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 3 • • • The NCP1602−[**C]&[**D] versions are targeted in applications where the circuit is fed by an auxiliary power source. Its start-up level is lower than 11.25 V, allowing the circuit to be powering from a 12-V rail. Both versions feature a large VCC operating range (9.5 V to 30 V). Fast Line/Load Transient Compensation (Dynamic Response Enhancer and Soft OVP): Due to the slow loop response of traditional PFC stages, abrupt changes in the load or in the input voltage may cause significant over or under-shoots. This proprietary circuit drastically limits these possible deviations from the regulation point. Safety Protections: NCP1602 features make the PFC stage extremely robust. Among them, we can mention the Brown-Out Detection block1 that stops operation when the ac line is too low and the 2-level Current Sensing, that forces a low duty-ratio operation mode in the event that the inductor current exceeds 150% of the current limit. This situation can be caused by inductor saturation or by the bypass or boost diode short circuit. Eased Manufacturing and Safety Testing: Some elements of the PFC stage can be accidently shorted, badly soldered or damaged as a result of manufacturing or handling incidents, excessive mechanical stress or other troubles. In particular, some adjacent pins can be shorted, a single pin can be grounded or badly connected. It is often required that such open/short situations do not cause fire, smoke nor loud noise. The NCP1602 integrates enhanced functions that help address these requirements, for instance, in case of an improper pin connection (including GND) or of a short of the boost or bypass diode. Application note AND9079/D details the behavior of a NCP1612-driven PFC stage under safety tests [1]. 1The voltage of the brown-out detection block input pin (CS/ZCD) is also used to detect the line range and reduce the loop gain in high-line conditions (2-step feed-forward). 1 Publication Order Number: AND9218/D AND9218/D Rfb2 RSENSE DRV 4 5 3 2 CS/ZCD CZ EMI Filter AC Line VIN CIN RZ CP RCS2 RCS1 RCS0 IL GND VCTRL 1 L1 6 FB VCC D1 Rfb1 CBULK VBULK Load PFC STAGE DIMENSIONING Figure 1. Evaluation Board Schematic with Power and Control Circuitry www.onsemi.com 2 AND9218/D STEP 1: DEFINE THE KEY SPECIFICATIONS • fline : Line frequency. 50 Hz/60 Hz applications are • • • KCS = ((RCS1 + RCS2 ) / (KCS1 )) = 138. Internal brown-out fixed value reference voltages VboH = 819 mV and VboH = 737 mV are used for calculating the line brown-out thresholds: targeted. Practically, they are often specified in a range of 47−63 Hz and for calculations such as hold-up time, one has to factor in the lowest specified value. (Vline,rms )min : Lowest level of the line voltage. This is the minimum rms input voltage for which the PFC stage must operate. Such a level is usually 10−12% below the minimum typical voltage which could be 100 V in many countries. We will take: (Vline,rms )min = 90 V (Vline,rms )max : Highest level for the line voltage. This is the maximum input rms voltage. It is usually 10% above the maximum typical voltage (240 V in many countries). We select: (Vline,rms )max = 264 V. High Line (Vline,rms )HL and Low Line (Vline,rms )LL thresholds for internal line feedforward. Operating line voltage must be well above (Vline,rms )HL or well below (Vline,rms )LL . These thresholds values cannot be changed because VHL et VLL internal reference voltage are fixed, and they must not be changed by changing KCS value KCS = ((RCS1 + RCS2 ) / (KCS1 )) because KCS value also controls OVP2 level and line Brown-out levels. ♦ ǒV line,rmsǓ ♦ ǒV line,rmsǓ LL HL + + K CSV LL Ǹ2 K CSV HL Ǹ2 + 138 @ 1.392 + 135.9 V rms (eq. 1) Ǹ2 + 138 @ 1.801 + 175.8 V rms (eq. 2) Ǹ2 ♦ ǒV line,rmsǓ boH ♦ ǒV line,rmsǓ boL + + K CSV boH Ǹ2 K CSV boL Ǹ2 + 80 V (eq. 3) + 72 V (eq. 4) NOTE: Line brown-out thresholds cannot be modified using KCS because KCS also controls OVP2 threshold and internal line feedforward thresholds. • Vout,nom : Nominal output voltage. This is the regulation • • • • • (Vline,rms )boH : Brown-out line upper threshold (In case the controller is using an option featuring the brown-out protection. For controller option not featuring the brown-out protection, the following lines don’t apply). The circuit prevents operation until the line rms voltage exceeds(Vline,rms )boH . The NCP1602 offers a 10% hysteresis. Hence, if no specific action is taken, it will detect a brown-out situation and stop operation when the rms line voltage goes below(Vline,rms )boL that equates ((90% V Vline,rms )boH ). A brown-out event is sensed through the CS/ZCD pin and the parameter KCS, • • level for the PFC output voltage (also designated as the bulk voltage). Vout,nom must be higher than (/2 V (Vline,rms )HL ) = 373 V. 400 V is our target value (tu utilises 399 V dans les calculs) (dVout )pk−pk ): Peak-to-peak output voltage ripple. This parameter is often specified in percentage of output voltage. It must be selected equal or lower than 8% to avoid triggering the Dynamic Response Enhancer (DRE) in normal operation. Pout : Output power. This is the power consumed by the PFC load. Pout,max : Maximum output power. This is the maximum output power level which is 160 W in our application. (Pin,avg )max : Maximum input power. This is the maximum power that can be absorbed from the mains in normal operation. This level is obtained at full load, low line. Assuming an efficiency of 95% in these conditions, we will use: (Pin,avg )max = 160/95% 9 170 W Iline,max : Maximum line current obtained at full load, low line. Vctrl,th,* : CTRL pin voltage threshold below which the circuit reduces the frequency (VSFF). If the CTRL pin voltage Vctrl is lower than Vctrl,th,*, the PFC stage will permanently operates with a reduced frequency. Conversely if Vctrl is higher than Vctrl,th,*, then the PFC stage will operate in CrM (no frequency fold-back). STEP 2: POWER COMPONENTS SELECTION will determine the current rise for a given on-time. More specifically, the following equation gives the power capability of the PFC stage: In heavy load conditions, the NCP1602 operates in Critical conduction Mode (CrM). Hence, the inductor, the bulk capacitor and the power silicon devices are dimensioned as usually done with any other CrM PFC. This chapter does not detail this process, but simply highlights key points. ǒPin,avgǓ HL + V line,rms 2L 2 @ T on,max (eq. 5) The smaller the inductor, the higher the PFC stage power capability. Hence, L must be low enough so that the full power can be provided at the lowest line level: Inductor Selection The on-time of the circuit is internally limited. The power the PFC stage can deliver depends on the inductor since L www.onsemi.com 3 AND9218/D Lv ǒVline,rmsǓ Power Silicon Devices 2 LL 2 @ ǒP in,avgǓ @ T on,max Generally, the diode bridge and the power MOSFET are placed on the same heat-sink. As a rule of the thumb, one can estimate that the heat-sink will have to dissipate around: • 4% of the output power in wide mains applications (95% being generally the targeted minimum efficiency) • 2% of the output power in single mains applications. (eq. 6) max Like in traditional CrM applications, the following equations give the other parameters of importance: • Maximum Peak Current: ǒIL,pkǓ max + 2 @ Ǹ2 @ ǒPin,avgǓ max ǒV line,rmsǓ (eq. 7) In our wide-mains application, about 6.4 W are then to be dissipated. We selected a low-profile heat-sink from COLUMBIA-STAVER (reference: TP207ST/120/12.5/ NA/SP/03) whose thermal resistance has been measured to be in the range of 6°C/W. Among the sources of losses that contribute to this heating, one can list: • The diodes bridge conduction losses that can be estimated by the following equation: LL • Maximum rms Current: ǒIL,rmsǓ max + ǒIL,pkǓ max Ǹ6 (eq. 8) In our application, the inductor must then meet the following requirements: NOTE: TON,max,LL = 12.5 ms corresponds to the version NCP1602−AEA (2nd digit E) which is used on the EVB. 90 2 @ 12.5 m + 295 mH 2 @ 170 Lv ǒIL,pkǓ max + 2 @ Ǹ2 @ ǒIL,rmsǓ max + 170 ^ 5.3 A 90 P bridge + 2 @ V f @ (eq. 9) • 5.3 ^ 2.2 A Ǹ6 (Ton,max = 12.5 ms) is the value for NCP1602−AEA version and it is used in Equation 9. However, the worst case for Ton,max when used in Equation 9 is for product versions NCP1602−*G*,NCP1602−*H* and NCP1602−*I* for which the Ton,max @ Low Line is equal to 8.33 ms. When these low Ton,max versions are used, the inductor value must satisfy the criteria: Lv 90 2 @ 8.5 m + 202 mH 2 @ 170 V line(t) 2 @ ǒV out * V line(t)Ǔ 4 @ P in,avg @ V out @ L @ 8.5 m + 202 mH f SW + 2 @ ǒ390 * Ǹ2 @ 90Ǔ 4 @ 170 @ 390 @ 200 @ 10 *6 ^ 80 kHz 4 + @ R DS(on) @ 3 @ [ 1.8 @ V f V line,rms P out @ h (eq. 13) ǒ 1* ǒ P out,max h @ ǒV line,rmsǓ 8 Ǹ2 @ ǒV line,rmsǓ 3p @ V out,nom LL LL Ǔ 2 @ Ǔ (eq. 14) In our application, we have: • PBRIDGE = 3.4 W, assuming that Vf is 1 V. • (pon )max = 3.4 ⋅ RDS(on) . In our application, a low (eq. 10) RDS(on) MOSFET (0.25 W @ 25°C) is selected to avoid excessive conduction losses. Assuming that RDS(on) doubles at high temperature, the maximum conduction losses peak to about 1.7 W. The total conduction losses for the MOSFET and the diode bridge can be as high as 5.1 W. Switching losses cannot be easily computed. We will not attempt to predict them. Instead, as a rule of the thumb, we will assume a loss budget equal to that of the MOSFET conduction ones. Experimental tests will check that they are not under-estimated. The boost diode is the source of the following conduction losses:(IOUT V Vf ), where IOUT is the load current and Vf the diode forward voltage. The maximum output current being (eq. 11) For instance, at low line, full load (top of the sinusoid), the switching frequency is: ǒǸ2 @ 90Ǔ V line,rms where Vf is the forward voltage of the bridge diodes at the rated current. The MOSFET conduction losses are given by: (P on) max It is, in addition, recommended to select an inductor value that is at least 25% less than that returned by Equation 9 for a healthy margin. A 200-mH/6-Apk inductor (ref: 750370081 from WÜRTH ELEKTRONIK) is selected. It consists of a 10:1 auxiliary winding for zero current detection. One can note that the switching frequency in CrM operation depends on the inductor value: f SW + Ǹ2 P out 2 p @ h (eq. 12) www.onsemi.com 4 AND9218/D nearly 0.4 A, the diode conduction losses are in the range of 0.4 W (assuming Vf = 1 V). PDIODE = 0.4 W C bulk w pk*pk + P out,max C bulk @ w @ V out,nom ǒI c,rmsǓ (eq. 15) where (w = 2p V fline ) is the line angular frequency. This ripple must keep lower than ±4% of the output voltage (8% peak-to-peak) in order to avoid triggering the Dynamic Response Enhancer (DRE) system while in steady state. Taking into account the line frequency minimum value (47 Hz), this leads to: 160 8% @ 2p @ 47 @ 399 2 ^ 42 mF ^ 2 @ P out,max @ t HOLD*UP 2 V out,nom * V out,min 2 max (eq. 18) ^ (eq. 19) Ǹ ǒP ȡǸ32 Ǹ2 @ ȧ 9p ǸǒV Ȣ ȣ ǒP ȧ* V Ȥ 2 Ǔ in,avg max Ǔ @ V out,nom line,rms LL out,max Ǔ 2 out,nom In our application, we have: I c,rms ^ (eq. 16) • Hold-Up Time Specification: C bulk w ^ 87 mF The rms current depends on the load characteristic. Assuming a resistive load, we can derive the following approximate expression of its magnitude2: There generally are three main criteria / constraints when defining the bulk capacitor: • Peak-to-Peak Low Frequency Ripple: C bulk w 399 2 * 350 2 • Rms Capacitor Current: Output Bulk Capacitor ǒdV outǓ 2 @ 160 @ 10 m Ǹ ǒǸ Ǔ 32 Ǹ2 170 @ Ǹ90 @ 399 9p 2 * ǒ160 Ǔ 399 2 ^ (eq. 20) ^ 1.06 A (eq. 17) 2It remains wise to verify the bulk capacitor heating on the bench! Hence, a 10-ms hold-up time imposes: STEP 3: BULK VOLTAGE MONITORING AND REGULATION LOOP As shown by Figure 1, the feedback arrangement consists of: • A resistor divider that scales down the bulk voltage to provide pin FB with the feedback signal. The upper resistor of the divider generally consists of three or four series resistors for safety considerations (see R8, R9 and R10 of Figure 7). If not, any accidental shortage of this element would apply the high voltage output to the controller low-voltage pin and destroy it. • A filtering capacitor that is often placed between pin FB and ground to prevent switching noise from distorting the feedback signal. A 1-nF capacitor is often implemented. Generally speaking, the pole it forms with the feedback resistors must remain at a very high-frequency compared to the line one. Practically, C fb v I FB + V REF R fb2 + 2.5 R fb2 (eq. 21) Trade-off between losses and noise immunity dictate the choice of this resistor. Resistors up to 56 kW (IFB ≈ 50 mA) generally give good results. Higher values can be considered if allowed by the board PCB layout. Please note anyway that a 250-nA sink current (500 nA max. on the −40° to 125°C temperature range) is built-in to pull the feedback pin down and disable the driver if the pin is accidently open. If IFB is set below 50 mA, the regulation level may be significantly impacted by the 250-nA sink current. When the bottom resistor is selected, select the upper resistor as follows: R fb1 + R fb2 @ 1 150 @ ǒR fb1 Ŧ R fb2Ǔ @ f line ǒ V out,nom V REF Ǔ *1 (eq. 22) In our application, we select a 27-kW value for Rfb2 (IFB ≈ 92 mA). As for Rfb1, two 1800-kW resistors are placed in series with a 680-kW one. These normalized values precisely give: (Rfb1 = 4.28 MW), leading to a nominal 399-V regulation level, which is acceptable. generally give good results. • A type-2 compensation network. Consisting of two capacitors and of one resistor, this circuitry sets the crossover frequency and the loop characteristic. Compensating the Loop In steady-state the feedback being in the range of the 2.5-V regulation reference voltage, the feedback bottom resistor (Rfb2 of Figure 1 or R11 of Figure 8) sets the bias current in the feedback resistors as follows: The loop gain of a PFC boost converter is proportional to the square of the line magnitude if no feed-forward is applied. Hence, this gain almost varies by an order of magnitude in universal mains conditions. The CS/ZCD pin www.onsemi.com 5 AND9218/D voltage is processed by the NCP1602 in order to get an internal voltage representative of the line voltage value. The NCP1602 uses this information to perform a 2-level feed-forward function: in high-line that is detected when Vline,rms happens to exceed (Vin,rms )HL , the PWM gain is divided by 3 (actually the tON,max value is divided by 3) compared to a low-line state (which is set if Vline,rms is less than (Vin,rms )HL for 25 ms – see Figure 2 and Figure 4). Not only the PWM gain is modified, Loop Gain (−) Vline,rms (V) (Vin,rms)BOH e.g.: 80 V (Vin,rms)LL e.g.: 136 V (Vin,rms)HL e.g.: 176 V Figure 2. 2-Step Feed-Forward Limits the Loop Gain Variation with Respect to Line Using small signal methods described in [1] and [2], we can derive two small-signal transfer functions of our PFC stage (one for High Line, one for Low Line): • Low-Line Small Signal Transfer Function: V out(s) V control(s) + 640000 @ L @ V out,nom The coefficient 640000 is for tON,max = 12.5 ms and 1920000 for tON,max = 12.5 ms/3 (product versions [*D*],[*E*]&[*F*] (The EVB is provided with the [*F*] version which is the default version), for other product versions with different tON,max , just calculate the new coefficient using the formula 8 V/tON,max e.g. 640000 = 8 V/12.5 ms). (eq. 23) 2 V in,rms @ R load Vout,nom is the nominal regulation level of the PFC output. @ 1)s@ 1 R load@C bulk 2 • High-Line Small Signal Transfer Function: V out(s) V control(s) 2 + V in,rms @ R load 1920000 @ L @ V out,nom PFC stages must be slow. More practically, high PF ratios require the low regulation bandwidth to be in the range of 20 Hz or lower. Hence, sharp variations of the load result in excessive over and under-shoots. These deviations are effectively contained by the NCP1602 Dynamic Response Enhancer together with its accurate over-voltage protection. Still however, a type-2 compensation (R1,C1,C2) is recommended as shown in Figure 3. (eq. 24) @ 1)s@ 1 R load@C bulk 2 Where: Cbulk is the bulk capacitor. Rload is the load equivalent resistance. L is the PFC coil inductance. www.onsemi.com 6 AND9218/D VCONTROL VOUT ICONTROL R1 C2 C1 Rfb1 OTA FB To PWM Comparator − + Rfb2 + VREF Figure 3. Regulation Trans-Conductance Error Amplifier, Feed-Back and Compensation Network The output to control transfer function brought by the type-2 compensator is: V control(s) V out(s) + R1 C1 R 0 ǒC 1 ) C 2 Ǔ 1) @ ǒ 1 sR 1C 1 1 ) sR 1 @ C 1C 2 C 1)C 2 The crossover frequency is selected as low as possible but higher or equal to the PFC boost stage pole at full load: fp + Ǔ (eq. 25) The phase margin is generally set between 45 and 70 degrees. Where (R0 = Vout,nom / (Vref V GEA )), GEA being the 200-mS error amplifier transconductance gain, Vout,nom , the bulk nominal voltage and VREF, the OTA 2.5-V voltage reference. In our application, if we target a 15-Hz crossover frequency and a 60-degree phase margin (p/3 in radians), we have: Applying the compensation method described in [2] and [3] we obtain the following dimensioning equations: G0 + C2 + C1 + R1 + ǒV line,rmsǓ 2 LL 1 ^ 2.4 Hz p @ R load,min @ C bulk G0 + 90 2 @ 950 640000 @ 200 @ 10 *6 @ 390 ǒ @ R load,min (eq. 26) 640000 @ L @ V out,nom ǒ C2 + Ǔ G 0 @ tan p * f m 2 ^ 154 Ǔ 154 @ tan p * p 2 3 2 @ p 2 @ 14 2 @ 950 @ 136 @ 10 *6 @ 780 @ 10 3 (eq. 27) ^ ^ 200 nF å Let’s Choose 220 nF. 2 2 @ p 2 @ f c @ R load,min @ C bulk @ R 0 G0 2 @ p @ fc @ R0 C1 + * C2 * C2 ^ ^ 1.9 mF å Let’s Choose 2.2 mF. R load,min @ C bulk 2 @ C1 R1 + Where: (Vline,rms )LL is the rms voltage of the line when at its lowest level (90 V in our case). G0 is static gain at the lowest level of the line ((Vline,rms )LL ). V out,nom 2 P out,max + 950 @ 136 @ 10 *6 2 @ 2.2 @ 10 *6 ^ 29 kW å Let’s Choose 22 kW. Soft and Fast Overvoltage Protection (SOVP & FOVP): These functions check that the output voltage is within the proper regulation window by the monitoring of FB pin voltage: • The Fast Over-Voltage Protection (FOVP) trips if the bulk voltage reaches an abnormally high level (Vout,fovp = 107% ⋅ Vout,nom ) and disables de DRV pin (tON = 0) hence the name Fast. fm is phase margin (in radians). fc is the targeted crossover frequency Rload,min is the load equivalent resistor at full load: R load,min + 154 2 @ p @ 15 @ 780 @ 10 3 399 2 ^ 995 160 www.onsemi.com 7 AND9218/D When the feedback network is properly designed and correctly connected, the bulk voltage cannot exceed the level set by the Soft OVP function (Vout,sovp = 105% ⋅ Vout,nom ). If soft OVP threshold is reached, for example during no-load start-up, the on-time is gradually reduced instead of disabling the drive pin (tON = 0) hence the name soft. The FOVP threshold is set 2% higher than the soft OVP comparator. Taking KCS = 143.1 and the OVP2 internal threshold levels VOVP2H = 3.175 V and VOVP2L = 3.093 V we can calculate the two OVP2 thresholds for Vout (also named Vbulk ): V out,OVP2H + K CS @ V OVP2H + 143.1 @ 3.175 + 454.3 V (eq. 30) V out,OVP2L + K CS @ V OVP2L + 143.1 @ 3.093 + 442.6 V These threshold must be placed well above the Fast OVP threshold in order to be operational in case of an OVP failure, due for example to wrong FB resistor value or to FB resistor failure. The higher Fast OVP threshold being equal to 108% of Vout,nom and for Vout,nom = 400 V, this will give 1.08 × 400 = 432 V which is lower than the lower OVP2 threshold of 442.6 V. The values of RCS1 and RCS2 must be chosen high for not consuming too much power during standby. During standby, there is no switching and the voltage seen by RCS1 in series with RCS2 is a constant voltage equal to: Undervoltage Protection (UVP): At start-up, the DRV pin is enabled if VFB rises above an internal threshold voltage named VUVPH (VUVPH = 625 mV). After start-up, the DRV pin is disabled if VFB drops below an internal threshold voltage named VUVPL (VUVPL = 300 mV). Second Overvoltage Protection (OVP2): A second overvoltage protection (OVP2) is added for redundancy and safety reasons. The OVP2 is using the pin CS/ZCD voltage. During demagnetization time, the CS/ZCD voltage is roughly equal to KCS Vout if we neglect the voltage drop across the boost diode. If the CS/ZCD voltage rises above an internal OVP2 threshold named VOVP2H the power MOSFET drive is disabled for 800 ms and enabled after the 800-ms period if the CS/ZCD voltage sensed during demagnetization time has fallen under VOVP2H internal low voltage reference for OVP2 protection. It is recommended that the parameter KCS be equal to the value 138 for the circuitry processing the CS/ZCD voltage to work well. K CS + R CS1 ) R CS2 R CS2 V mains,rms @ Ǹ2 The power consumed during standby PCS,STBY being given by: P CS,STBY + ǒVmains,rms @ Ǹ2Ǔ R CS1 ) R CS2 2 (eq. 32) With: RCS1 = 5.1 MW + 240 kW + 240 kW RCS2 = 39 kW We get: For Vmains,rms = 86 V this will give PCS,STDBY = 2.6 mW For Vmains,rms = 110 V this will give PCS,STDBY = 4.3 mW For Vmains,rms = 230 V this will give PCS,STDBY = 18.8 mW For Vmains,rms = 265 V this will give PCS,STDBY = 25.0 mW (eq. 28) Targeting KCS = 138, the following values have been found: RCS1 = 5.1 MW + 240 kW + 240 kW RCS2 = 39 kW We finally get: KCS = 143.1 CSZCD Resistors Bridge – Resistor value choice and PCB layout guideline When the RCS resistor bridge totals a resistance in the MW range, it is very sensitive to parasitic capacitances as low as few hundreds of fF. Parasitic capacitances can be found between RCS resistors nodes and (GND or power MOSFET drain). These parasitic capacitances effect can lead to permanent false fault detection events: OCP, OVS or OVP2 triggering, making the controller unable to operate and regulate Vout properly. One easy way to avoid the effect of parasitic capacitors is to reduce the value of the resistors, while keeping the dividing ratio KCS around 138. Reducing the CS/ZCD bridge resistors value (reducing RCS1 + RCS2 ) is at the expense of standby power consumption which will increase. It has to be mentioned that [(RCS2 ⎢⎢ RCS1 ) + RCS0 ]. CCS must be kept close to a 500-ns time constant. CCS being the total capacitance between pin CS/ZCD and pin GND. The parasitic capacitance of this pin being estimated to be 10 pF then, if no external capacitor is added: ƪǒRCS2 ø RCS1Ǔ ) RCS0ƫ @ CCS + 487 ns (eq. 31) (eq. 29) If an additional ceramic capacitor is added between pin CS/ZCD and pin GND, its capacitance value must be added to the 10-pF parasitic capacitance of the previous formulas. The reason of meeting this time constant value is that there is an internal circuitry connected to the pin CS/ZCD which cancels the pole made by RCS2 + RCS0 and the CS/ZCD to GND total capacitance (CCS ). www.onsemi.com 8 AND9218/D Bench experiments have proven SMD1206 & 0805 superiority, parasitic capacitance wise, over trough hole resistors for RCS1 , RCS2 and RCS0 resistors. RCS0 must be placed as close as possible to CS/ZCD pin voltage and RCS1 and RCS2 as close as possible to RCS0 . PCB traces connecting the RCSi resistors must be kept as short as possible, the width of the trace being as small as possible (minimum parasitic capacitance) It is wise to keep a safety distance of 1 cm between the high value resistors of the CSZCD brige and DRV, Vin , Vdrain copper traces to avoid coupling. Note than while decreasing the value of RCS1 and RCS2 , RCS0 must be increased in order to meet the 500-ns time constant made with RCS resistor and CCS total capacitance. If RCS1 + RCS2 value is well under 1 MW, three 200-V SMD1206 resistors can be placed in series but when the RCS1 + RCS2 value is above 1 MW it has been found that the three SMD 200-V resistors in series lead to false fault tripping (e.g. OVP2 false triggering). In that case, it is advised to have one 500-V SMD high-value resistor on the drain side (e.g. 5.1 MW for The EVB) with two low value (e.g. 240 kW) 200-V SMD resistors in series like the values used in the previous calculations. This is to avoid inter-resistor capacitance to GND to have difficulties to be discharged before a tON cycle. Experience shows that it is not recommended to follow the common sense reasoning of using 3 equal value resistors to balance the drain voltage. STEP 4: INPUT VOLTAGE SENSING – BROWN-OUT In a boost converter, considering a zero inductor average voltage at steady state,averaged drain voltage is equal to the Vin voltage (rectified Vline voltage) . The VCSint voltage of Figure 4 is equal to Rsense V Iind during the on-time and equal to Vdrain /KCS during off-time. Thanks to the DRV driven switches, the input of the Rsns /Csns low pass filter will be vdrain (t)/KCS and the output of the same filter v(t) will be vin (t)/KCS or abs(vline (t)/KCS ) V SNS(t) + Abs ǒ V line(t) K CS Ǔ (eq. 33) DRAIN RSNS RSNS VSNS RCS1 RCS0 DRVBAR CS/ZCD Pin Re-Shaping Filter CSNS CSNS VCSint CCS DRV ZCD RF RCS2 CF SOURCE Figure 4. Brown-Out and Line Range Detection Block brown-out internal reference voltage VBOL = 737 mV for 50 ms, then brown-out is enabled. After brown-out is confimed, drive pulses are not immediately disabled, instead, a 30-mA current source is applied to the VCTRL pin to gradually reduce Vctrl . As a result, the circuit only stops pulsing when the static OVP function is activated (that is when Vctrl reaches the SKIP detection threshold). At that moment, the circuit stops switching. This method limits any risk of false tripping. The following formulas are showing The product codes [C**] and [D**] have the Brown-out feature enabled. There are two brown-out levels, high and low. By default and before start-up, the brown-out is enabled. When VSNS (VSNS is a low-pass filtered scaled down Vline ) sensed thru CS/ZCD pin goes higher than the internal reference voltage VBOH = 819 mV the brown-out is reset and allows the controller to start switching. After brown-out is reset, and switching activity starts, Vline continues to be sensed thru CS/ZCD pin and when VSNS falls under the www.onsemi.com 9 AND9218/D how internal brown-out reference voltages translate to line rms voltage thresholds. ǒV line,rmsǓ ǒV line,rmsǓ BOH BOL + + K CS @ V BOH Ǹ2 K CS @ V BOL Ǹ2 + 143.1 @ 0.819 + 83 V Ǹ2 (eq. 34) + 143.1 @ 0.734 + 74 V Ǹ2 (eq. 35) VSNS goes above VHL = 1.801 V, the controller enters the high line state and when VSNS goes under VLL = 1.392 V it toggles into the the low line state. Translation of high line to low line thresholds and vice versa into line rms voltage is given by the following equations. Low line to high line threshold is: ǒV line,rmsǓ Where: VBOH is the 819-mV upper brown-out internal threshold. VBOL is the 734-mV lower brown-out internal threshold. HL + K CS @ V HL Ǹ2 143.1 @ 1.801 + 182 V Ǹ2 + (eq. 36) High line to low line threshold is: ǒV line,rmsǓ LL + K CS @ V LL Ǹ2 + 143.1 @ 1.392 + 141 V Ǹ2 (eq. 37) High and Low Line Detection An internal digital flag named LLINE is used to detect if the line voltage is low (LLINE = 1) or high (LLINE = 0). This flag is used to change the on-time in order to realize a two-level line feed-forward and reduce the spread of the small signal open-loop cut-off frequency. There is also an abrupt change in VCTRL when transitioning from high line to low line and vice versa. Like in the brown-out detection circuit, the internal VSNS is compared to two levels defining an hysteresis between high line and low line states. When X2 Capacitors Discharge: RX1 and RX2 are designed for safety considerations. In general, they must be selected so that the series combination of (RX1 + RX2 = 2RX ) form with the X2 EMI capacitors a time constant less than 3 s (?? Habituellement, la norme impose une constant de temps de 1 s). In our case, two 1-MW resistors (RX1 = RX2 = RX = 1 MW) are implemented so that with the selected X2 capacitors, it leads to a 1.8-s discharge time constant, which offers a comfortable margin. STEP 5: CURRENT SENSE NETWORK The current sense circuitry consists of a current sensing resistor Rsense . Hence, our 80-mW current sense resistor will dissipate about 278 mW at full load, low line. => Computing Rsense => Zero Current Circuitry The circuit detects an over-current situation if the voltage across the current sense resistor exceeds 0.5 V. Hence: The ZCD circuitry is show in Figure 5. The basic idea is to get the ZCD information from Vdrain voltage crossing the Vin voltage. Vdrain and Vin voltages being external to the controller, the schematic of Figure 5 will bring these voltages internally but scaled-down by KCS . 0.5 R sense + ǒIL,pkǓ (eq. 38) max Combining this equation with Equation 8 leads to: R sense + ǒV line,rmsǓ LL 4 Ǹ2 @ ǒP in,avgǓ K CS + (eq. 39) 90 ^ 0.094 W Ǹ 4 2 @ 170 (eq. 40) In order to have a bit of margin, a 80-mW resistor is selected. Rsense losses can be computed using the equation giving the MOSFET conduction losses where Rsense replace RDS(on) : ǒPRcsǓ max + @ 4 @ R sense @ 3 ǒ 1* ǒ ǒPin,avgǓ max ǒV line,rmsǓ 8 Ǹ2 @ ǒV line,rmsǓ 3p @ V out,nom LL LL Ǔ Ǔ R CS2 (eq. 42) In a boost converter, the averaged drain voltage which is one pin of the boost inductor is equal to the Vin voltage which is on the other pin of the boost inductor and this is because the average voltage drop across the inductor is zero volts if we neglect the series resistance of the inductor. Scaled-down drain voltage is brought inside the controller by RCS1 , RCS2 bridge and the re-shaping filter so the internal node voltage VCSint will be: max In our practical case, R sense + R CS1 ) R CS2 V CSint(t) + 1 @ V drain(t) K CS (eq. 43) Thanks to a low pass filter the two inputs of the ZCD comparator will be like comparing Vin (t) and Vdrain (t): 2 @ V *(t) + (eq. 41) 1 @ V in(t) K CS (eq. 44) 1 @ V drain(t) V )(t) + K CS www.onsemi.com 10 AND9218/D The ZCD digital signal resulting from the comparison Vin (t) and Vdrain (t) is used for synchronizing the power MOSFET turn-on. The power MOSFET turn-on event is synchronized with the falling edge of ZCD signal. The only thing to care about is that KCS value is as close as possible to 138, to ensure a correct operation of the ZCD comparator. Vdrain 5.1 MW/ 500 V RCS1a 240 kW RCS1b 240 kW RCS1c ZCD RCS0 DRV CS/ZCD Re-Shaping Filter 10 kW 39 kW CSint Low Pass Filter CCS RCS2 DRV Vsource 80 mW Rsense Figure 5. NCP1602 Zero Crossing Detection with Typical Component Values The NCP1602 integrates leading edge blanking on the CS/ZCD pin that prevents the need for a filtering capacitor. No any capacitor is allowed in the CS/ZCD circuitry as this will result in distorting the CS/ZCD signal leading to wrong or no ZCD detection. Care must be taken when probing the CS/ZCD signal with a scope probe as the scope probe will add typically a 10-pF capacitance in parallel with the package parasitic capacitance CCS . This additional capacitance will distort the CS/ZCD signal and result in degraded ZCD detection performance (we may lose demagnetization detection and start triggering a 200 ms watchdog timer, and also loose valley turn-on). K CS + N prim N aux @ R CS1 ) R CS2 R CS2 (eq. 45) KCS = 138 must always be the target value. This new KCS formula allows to use ten times a lower RCS1 value, given the fact that Nprim /Naux = 10 for the transformer used on our EVB. With this approach, a lower voltage is carried and also low RCS1 values reduce the sensitivity to parasitic capacitors. One benefit of this circuitry is that there is no current consumption during standby (No switching activity hence no Vaux voltage). It has to be mentioned that product version with brown-out feature activated will not operate with this circuitry so product versions [C**] and [D**] must not be used with this Vaux circuitry. Everything else will work exactly the same as already described when the power MOSFET drain voltage is used instead of auxiliary voltage Vaux . It is just that KCS formula is slightly different. Using the Auxiliary Winding Voltage Vaux for the CSZCD Circuitry It is possible to use the schematic shown in Figure 6 to generate the signal of CS/ZCD pin. Thanks to the auxiliary winding voltage capacitor Caux , resistor Raux and diode Daux1 , it is possible to generate at the cathode of Daux1 diode a voltage equal to the power MOSFET drain voltage multiplied by the auxiliary (Naux ) to primary (Nprim ) transformer turns ratio. The parameter KCS previously described is now defined by: www.onsemi.com 11 AND9218/D Naux / Nprim = 0.1 Caux Vdrain Raux Vaux 100 W 47 nF Daux1 1N4148 300 kW RCS1 ZCD RCS0 DRV CS/ZCD Re-Shaping Filter 27 kW 22 kW RCS2 Line Voltage Extraction for ZCD CCS Vsource 80 mW Rsense Figure 6. CS/ZCD Circuitry using Auxilliary Winding Voltage with Typical Components Values Layout and Noise Immunity Considerations The NCP1602 is not particularly sensitive to noise. However, usual layout rules for power supply design apply. Among them, let us remind the following ones: • The loop area of the power train must be minimized. • Star configuration for the power ground that provide the current return path. • Star configuration for the circuit ground. • The circuit ground and the power ground should be connected by one single path, no loop is allowed. • This path should preferably connect the circuit ground to the power ground at a place that is very near the grounded terminal of the current sense resistor (Rsense ). • A 100 or 220-nF capacitor should be placed between • • the circuit VCC and GND pins, with minimized connection length. The RCSx resistors must be placed as close as possible to the CS/ZCD pin, and capacitance coupling with GND or any other signal must be avoided. It is recommended to place a filtering capacitor on the FB pin to protect the pin from possible surrounding noise. It must be small however not to distort the voltage sensed by the FB pin. See the corresponding sections for more details. www.onsemi.com 12 AND9218/D SUMMARY OF THE MAIN EQUATIONS Table 1. DESIGN STEPS TABLE Step Step 1: Key Specifications Components Formula Comments • fline : Line frequency. It is often specified in a range of 47−63 Hz for 50 Hz/60 Hz applications. • (Vline,rms )LL : Lowest Level of the line voltage, e.g., 90 V. • (Vline,rms )HL : Highest Level for the line voltage (e.g., 264 V in many countries). • (Vline,rms )BOH : Brown-Output Line Upper Threshold. The circuit prevents operation until the line rms voltage exceeds this level. • Vout,nom : Nominal Output Voltage. • (dVout )pk-pk : Peak-to-Peak output voltage low-frequency ripple. • tHOLD-UP : Hold-up Time that is the amount of time the output will remain valid during line drop-out. • Vout,min : Minimum output voltage allowing for operation of the downstream converter. • Pout,max : Maximum output power consumed by the PFC load, that is, 160 W in our application. • (Pin,avg )max : Maximum power absorbed from the mains in normal operation. Generally obtained at full load, low line, it depends on the efficiency that, as a rule of a thumb, can be set to 95%. Step 2: Power Components Input Diodes Bridge Losses P bridge + 2 @ V f @ Inductor MOSFET Conduction Losses (P on) max Bulk Capacitor Constraints C bulk v ^ max ǒ 1* V line,rms P out @ h In our application : 90 2 @ 12.5 m + 295 mH Lv 2 @ 170 @ T on,max max ǒPin,avgǓ ǒIL,pkǓ + ǒIL,pkǓ max ǒV line,rmsǓ ǒdV outǓ pk*pk ǒIL,rmsǓ max ǒ P out,max h @ ǒV line,rmsǓ LL 3p @ V out,nom LL Ǔ @ 2 V out,nom * V out,min 2 Ǔ in,avg max ȣ ǒP ȧ* V Ȥ @ V out,nom www.onsemi.com 13 + 5.3 ^ 2.2 A Ǹ6 These 3 equations quantify the constraints resulting from the low-frequency ripple ((dVout )pk-pk that must be kept below 8%), the hold-up time requirement and the rms current to be sustained. 2 @ P out,max @ t HOLD*UP Ǔ max Ǔ @ w @ V out,nom line,rms LL 170 ^ 5.3 A 90 RDS(on) is the drain-source on-state resistance of the MOSFET 2 ^ Ǹ + 2 @ Ǹ2 @ Ǹ6 8 Ǹ2 @ ǒV line,rmsǓ ǒP ȡǸ32 Ǹ2 @ ȧ 9p ǸǒV Ȣ max LL P out,max C bulk w ǒI c,rmsǓ max 4 + @ R DS(on) @ 3 @ LL + 2 @ Ǹ2 @ ǒIL,rmsǓ 1.8 @ V f Vf is the forward voltage of any diode of the bridge. It is generally in the range of 1 V or less. 2 2 @ ǒP in,avgǓ max [ V line,rms ǒVline,rmsǓ Lv ǒIL,pkǓ Ǹ2 P out 2 p @ h 2 out,max Ǔ out,nom 2 AND9218/D Table 1. DESIGN STEPS TABLE (continued) Step Components Step 3: Bulk Voltage Monitoring and Regulation Loop Resistor Divider Formula R fb2 + ǒ Compensation G0 + C2 + V REF Ǔ *1 IFB is the bias current that is targeted within the resistor divider. Values in the range of 50 mA to 100 mA generally give a good trade-off between losses and noise immunity. 1 150 @ ǒR fb1 Ŧ R fb2Ǔ @ f line ǒV line,rmsǓ 2 LL @ R load,min 640000 @ L @ V out,nom ǒ Ǔ CFB is the filtering capacitor that can be placed between the FB pin and ground to increase the noise immunity of this pin. (see Figure 3) G 0 @ tan p * f m 2 2 2 @ p 2 @ f c @ R load,min @ C bulk @ R 0 C1 + G0 2 @ p @ fc @ R0 * C2 R load,min @ C bulk R1 + OVP and UV OVP 2 2.5 I FB V out,nom R fb1 + R fb2 @ C fb v Comments 2 @ C1 107% of Vout,nom for OVP V out,UVPx + K FB @ V UVPx OVP and UV are sensed by the feedback network (KFB ) as OVP2 is sensed by the CS/ZCD resistor network (KCS ). V out,OVP2x + K CS @ V OVP2x Step 4: Input Voltage Sensing Input Voltage Sensing K CS + ǒV line,rmsǓ R CS1 ) R CS2 R CS2 BOH ǒV line,rmsǓ BOL ǒV line,rmsǓ HL ǒV line,rmsǓ LL + + + + K CS @ V BOH Ǹ2 K CS @ V BOL Ǹ2 K CS @ V HL Ǹ2 K CS @ V LL Ǹ2 www.onsemi.com 14 Input voltage is sensed through the CS/ZCD pin (Vline,rms )BOH line rms level above which the circuit starts operating the circuit stops switching when line rms level falls under (Vline,rms )BOL . When line rms voltage goes above (Vline,rms )HL we enter High Line state and when line rms voltage below (Vline,rms )LL we enter Low Line state AND9218/D Table 1. DESIGN STEPS TABLE (continued) Step Components Step 5: Current Sense Network Input Voltage Sensing Formula R CS + ǒPRcsǓ max + @ Current Controlled Frequency Fold-Back ǒV line,rmsǓ R FF + 1* ǒ max ǒPin,avgǓ max ǒV line,rmsǓ LL 8 Ǹ2 @ ǒV line,rmsǓ 3p @ V out,nom 25 Ǹ2 @ ǒV line,rmsǓ C FF v 112 @ L @ ǒI lineǓ BOH th 1 150 @ I line @ R FF www.onsemi.com 15 (Vline,rms )LL is the line rms voltage lowest level in normal condition (e.g., 90 V). Vout,nom is the output nominal level (e.g., 390 V). (Pin,avg )max is the maximum input power of your application. LL 4 Ǹ2 @ ǒP in,avgǓ 4 @ R CS @ 3 ǒ Comments Ǔ LL 2 @ Ǔ (Iline )th is the line current level below which the NCP1612 starts reducing the frequency. 16 Figure 7. Application Schematic − Power Section www.onsemi.com L N Earth C3c C3b C3a S2b 86−265 V rms F1 S2a CM1 VLINE C5a 220 nF 400 V C1 1 nF Type = Y C2 1 nF Type = Y R1 1 MW R2 1 MW IN C2 22 nF Type = X2 U1 GBU406 220 nF Type = X2 C5b 220 nF 400 V VIN S1b D4 1N4148 Socket for External VCC Power Source S1a R6 22 W D3 1N4148 L2 200 mH (np/ns = 10) C7 22 mF 50 V R5 2.2 W D2 1N5406 R10 10 kW DZ2 33 V R3 80 mW 3W Q1 IPA50R250 D1 MUR550 C6a 68 mF 450 V Rth1 B57153S150M C6b 68 mF 450 V BULK Vcc GND Vsource Vbulk DRV Vdrain Vaux AND9218/D (Detailed Schematic for our 160-W Evaluation Board, Universal Mains Application) SCHEMATICS www.onsemi.com 17 C8 1 nF R11 27 kW C9 2.2 mF R12 22 kW C10 220 nF R27 0R C11 NC C13 100 nF DRV 4 3 CS/ZCD Top View VCC 5 2 GND 6 FB 1 R27 is used as a strap VCTRL R10 1800 kW R9 1800 kW R8 680 kW S3 R36 NC R31 10 kW R32 4.7 MW R33 1 MW R34 NC R42 NC R39 NC R30 0W C12 NC Q2 BSS127 R37 NC R38 NC R7 0W R24 240 kW D5 NC R41 NC R22 5.1 MW/ 500 V L2 200 mH (np/ns = 10) R40 NC R21 39 kW R23 240 kW D6 NC C30 NC GND DRV Vsource Vdrain Vcc Vbulk Vaux AND9218/D Figure 8. Application Schematic for ZCD Sensing using Power MOSFET Drain Voltage − Control Section AND9218/D Figure 9. NCP1602 Low Profile Evaluation Board Top View Showing Power Circuitry Figure 10. NCP1602 Low Profile Evaluation Board Bottom View Showing the Control Circuitry CONCLUSIONS This paper summarizes the key steps when dimensioning a NCP1602−driven PFC stage. The proposed approach being systematic, it can be easily applied to other applications. www.onsemi.com 18 AND9218/D REFERENCES [3] Joel Turchi, “Compensating a PFC stage”, Tutorial TND382/D available at: http://www.onsemi.com/pub_link/Collateral/ TND382−D.PDF. [4] NCP1602/D Data Sheet, http://www.onsemi.com/pub_link/Collateral/ NCP1602−D.PDF. More details on the circuit operation can be found in its data sheet [4]. [1] Joel Turchi, “Safety tests on a NCP1612-driven PFC stage”, Application note AND9064/D, http://www.onsemi.com/pub_link/Collateral/ AND9064−D.PDF. [2] Joel Turchi, “Compensation of a PFC stage driven by the NCP1654”, Application note AND8321/D, http://www.onsemi.com/pub_link/Collateral/ AND8321−D.PDF. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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