Interleaved PFC Agenda Introduction: Basics of interleaving Main benefits NCP1631: a novel controller for interleaved PFC Out-of-phase management The NCP1631 allows the use of smaller inductors Main functions Experimental results and performance General waveforms Efficiency Conclusion 2 Interleaved PFC Two small PFC stages delivering (Pin(avg) / 2) in lieu of a single big one IL1 Ac line Iin (t ) ID1 1 8 2 7 3 6 4 5 NCP1601 Vin (t ) EMI Filter IL(tot ) IL 2 ID 2 1 8 2 7 3 6 4 5 NCP1601 ID(tot ) Cbulk Vout LOAD If the two phases are out-of-phase, the resulting currents (IL(tot)) and (ID(tot)) exhibit a dramatically reduced ripple. 3 Interleaved Benefits More components but: A 150 W PFC is easier to design than a 300 W one Modular approach Better heating distribution Extended range for Critical Conduction Mode (CrM) Smaller components (help meet strict form factor needs – e.g., flat panels) Two DCM PFCs look like a CCM PFC converter… • Eases EMI filtering and reduces the output rms current 4 Input and Output Current What is the ripple of the IL(tot) total input current? What is the ripple of the ID(tot) total output current? IL1 Ac line Iin (t ) ID1 1 8 2 7 3 6 4 5 NCP1601 Vin (t ) EMI Filter IL(tot ) IL2 ID2 1 8 2 7 3 6 4 5 NCP1601 5 ID(tot ) Cbulk Vout LOAD Input Current Ripple at Low Line When Vin remains lower than Vout / 2, the input current looks like that of a CCM, hysteretic PFC (IL(tot)) swings between two nearly sinusoidal envelops Peak, averaged and valley current @ 90 Vrms, 320 W input (Vout = 390 V) Peak, valley and averaged Input Current (A) 7 6 Iin(t) IL(tot) Envelop for the peak currents 5 4 3 Envelop for the valley currents 2 1 0 0.00% 25.00% 50.00% 75.00% time as a percentage of a period (%) 6 100.00% Input Current Ripple at High Lline When Vin exceeds (Vout / 2), the valley current is constant! ⎛ Vout It equates ⎜⎜ ⎝ 2 ⋅ Rin ⎞ ⎟⎟ where Rin is the PFC input impedance ⎠ Peak, averaged and valley current @ 230 Vrms, 320 W input (Vout = 390 V) Peak, valley and averaged Input Current (A) 3.0 2.5 Iin(t) IL(tot) 2.0 1.5 1.0 0.5 0.0 0.00% Pin(avg )⋅Vout 25.00% 50.00% 75.00% time as a percentage of a period (%) 7 No ripple when Vin = Vout / 2 100.00% 2 ⋅ Vin( rms )2 = Vout 2 ⋅ Rin Line Input Current For each branch, somewhere within the sinusoid: 2 ⋅ IL1 Tsw IL1 IL1 Tsw The sum of the two averaged, sinusoidal phases currents gives the total line current: Iin = IL( tot ) Tsw 2 = IL1 Tsw + IL 2 Tsw Assuming a perfect current balacing: 2 ⋅ IL1 Tsw = 2 ⋅ IL 2 Tsw = Iin The peak current in each branch is Iin(t) 8 Ac Component of the Refueling Current The refueling current (output diode(s) current) depends on the mode: 2⋅I in Phase 1 Phase 2 Iin Iin Single phase CCM Single phase CrM Interleaved CrM rms value over Tsw rms value over Tsw rms value over Tsw Iin ⋅ 9 Vin Vout 2 3 ⋅ Iin Vin Vout Iin Vin 2 ⋅ Iin 3 Vout A Reduced Rms Current in the Bulk Capacitor Integration over the sinusoid leads to (resistive load): Single phase CCM PFC Diode(s) rms current (ID(rms)) Single phase CrM or FCCrM* PFC 2 2 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ 3π ⋅Vin( rms ) ⋅Vout ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 3π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout 300 W, Vout=390 V Vin(rms)=90 V ID(rms) = 1.9 A IC(rms) = 1.7 A 2 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ 2 ⎝ η ⎠ ⋅ 3π ⋅Vin( rms ) ⋅ Vout 3 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ 2 ⎝ η ⎠ ⋅ 3 3π ⋅Vin( rms ) ⋅Vout 2 2 Capacitor rms current (IC(rms)) ⎞ ⎟⎟ ⎠ 2 ⎛P ⎞ 32 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 9π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout ID(rms) = 2.2 A IC(rms) = 2.1 A Interleaved CrM or FCCrM* PFC 2 ⎞ ⎟⎟ ⎠ 2 ⎛P ⎞ 16 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 9π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout ⎞ ⎟⎟ ⎠ 2 ID(tot)(rms) = 1.5 A IC(rms) = 1.3 A Interleaving dramatically reduces the rms currents Îreduced losses, lower heating, increased reliability * Frequency Clamped CrM 10 Finally… Interleaved PFC combines: The advantages of CrM operations • No need for low trr diode • High efficiency A reduced input current ripple and a minimized rms current in the bulk capacitor A better distribution of heating More components but “small” ones Well adapted to slim form factor applications such as notebook adapters and LCD TVs Refer to application note AND8355 for more details 11 Agenda Introduction: Basics of interleaving Main benefits NCP1631: a novel controller for interleaved PFC Out-of-phase management The NCP1631 allows the use of smaller inductors Main functions Experimental results and performance General waveforms Efficiency Conclusion 12 NCP1631 Overview Interleaved, 2-phase PFC controller Frequency Clamped Critical conduction Mode (FCCrM) to optimize the efficiency over the load range. Substantial out-of-phase operation in all conditions including start-up, OCP or transient sequences. Feedforward for improved loop compensation Eased design of the downstream converter: pfcOK, dynamic response enhancer, standby management High protection level: Brown-out protection, accurate 1-pin current limitation, in-rush currents detection, separate pin for (programmable) OVP… 13 NCP1631 Overview Interleaved, 2-phase PFC controller Zero voltage detection (branch2) • Fixes the max. on-time • Feed-forward High (5 V) when PFC is ready (steady state) Fixes the max. switching frequency Adjusts the regulation loop bandwidth Latch input: if VLatch > 2.5 V, the controller shutdowns Adjusts the Frequency Foldback characteristic Brown-out detection with a 50-ms blanking delay to meet hold-up time requirements 14 Zero voltage detection (branch1) Over and Under voltage protection (OVP, UVP) One CS pin to sense the total input current for OverCurrent Protection and Inrush detection NCP1631 Typical Application Indicates the downstream converter that the PFC is ready Vin Vout Rbo1 R out1 OVP in R zcd1 FB 1 16 2 15 L2 coil1 L1 Rzcd2 Rout2 Rout3 I Vaux2 Vaux2 I D1 Vout pfcOK Cosc Ac line Rbo2 Cbo2 EMI Filter Cin Cz 14 4 13 5 12 6 11 7 10 8 9 D2 M1 Rt RFF Cp 3 coil2 M2 Vcc LOAD Rz BO OVP in C bulk Rocp R sense I in 1 current sense resistor Synchronization of phases is completely internal 15 Interleaving: Master / Slave Approach… The master branch operates freely The slave follows with a 180° phase shift Main challenge: maintaining the CrM operation (no CCM, no dead-time) L2 < L1 Tsw 2 Tsw 2 Tsw 2 Current mode: inductor unbalance 16 Tsw 2 Tsw 2 Tsw 2 Voltage mode: on-time shift Interleaving: Interactive-Phase Approach… Each phase properly operates in CrM The two branches interact to set the 180° phase shift Main challenge: to keep the proper phase shift On-time perturbation for one phase Tsw 2 Tsw 2 We selected this approach 17 Tsw 2 CrM operation is maintained but a perturbation of the on-time may degrade the 180° phase shift Interleaving Management The oscillator manages the out-of-phase operation It acts as the interleaved clocks generator 5V 4V 18 Current Balancing between the 2 Branches The NCP1631 operates in voltage mode Same on-time and hence switching period in the two branches An imbalance in the inductors: Does not affect the switching period “Only” causes a difference in the power amount conveyed by each branch Iin(1) Iin(2) L1 > L2 L = 2 L1 Phase 1 Phase 2 ton ton The two branches remains synchronized CrM operation is kept (or FCCrM) No alteration of the 180 degree phase shift 19 time Artificial Unbalancing In this test, the 150 µH inductor of branch 1 is replaced by a 300 µH coil !!!! Hence, more current is drawn by branch2 and MOSFET of branch2 is (normally) hotter The following plots show how the PFC stage behaves in these extreme conditions and full load 20 Still Operates in a Robust Manner… 230 Vrms, 0.8 A (PF = 0.980, THD = 11%) 120 Vrms, 0.8 A (PF = 0.997, THD = 6%) Iline (5 A/ div) Iin (2 A/div) Iline (5 A/ div) Iin (5 A/div) DRV2 (10 V/div) DRV2 (10 V/div) DRV2 (10 V/div) DRV2 (10 V/div) Zoom OSC pin voltage (5 V/ div) OSC pin voltage (5 V/ div) Iin (2 A/div) Iin (5 A/div) 21 DRV2 DRV2 DRV2 DRV2 Switching Frequency Variations in CrM Normalized fsw variations within the ac line sinusoid (V in,rms = 90 V, V out = 400 V) Normalized fsw (at the sinusoid top) vs Vin,rms fsw / fsw (90) 1.50 Vin(t) 1.00 0.50 2.50 2.00 1.50 1.00 0.50 80 1.00 2.00 ωt The switching frequency varies versus the input power, the ac line amplitude and within the sinusoid fsw becomes high at light load, leading to large switching losses fsw should be limited 140 170 230 260 fsw becomes large fsw (normalized) vs Pin 20 15 10 5 0 0 50 100 Pin (W) 22 200 Vin,rms (V) 3.00 fsw / fsw(200W) 0.00 0.00 110 150 200 Limiting fsw to Optimize the Efficiency At the top of the sinusoid: fsw = ( Vin,pk ) 2 4 ⋅ L ⋅ Pin,avg ⎛ Vin,pk ⎜⎜ 1 − Vout ⎝ ⎞ ⎟⎟ ⎠ CrM operation requires large inductors to limit the switching losses at light load Can’t we clamp fsw not to over-dimension L? Î Frequency Clamped Critical conduction Mode (FCCrM) 23 Frequency Clamped Critical Conduction Mode At light load, the current cycle is short When shorter than the oscillator period, no new cycle until the oscillator period is elapsed Î dead-times (DCM) On-times are increased to compensate the dead-times Î no PF degradation (ON proprietary) 24 NCP1631 Operation - FCCrM In FCCrM, the switching frequency is clamped: Fixed frequency in light load mode and near the line zero crossing Critical conduction mode (CrM) achieved at full load. FCCrM optimizes the efficiency over the load range. FCCrM reduces the range of frequencies to be filtered (EMI) FCCrM allows the use of smaller inductors No need for large inductances to limit the frequency range! E.g., 150 µH (PQ2620) for a wide mains 300-W application Frequency Foldback reduces the clamp fequency at light load to further improve the efficiency 25 NCP1631 Frequency Foldback The clamp frequency linearly decays when Pin goes below a preset level (PLL) ( Pin )FF PLL is programmed by the pin6 resistor ( P ) in HL = Rpin 6 ⋅ 105 µA 1.66 ≅ Rpin 6 15810 (Pin)HL is the max. power deliverable by the PFC stage Example: FF at 40% load and a 130 kHz nominal frequency 160 Fsw(max)nom 140 Fsw(max) 120 100 IFF 80 60 105 µA 40 20 0 0 20 40 60 80 100 Load (%) Pin 6 pins out a voltage proportional to the power. The IFF current is clamped to 105µA and used to charge and discharge the oscillator capacitor Gradual decay of the clamp frequency No discontinuity in the operation A resistor across the oscillator capacitor sets a minimum clamp frequency (e.g., 20 kHz - see application note AND8407) 26 Light Load Operation Input current (2 A / div) 25% load, 90 V Frequency is reduced at light load Î Heavy DCM operation to reduce the switching losses Vaux1 (10 V/div) Dead-time Vaux2 (10 V/div) Full load, 90 V CrM at heavy load conditions 27 No Load Consumption Conditions Line Voltage (V) Input Power (mW) No Frequency Foldback (pin6 grounded) 115 107 2 separate Vout sensing networks for FB and OVP for a total 185-µA leakage on theVout rail 230 138 Frequency Foldback (RFF = 4.7 kΩ) 115 96 2 separate Vout sensing networks for FB and OVP for a total 185-µA leakage on the Vout rail (*) 230 134 Frequency Foldback (RFF = 4.7 kΩ) 115 38 one Vout sensing network for FB and OVP for a total 48-µA leakage on the Vout rail 230 82 Measured on the 300 W NCP1631 demoboard External Vcc, 3 * 680 kΩ resistors to discharge the X2 capacitors Frequency Foldback improves the efficiency in light load but also in no-load conditions (*) Default demoboard configuration 28 NCP1631 Fault Management Brown-out Undervoltage protection Latch-off condition Die overtemperature Improper Vcc level for operation Too low current sourced by the Rt pin In OFF mode, the major part of the circuit sleeps and consumption is minimized to < 500 µA 29 NCP1631 Over Current Protection 2) ICS current maintains 0 V on CS pin R − ( RCS ⋅ Iin ) + ( ROCP ⋅ ICS ) = 0 ⇒ ICS = CS ⋅ Iin 3) If ICS exceeds 210uA, OCP is triggered ROCP 1) NCP1631 monitors a negative voltage, VCS, proportional to the current drawn by both interleaved branches, Iin. 30 Select RCS freely (optimally) ROCP sets the current limit Minimized losses in RCS NCP1631 Overcurrent Protection When ICS > 210 μA, the OCP switch closes and a current equal to 0.5*(ICS – 210 μA) is injected into the negative input of the VTON processing opamp Î the on-time sharply reduces proportionally to the magnitude of the overcurrent event. Iin (2 A/ div) No discontinuity in the operation, out-ofphase operation is maintained No need for preventing OCP from tripping during a normal transient The current can be accurately limited 31 Vcontrol (1 V/div) Iline (2 A/div) NCP1631 In-rush Current Detection Disables output drive when signal is high (ICS > 14μA) (7% of IILIMIT) When plugged into the mains, the bulk capacitor is abruptly charged to the line voltage and the charge current (in-rush current) is huge. Drive turn-on during this time can damage the MOSFETs. 32 Circuitry to ground the Inrush protection once the circuit begins operation NCP1631 Over Voltage Protection Separate pins for FB and OVP (redundancy) The two functions share the same 2.5 V internal reference for an eased and accurate setting of the OVP level Method 1: One feed-back network for OVP and FB Vout (ovp ) Vout ( nom ) 33 = 1+ Rout 3 Rout 2 Method 2: Two separate feed-back networks Vout (ovp ) Vout ( nom ) = Rovp1 + Rovp 2 Rout 2 ⋅ Rout 1 + Rout 2 Rovp 2 Brown-out Protection with a 50 ms Blanking Time Ac line current (2 A / div) Vbulk (100 V/div) BO pin voltage (1 V/div) For the blanking time, the BO pin voltage is maintained around the BO threshold not to delay the circuit restart when the line has recovered Vin (100 V/div) 20-ms line interruption Mains interruptions shorter than 50 ms are ignored The blanking time helps meet hold-up time requirements The BO pin voltage serves for feedforward 34 NCP1631 PfcOK / REF5V Signal The pfcOK signal can be used to enable/disable the downstream converter. It is high (5 V) when the PFC stage is in normal operation and low otherwise. The pfcOK signal is low: Any time the PFC is off because a major fault is detected (UVLO condition, thermal shutdown,UVP, Brown-out, Latch-off / shutdown, Rt pin open) For the start-up phase of the PFC stage until the nominal bulk voltage is obtained The pfcOK pin can be used as a 5 V power source (5 mA capability) 35 A (simple but easy to use) Excel Spreadsheet (www.onsemi.com) computes the external components 36 Agenda Introduction: Basics of interleaving Main benefits NCP1631: a novel controller for interleaved PFC Out-of-phase management The NCP1631 allows the use of smaller inductors Main functions Experimental results and performance General waveforms Efficiency Conclusion 37 NCP1631 Demoboard Wide mains, 300 W, PFC pre-converter MUR550 NCP1631 38 NCP1631 Demoboard Schematic The circuit is latched off if Vcc exceeds 17.5 V. Could be used for thermal protection D16 1N5406 D5 MUR550 X7 Vaux2 R21 0 DRV2 Vin C5 100nF IN Q2 2N2907 C7 NC Vout X6 IPP50R250 R20 10k S4 + C18 680nF R17 2.2 D4 MUR550 R31 1800k X1 S5 - D18 NC Vaux1 C10 4.7nF Type = Y1 DRV1 R16 0 D14 1N4148 R7 2.2 D20 NC CM1 C16 4.7nF Type = Y1 R121 680k R43 1800k OVPin R46 120k C27 1nF C15 220pF R23 820k R40 27k C20 150nF R36 33k Earth 85-265 Vrms R34 270k D3 LED C29 NC 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 U2 pfcOK C30 100nF Vaux1 Vcc D21 15V C34 10nF R1 1.8k OVPin R12 NC C33 100nF R47 NC C32 100 µF/25V C31 NC D2 NC R2 1k D19 NC D17 1N5406 D6 1N4148 DRV2 D23 NC R24 50m (3W) I in + 300 W, wide mains PFC pre-converter 39 R15 22k R14 22k DRV2 C25 1µF R37 4.7k R122 680k DRV1 N - R6 1k R33 18k D22 NC L 390V Vaux1 Vaux2 C21 NC R25 27k R38 1800k R44 1800k C28 220nF R123 680k R39 1800k R18 560k C22 1nF C2 100 µF/450V DRV1 R42 1800k C6 1µF Type = X2 L4 150µH R41 1800k X4 IPP50R250 R11 10k Q1 2N2907 + R32 1800k 15V - U1 KBU6K D15 1N4148 Input Voltage and Current Full load, 120 Vrms Full load, 230 Vrms Iline (5 A/div) Iline (5 A/div) IL(tot) (2 A /div) IL(tot) (5 A /div) Vin (100 V/div) Vin (200 V/div) As expected, the input current looks like a CCM one At high line, frequency foldback influences the ripple 40 Zoom of the Precedent Plots Full load, 90 Vrms Full load, 230 Vrms IL(tot) (2 A/div) IL(tot) (1 A/div) DRV2 DRV2 DRV1 DRV1 These plots were obtained at the sinusoid top The current swings at twice the frequency of each phase At low and high line, the phase shift is substantially 180° 41 Refueling Sequences Full load, 230 Vrms Full load, 90 Vrms IL(tot) (2 A/div) IL(tot) (1 A/div) VZCD1 VZCD1 VZCD2 VZCD2 CrM at low line with valley switching Fixed frequency operation at high line (frequency clamp) Out-of-phase operation in both cases 42 Efficiency Measurements The output voltage is generally 390 V For a 300 W application, the output current is: 770 mA at full load 154 mA at 20% of the load Both currents are generally measured with the same tool If @ 20% of the load, the input power is 63 W 1-mA error in Iout leads to Iout = 153 mA Î Eff = 100 x 390 x 0.153 / 63 = 94.7 % Iout = 155 mA Î Eff = 100 x 390 x 0.155 / 63 = 95.9 % A 1-mA error causes a 1.2% difference in the efficiency! Measurements @ 10% and 20% of the load need care!!! 43 Efficiency Measurements The efficiency does not only depend on the control mode The inductor, the MOSFETs, diodes, EMI filter… play a role For instance, if we compare the efficiency with a 200 µH PQ2625 inductor to that with a 150 µH PQ2620 one: Efficiency @ 230 V 98.2 98.0 Frequency Foldback limits the difference at light load Efficiency (%) 97.8 97.6 97.4 97.2 97.0 200 µH 96.8 150 µH 96.6 96.4 0 20 40 60 Load (%) 44 80 100 120 Demoboard Efficiency 99.00 98.00 Efficiency (%) 97.00 96.00 95.00 94.00 115V 230V 93.00 92.00 0 20 40 60 80 100 120 Load (%) In the 20% to 100% range, the efficiency remains: > 95.8% at low line > 97.0 % at high line Refer to NCP1631EVB/D at www.onsemi.com for details 45 Tweaking Frequency Foldback … pfcOK / 5V A resistor can be added between the pfcOK (5 V) and frequency foldback pins Doing so, the frequency clamp decays more sharply: fsw(max) Programmable nominal frequency R1 addition R2 ⋅ 105 µA VREGUL Programmable minimum frequency 46 2 R1 FF pin 1 R2 fsw(max) VREGUL = R2 ⋅ 5V R1 + R2 ( R2 ⋅ 5V + ( R1 ⋅ 105 µA ) ) VREGUL R1 + R2 (VREGUL is proportional to the PFC power) 99.00 99.00 98.00 98.00 97.00 97.00 96.00 95% 95.00 R1 addition 94.00 E fficiency (% ) E fficien cy (% ) Efficiency Improvement 96.00 95% 95.00 94.00 1% 115V 93.00 1% 115V 93.00 230V 92.00 230V 92.00 0 10 20 30 40 50 Load (%) 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 Load (%) A resistor on the oscillator pin sets the minimum frequency With R1, the PFC stage operates at the minimum frequency (20 kHz) at 10% and 20% of the load The tweak further improves the light load efficiency 47 100 Agenda Introduction: Basics of interleaving Main benefits NCP1631: a novel controller for interleaved PFC Out-of-phase management The NCP1631 allows the use of smaller inductors Main functions Experimental results and performance General waveforms Efficiency Conclusion 48 Conclusion Interleaved PFC allows use of smaller components, improves thermal performance, increases the CrM power range and reduces current ripple. The NCP1631 provides a single IC solution which incorporates all the features necessary for building a robust and compact 2-phase interleaved PFC stage with minimal external components. Its FCCrM and frequency foldback allows an efficient operation over the load range with small inductors 49 For More Information View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com View reference designs, design notes, and other material supporting the design of highly efficient power supplies at www.onsemi.com/powersupplies 50