AND8207/D 19 V/6.4 A Universal Input AC−DC Adaptor with PFC Using NCP1603 Prepared by: Kahou Wong ON Semiconductor http://onsemi.com APPLICATION NOTE INTRODUCTION two−stage PFC−PWM power conversion. Suiting for low−power AC−DC application, the PFC section is Discontinuous Conduction Mode (DCM) and Critical Mode (CRM) boost topology. This PFC operating mode is a special case of Peak−Current Mode PFC that needs fewer external components since the average−current circuit is saved. It is suitable for space−saving in the combo controller implementation. On the other hand, the PWM section is a fixed−frequency PWM current−mode CCM or DCM flyback topology with skipping cycle capability. The features (including skipping cycle operation, the integrated lossless high−voltage startup and the PFC section shutdown during standby) present excellent no−load standby power consumption. NCP1603 is an ideal controller for application that needs extremely low standby power consumption and PFC feature. This application note presents an AC−DC converter example circuit in Figure 1 using NCP1603 with the design steps and measurement. The measurement shows that the 120 W converter has a greater than 0.93 power factor under the universal input (90 to 260 Vac), less than 200 mW no load standby power consumption, and greater than 81% efficiency. NCP1603 is a co−package of NCP1230 and NCP1601 so that the example circuit can be a reference circuit for NCP1230 and NCP1601. The NCP1603 is first ON Semiconductor PFC/PWM (or so called PFC/DCDC because the second stage is only a DC−DC conversion) combo controller featuring integrated high−voltage startup and excellent low standby no load power consumption. The NCP1603 solution is the standard Table 1. Features of Power Supply Using NCP1603 or NCP1230/NCP1601 Topology PFC Stage PWM Stage Features CRM / DCM boost CCM / DCM flyback • CRM/DCM PFC is preferable for low−power application. CRM is a special case of Peak Current Mode PFC that needs very few external components. • Hold−up time is maximized by a step−up voltage in the PFC. • Isolated flyback topology is with minimum circuit component for low−power application. Standby condition Power off Skipping cycle • It offers excellent low standby power consumption. Fault condition Power off Double hiccup restart • It minimizes power dissipation in fault and allows auto−recovery ability when fault is cleared. Latch protection activated Power off Latched off • VCC stays above typical 5.6 V and PWM drive output remains off until circuit reset. • Reset needs the AC input unplugged. non−fully−power−factor−corrected current in this moment) and the OCP level is indirectly related to the zero current threshold (ZCD) of the PFC stage. Higher ZCD level will reduce the efficiency by non−zero−current switching and also make the PFC distortion higher in the high−line condition. The maximum input power the NCP1603 is experimentally found at around 120 W for universal input range. The major barrier for higher power is that the Go−To−Standby (GTS) feature requires higher overcurrent (OCP) level in PFC (because the PFC needed to startup at low−line full−load condition that the circuit is drawing high © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 1 1 Publication Order Number: AND8207/D F1 2A L1 D1 − D4 1N5406 x 4 180uH / 10A C1 0.1uF D5 C4 − C5 MUR460 100uF / 450V x 2 Q1 SPP11N60C3 R22 150k C16 100pF R20 25 D13 1N5359B Osc R8* 0 http://onsemi.com 2 Vaux HV FB2 NC CS2 Vcc2 Gnd1 CS1 Out1 Vctrl Vcc1 FB1 R7 1k R16 1k C17 1nF C8 0.047uF R21* 15k R14* 15k Gnd2 Out2 IC4 TL431A Q2 SPP06N80C3 R11 − R12 0.5 /1W x 2 C18 33pF D10 MRA4005 C6 470uF Ramp D9 MPZ4745A C15 1nF C14 0.82uF IC1 NCP1603 C13 2200pF C2 0.22uF C19 0.82uF Figure 1. Application Schematic of the Example Circuit C7 1nF / 1000V R18 2.37k Flyback transformer T2 TDK SRW42EC−U16H014 Primary inductance = 420uH +/− 10% Leakage inductance = 6.5uH max Turn ratio = 5.58 : 1 : 0.79 IC3 SFH615AA007 R15 4.99k C21 0.1uF C12 2200uF R10 332 C20 0.82uF R9 10 IC2 SFH615AA007 C22 100pF /100V R19 750 / 0.5W D11 − D12 MBR16100 x 2 T2 C9 − C11 L2 2200uF x 3 10uH / 10A R17 15.8k *Note: Circuit is not synchronized when R14 and R21 are removed. Circuit is synchronization when R14 and R21 are connected. R8 is a bare wire, the PFC section is disabled when R8 is removed. D6 MUR1100E D8 MURS160 Output 19V / 6.4A (Vcc = 15V) D7 1.5KE250A R23 13k R13 47k / 5W R5 60.4k R4 910k R3 910k R6 10 R1 − R2 0.05 / 1W x 2 C3 1uF AC Input 90 to 260 Vac T1 P3717−A AND8207/D R24 4.3k AND8207/D DESIGN STEPS around 100 kHz so that it matches the PWM section operating frequency in the synchronization case. Referring to Figure 70 in the NCP1603 datasheet when a 100 pF capacitor is connected to osc pin (Pin 5), the PFC section maximum frequency is clamped at 107 kHz that corresponds the DCM operation switching period as 9.33 ms. Step 1. Define the Specification Input Output Features 90 to 260 Vac, 50 Hz 19 Vdc, 6.4 A, isolated Synchronization option Output overvoltage protection latch f + 107 kHz T + 1 + 9.33 ms f The maximum overvoltage protection threshold of the PFC section is 225 mA that corresponds to 225 mA x 1.88 MW + 5 V = 428 V when feedback resistor RFB is 1.88 MW (910 kW + 910 kW + 60 kW) and a 5 V maximum offset of the feedback pin of the PFC section. A 450 V output capacitor can be used here. On the other hand, the output voltage has to be higher than the maximum of input voltage in boost topology to make the boost converter work properly. Therefore, the nominal PFC−stage output voltage Vout is set at 380 Vdc. Note that there is a roughly 4 V offset when feedback current is 200 mA. Step 2. Assuming Efficiency and Loss The converter consists of two power stages. The overall efficiency is a cascaded efficiency of the two stages. Hence, the target overall efficiency cannot be too aggressive. When both stages are with 90% efficiency, the overall efficiency h is only 81%. It means that 150.1 W input power Pin is needed to deliver 19 V/6.4 A at 81% efficiency. Referring to Figure 2, only 135 W power is needed from the PFC stage but the PFC stage is designed at 150 W to reserve some design margin. Vout u Vin(max) + Ǹ2 · 260 + 367.7 V Vout + 200 mA P 19 V 6.4 A + 150.1 W Pin + out h + 81% 1.88 MW ) 4 V + 380 V In order to demonstrate the PFC/PWM synchronization option, the DCM frequency of the PFC is chosen to be AC Line 150.1 W 380 V 135.1 W 150 W PFC Boost 90% efficiency 120 W PWM flyback 90% efficiency 15 W loss 19 V / 6.4 A 121.6 W 13.5 W loss Figure 2. Power Structure Step 3. Biasing the Controller voltage in Figure 3. In order to have extremely low standby power consumption, the VCC must be supplied by an external biasing circuit that costs only one additional output of the flyback in the PWM stage. Thanks to the high−voltage startup pin (Pin 16) of the NCP1603, the initial IC supply voltage VCC can be obtained by connecting this pin to the bulk capacitor AC Input PFC Boost EMI Filter and Diode Bridge Output 19 V / 6.4 A HV VCC 15 V NCP1603 Figure 3. VCC Biasing Scheme http://onsemi.com 3 AND8207/D Cramp + 1000 pF Typical total current consumption of the whole NCP1603 controller (including the PWM and PFC sections and the current to switch a pair of MOSFETs) are 10 mA. The supply voltage is normally set as 15 V so that it reserves some margin for the startup threshold of the PFC section (typical 10.5 V) to avoid insufficient biasing voltage. With this value of Cramp, the Vcontrol in high line and low line conditions are 0.11 V and 0.89 V respectively. Vcontrol + 2LIchPin CrampVac2 + 2 · 180 Step 4. PFC Section Design The PFC Section of NCP1603 is NCP1601. So, the design is a standard PFC NCP1601 circuit design as follows. Vcontrol + Step 4a. Calculate the Current Stress The worst case happens when input is 90 Vac. The input RMS current Iac is 2.22 Aac if the power factor is perfect. The suffix ac represents it is RMS value. This current stress is mainly on the front−ended rectifier. 10−6 · 100 10−6 · 167 + 0.09 V 10−9 · 2602 2LIchPin CrampVac2 + 2 · 180 10−6 · 100 10−6 · 167 + 0.74 V 10−9 · 902 Step 4d. Adjust the Output Voltage When Vcontrol is estimated, the output voltage can be estimated more accurately by the 96% regulation block. The calculation here takes a 4 V offset at around the feedback current range of IFB = 200 mA. The output voltage in the high line and low line conditions are 378.67 V and 368.86 V. P 150 Pin + out h + 90% + 167 W P Iac + in + 167 W + 1.85 Aac Vac 90 V The instantaneous maximum current stress in the PFC stage will be 6.29 A in critical mode. Vout + (Vout(nom) * 4 V) · (1 * 0.04 · Vcontrol) ) 4 V Ipk + 2 Ǹ2 Iac + 5.24 A + (380 * 4)(1 * 0.04 · 0.09) ) 4 + 378.67 V Vout + (Vout(nom) * 4 V) · (1 * 0.04 · Vcontrol) ) 4 V This current stress affects the component selections on the current sense resistor, MOSFET, diode and inductor. + (380 * 4)(1 * 0.04 · 0.74) ) 4 + 368.86 V Step 4b. Inductor Design Step 4e. Check the Switching Period to Ensure CRM at the Sinusoidal Peak. The minimum CRM inductance L(CRM) at low line is obtained as follows: The switching period in high line and low line conditions are: V * Vin Vin 1 L(CRM) + out Ipk f Vout + t1 ) t2 + V 380 * Ǹ2 · 90 Ǹ2 · 90 1 + 151 mH 380 6.29 107 103 + It is the minimum value inductor value to keep the circuit in CRM. The inductor L is therefore set to be 180 mH. The switching frequency is 75 kHz at the sinusoidal peak and it is in CRM. t1 ) t2 + V V * Vin Vin 1 freq + out Ipk L Vout + 380 * Ǹ2 · 90 Ǹ2 · 90 1 380 5.24 180 10−6 Step 4f. Current Sense Resistors Design Maximum power can be obtained when Vcontrol = 1 V. Worst case is at low line 90 Vac. There is a minimum sense resistor limit of RS(ZCD) = 1 kW. The higher the RS value, the higher the current sense resistor needed which dissipates more power. Therefore, RS is set at 1 kW. Pin · 2LIch Vac2 10−6 · 100 10−9 · 0.74 368.86 Ǹ 368.86 * 2 · 90 100 10−6 When the circuit operates in CRM at the peak, the maximum current is limited to twice of the average. Step 4c. Ramp Capacitor Design + 167 · 2 · 180 902 CrampVcontrol Vout Ich * V out in + 11.31 ms u 9.33 ms + 88 kHz t 107 kHz Cramp u 10−9 · 0.09 378.67 Ǹ 378.67 * 2 · 260 100 10−6 + 30.64 ms u 9.33 ms L + 180 mH + CrampVcontrol Vout Ich * V out in RS + 1 kW 10−6 + 742 pF Then, the maximum inductor current from the previous step is 5.24 A in low line is with RCS = 37.6 mW. Hence, the Cramp is set to be 1 nF. http://onsemi.com 4 AND8207/D RCS + + RS · IS(OCP) * VS(OCP) Because the transformer turn ratio is variable in the design of a flyback circuit, the design is an iteration process to balance a set of parameters to make the parameters work nicely with each other. The following are the most concerned parameters. • Maximum duty ratio − It is a parameter limited by the switching controller and cannot go further if the switching controller is not replaced. It is (75% min, 85% max) for NCP1230 (the PWM section of the NCP1603). This is the first constraint. • Minimum duty ratio − The NCP1230 enters skipping mode when VFB2 goes below 0.75 V (typical). It corresponds to duty goes below 20% (typical) (VFB2 = 3 V for 80%). The flyback has minimum duty ratio when the PFC is on and the circuit is delivering full power. It is undesirable to have skipping operation in full load due to potential low−frequency audible noise. • Maximum MOSFET voltage stress − It includes the reflected voltage and the possible instantaneous peak voltage due to the leakage inductance of the transformer. Common available MOSFET voltage in market is up to 800 V. This is another constraint. • Maximum output diode blocking voltage − The blocking voltage increases with the forward voltage drop. This conduction loss is significant because the output current in this design is 6.4 A. • Maximum input power for a realistic efficiency (or output power) − It is done by selecting the maximum peak current, inductance (to affect the operating mode in CCM or DCM). To keep this application note short enough and readable, the iteration process is not shown. According to the calculation result, the following parameters are finalized: Output voltage = 19 V Output current = 6.4 A Output diode volt drop = 1 V Transformer turn ratio (n1/n2) = 5.58 Maximum peak switch current = 4 A Switching frequency = 100 kHz IL(OCP) 1 kW · 200 mA * 3.2 mV + 31.3 mW 5.24 A Then, RCS is set at parallel of two 50 mW resistors to make IL(OCP) > 6.29 A. It gives the maximum current limit IL(OCP) is 5.24 A. RCS + 25 mW IL(OCP) + + RS · IS(OCP) RCS 1 kW · 200 mA * 3.2 mV + 7.87 A 25 mW Step 4g. Bulk Capacitor Design As a rule of thumb, output capacitance is generally set at 1 mF/W. Hence, without loss of generality the 150 W application needs 150 mF. Another consideration is the ripple current in the bulk capacitor. On the other hand, in a NCP1601 PFC circuit the instantaneous output voltage affects the instantaneous control voltage Vcontrol. If the output voltage ripple is too high, it will make a large ripple on control voltage and the power factor can be dramatically reduced for highly dynamic control voltage. Hence, it is implemented by two 100 mF, 450 V capacitors to increase the ripple current capability. Cbulk + 200 mF Step 4h. Fine Tuning Capacitor on Vcontrol Pin The unity power factor in the NCP1601/NCP1603 PFC circuit greatly relies on how steady the control voltage in the Vcontrol pin (Pin 10). A large external capacitor on this pin can help to reduce the noise and dynamics of this voltage and give a decent power factor. However, if the capacitor is too large, it will reduce the dynamic response or startup transient of the circuit. Step 5. PWM Section Design The PFC Section of NCP1603 is NCP1230 flyback that is fixed−frequency PWM and generic approach can be used. Step 5a. Fixed−Frequency PWM Flyback Calculation Transformer primary inductance = 420 mH Duty ratio (at Vin = 420 V, Continuous mode lossless) = 21% Duty ratio (at Vin = 100 V, Continuous mode lossless) = 53% In order to have extremely low standby power consumption, the PWM flyback always operates. The flyback is needed to be capable of the cases when the PFC boost is operating or not. Hence, the input voltage of the PWM flyback circuit must be wide input range. Some design margin is taken here. The high and low line voltages are assumed to be 100 V and 420 V respectively. It is noted that the minimum duty ratio in this design is a little bit low. Customers are recommended to design it higher to keep skip condition (duty < 20%) away from the normal operation. Vin(L) + 100 V Vin(H) + 420 V http://onsemi.com 5 AND8207/D when Vaux is high and it reduces the variation of VFB2 between the PFC−on and PFC−off. Particularly for the NCP1230 (NCP1603 PWM section) if the maximum current limit is set at 4 A, it refers a pair of resistors R11−R12 (or RCS) = 0.25 W. ID(max) + 1 V + 1 V + 4 A 0.25 W RCS Vaux The compensation ramp (that relates to stability and maximum duty) is set by R10 (or RS). Smaller value of RS makes a fewer compensation ramp for the modulation (less stable) and allows more maximum duty. Typical starting point of RS for design is from 1 kW or 2 kW. When stability problem is encountered, the value of RS is needed to be increased or the voltage−loop feedback gain is needed to be reduced. VFB2 3 VCS2 Out 2 High duty when PFC is off. Step 6. VCC Capacitor The maximum allowable time to recognize a fault is 125 ms and the VCC voltage is supposed to be still higher than the minimum operating values and hence the capacitor should be larger than 56 mF. Low duty when PFC is on. Figure 4. Transition when PFC turns on. Step 9. PCB Layout Layout is a big issue for the PFC/PWM combo controller because the shortest distances between the NCP1603 controller and the PFC MOSFET, PWM MOSFET and opto coupler are wanted. It is also noticed that the controller should be located outside the high current loop to prevent the strong magnetic field interfere the controller operation. The layout stretch of the example circuit is shown in Figure 5. C + Idt u 2.2 mA · 125 ms + 56 mF dV 12.6 V * 7.7 V Another concern on VCC capacitor selection is to make sure that VCC voltage is always above the UVLO start threshold (10.5 V typical) of the PFC section in standby where the ripple is higher. Step 7. Decoupling Capacitors Noise is always generated in the switching mode power supply. Some cautions are taken to handle the noise on some pins regarding the NCP1603 as following. The values of the decoupling capacitors are all up to the noise level in the layout. FB1 pin (Pin 9): Noise on this pin will potentially trigger the PFC OVP and the PFC operation can be ruined completely. CS2 pin (Pin 3): Noise on this pin will trigger the latch protection that is needed to be reset by unplugging the main (or making VCC goes below 4 V). FB2 pin (Pin 2): Noise on this pin will affect the PWM section duty ratio generation. Vaux or VCC1 pins (Pin 1 or 8): The internal Vaux MOSFET is with 11.7 W typical resistance. It is high enough to pollute the VCC1 voltage through the high−frequency switching pulses or noise. A decoupled capacitor is needed to keep VCC1 voltage clean. High Current Loop High Current Loop Gnd S D G PFC Boost MOSFET CS2 NCP1603 CS1 S D G PWM Flyback MOSFET Figure 5. Layout Stretch MEASUREMENT Part I. Standby loss The circuit offers excellent no load standby performance. The power consumption of the 150 W circuit is less than 200 mW. When input is high line (260 Vac) and the output is 508 mW (19.07 V * 26.66 mA), the input power is 840 mW. Step 8. PFC on/off Toggling The NCP1603 circuit turns the PFC section on and off depending on the load conditions by the changing of PWM section feedback voltage VFB2. There may be a potential on/off toggling issue when the load condition is at the on/off boundary. A resistor R22 is recommended to be connected between Vaux pin (Pin 1) and CS2 pin (Pin 3) to solve the toggling issue. This resistor adds an offset voltage to CS2 pin http://onsemi.com 6 Input Input power 260 Vac 180 mW 230 Vac 150 mW 220 Vac 145 mW 200 Vac 130 mW 160 Vac 110 mW AND8207/D Part II. Operating and Not Synchronized R14 and R21 are removed, the circuit is not synchronized. In Figures 6 to 9, the upper trace is the input current with 2 A/div. The center trace is the PFC output voltage with 100 V/div. And the lower trace is the rectified input voltage with 100 V/div. The PFC section of NCP1603 is in DCM sometimes. DCM operation can be synchronized with the PWM section or independently operates. This part shows the operating performance when the circuit is not synchronized. When Input Output Efficiency PF / THD 90 Vac 145.4 W 18.91 V 6.4 A 83.2% 0.998 / 5.2% 110 Vac 143.7 W 18.91 V 6.4 A 84.2% 0.997 / 5.2% 120 Vac 143.2 W 18.91 V 6.4 A 84.5% 0.996 / 6.3% 180 Vac 139.5 W 18.91 V 6.4 A 86.8% 0.993 / 6.3% 220 Vac 137.6 W 18.91 V 6.4 A 88.0% 0.982 / 13.3% 230 Vac 137.1 W 18.91 V 6.4 A 88.3% 0.973 / 17.9% 260 Vac 135.9 W 18.91 V 6.4 A 89.1% 0.934 / 34.2% Figure 6. 90 Vac Input Voltage and Not Synchronized Figure 7. 110 Vac Input Voltage and Not Synchronized Figure 8. 220 Vac Input Voltage and Not Synchronized Figure 9. 260 Vac Input Voltage and Not Synchronized http://onsemi.com 7 AND8207/D OSC NCP1603 Part III. Operating and Synchronized This part shows the circuit operating with the PFC and PWM sections are synchronized together. It is done by adding two 15 kW resistors (R14 and R21) as in Figure 10. The 100 pF capacitor here added as a decoupling filter for smoothing the synchronization signal to osc pin (Pin 5). The capacitor is essential because PFC performance can be degraded by noisy synchronization signal. The value of 100 pF is selected because too large value will result in big RC constant so that the osc pin voltage cannot reach 3.5 V and 5 V for synchronization. The result shows that the synchronization cannot offer a better efficiency in this circuit. Out2 R14 15k R15 15k C16 100 pF Figure 10. Synchronization Configuration Input Output Efficiency PF / THD 90 Vac 146.0 W 18.91 V 6.4 A 82.9% 0.998 / 4.5% 110 Vac 145.2 W 18.91 V 6.4 A 83.3% 0.997 / 5.3% 120 Vac 144.3 W 18.91 V 6.4 A 83.9% 0.996 / 6.6% 180 Vac 140.8 W 18.91 V 6.4 A 86.0% 0.993 / 5.8% 220 Vac 138.9 W 18.91 V 6.4 A 87.1% 0.982 / 11.4% 230 Vac 138.4 W 18.91 V 6.4 A 87.4% 0.976 / 15.3% 260 Vac 137.4 W 18.91 V 6.4 A 88.1% 0.939 / 31.3% Figure 11. 90 Vac Input Voltage and Synchronized Figure 12. 110 Vac Input Voltage and Synchronized Figure 13. 220 Vac Input Voltage and Synchronized Figure 14. 260 Vac Input Voltage and Synchronized http://onsemi.com 8 AND8207/D Part IV. PFC On/Off Transition is on, the flyback input voltage goes higher again. Hence, the circuit may oscillate at the PFC−on/off boundary. When resistor R22 is removed, the circuit goes toggling. In Figures 15 to 17, the upper trace is the output current with 1 A/div and the lower trace is the PFC output voltage with 100 V/div. In these figures, the input voltage is 110 Vac. The PFC stage is toggling when output current is 2.8 A in Figure 15. A resistor R22 (150 kW) is added between Vaux and CS2 pin. The PFC stage turns on when output is 3 A in Figure 16 and it turns off when output is 1.6 A in Figure 17. PFC on/off toggling is an inherent feature of NCP1230 or NCP1603 circuit. The abrupt change of the PWM stage duty ratio may cause the PFC toggling on and off in boundary condition. In a PFC−on/off boundary condition, flyback circuit with higher input voltage needs lower duty ratio. Lower duty ratio means standby condition. It wants PFC−off. After PFC is off, the flyback input voltage goes lower and duty ratio goes higher. Higher duty ratio means normal operation condition. It wants the PFC−on. After PFC Figure 15. PFC Toggling in Boundary Condition when R22 Removed Figure 16. PFC Toggling Disappeared Figure 17. PFC Turns Off at Load Current CONCLUSION layout comparing to CCM−PFC. The DC−DC section is implemented in flyback that also needs the minimum external components. It makes the NCP1603 (or NCP1601 with NCP1230) application circuit is simple and minimal for low−power AC−DC application with PFC requirement. An example circuit using NCP1603 is presented. The design steps and measurement are covered. It is noted that the NCP1603 can perform a decent power factor correction, excellent standby performance and good efficiency at 120 W, 19 V, 6.4 A. The PFC boost section is implemented in CRM and DCM. It needs very few external component for easier design and http://onsemi.com 9 AND8207/D Appendix I. Bill of Material of the NCP1603 19 V/6.4 A Example Circuit Designator F1 L1 L2 T1 T2 Q1 Q2 IC1 IC2 − IC3 IC4 D1 − D4 D5 D6 D7 D8 D9 D10 D11 − D12 D13 D14 R1 − R2 R3 − R4 R5 R6 R7 R8 R9 R10 R11 − R12 R13 R14, R21 R15 R16 R17 R18 R19 R20 R22 R23 R24 C1 C2 C3 C4 − C5 C6 C7 C8 C9 − C12 C13 C14, C19 − C20 C15, C17 C16 C18 C21 C22 Heatsink Heatsink Insulation AC Connector DC Connector Qty 1 1 1 1 1 1 1 1 2 1 4 1 1 1 1 1 1 2 1 1 2 2 1 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 4 1 3 2 1 1 1 1 3 4 1 1 Part No 0465 02 PCV−2−184−10 PCV−2−103−10 P3717−A SRW42EC−U16H014 SPP11N60C3 SPP06N80C3 NCP1603D100 SFH615AA−X007 TL431AID 1N5406 MUR460 MUR1100E 1.5KE250A MURS160 MZP4745A MRA4005T3 MBR16100CT 1N5359B 1N5923B WSL2512R0500FEA CCF55910KFKE36 CRCW12066042F CRCW120610R0F CCF551K00FKE36 N/A CCF5510R0FKE36 CRCW12063320F WSL2512R5000FEA HPS523−47k−5% CRCW12061502F CRCW12064991F CRCW12061001F CRCW12061582F CRCW12062371F CCF55750RFKE36 CRCW120624R9F CRCW12061503F CRCW12064321F CRCW12061302F LE104 RE224 LE105 450AXW100M18X40 025YXG−470M00−10X16 ERO610RJ4100M 630MMB473K 025YXG2200M12.5X30 VJ1206Y222KXXA VJ1210Y824KXXA VJ1206Y102KXXA VJ1206A101KXXA VJ1206A330KXXA VJ1210Y104KXXA VJ1206Y101KXBA 78065 4672 770W−X2/10 26−60−4030 or 009652038 Description 250 V 2 A Delay Surface Mount Fuses Inductor 10 A 180 mH Inductor 10 A 10 mH CM 25 mH, DM 1 mH filter, 3 A rms Custom Transformer 420 mH, 5 A, 5.58:1:0.79 11 A 600 V N−MOSFET 6 A 800 V N−MOSFET PFC/PWM Combo Controller Optocoupler 2.5 V 1% Voltage Reference, SO−8 3 A 600 V Diode 4 A 600 V Diode 1 A 1000 V Diode 250 V TVS Zener Diode 1 A 600 V Diode 16 V @ 15.5 mA Zener Diode 1 A 600 V Diode 16 A 100 V Diode 24 V @ 1 mA Zener Diode 8.2 V @ 49.2 mA Zener Diode 0.05 W 1W SMD 1% 910k W, axial 0.25W 1% 60.4k W, SMD 1206 1% 10 W, SMD 1206 10% 1k W, axial 0.25W 1% bare wire, remove for disable PFC section 10 W, axial 0.25W 1% 332 W, SMD 1206 0.5 W 1W SMD 1% 47k W, 4W axial 5% 15k W, SMD 1206 4.99k W, SMD 1206 1k W, SMD 1206 15.8k W, SMD 1206 2.37k W, SMD 1206 750 W, axial 0.5W 25 W, SMD 1206 150k W, SMD 1206 4.32k W, SMD 1206 13k W, SMD 1206 0.1 mF 275 Vac Film Capacitor 0.22 mF 275 Vac Film Capacitor 1 mF 275 Vac Film Capacitor 100 mF 450 V Aluminium Cap 470 mF 25 V Aluminium Cap 20% 1 nF 5 mm pitch Y2 cap 0.047 mF 630 V Film Capacitor 10% 2200 mF 25 V Aluminium Cap 2200 pF 25 V Ceramic Cap 0.82 mF 25 V Ceramic Cap 1 nF 25 V Ceramic Cap 100 pF 25 V Ceramic Cap 33 pF 25 V Ceramic Cap 0.1 mF 25 V Ceramic Cap 100 pF 100 V Ceramic Cap Indian Chief 1.18” unfinished cut TO−220 mica insultion IEC60320 C8 Connector 3−terminal 3.96 mm distance male header http://onsemi.com 10 Manufacturer Littelfuse Coilcraft Coilcraft Coilcraft TDK Infineon Infineon ON Semiconductor Vishay ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor Vishay Vishay Vishay Vishay Vishay N/A Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Okaya Okaya Okaya Rubycon Rubycon Evox Rifa Rubycon Rubycon Vishay Vishay Vishay Vishay Vishay Vishay Vishay Aavid Keystone Qualtek Molex AND8207/D Appendix II. The PCB Layout Figure 18. Top Layer Layout Figure 19. Bottom Layer Layout http://onsemi.com 11 AND8207/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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