DTA144TT1 Preferred Device Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SC−59 package which is designed for low power surface mount applications. http://onsemi.com PNP SILICON BIAS RESISTOR TRANSISTOR PIN 3 COLLECTOR (OUTPUT) Features • • • • • • • Simplifies Circuit Design Reduces Board Space Reduces Component Count Moisture Sensitivity Level: 1 ESD Rating: Human Body Model: Class 1 Machine Model: Class B The SC−59 package can be soldered using wave or reflow. The modified gull−winged leads absorb thermal stress during soldering eliminating the possibility of damage to the die. Pb−Free Package is Available R1 PIN 2 EMITTER (GROUND) 3 1 MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc IC 100 mAdc Collector Current R2 PIN 1 BASE (INPUT) 2 MARKING DIAGRAM THERMAL CHARACTERISTICS Characteristic Total Device Dissipation TA = 25°C Derate above 25°C Symbol Max Unit PD 230 (Note 1) 338 (Note 2) 1.8 (Note 1) 2.7 (Note 2) mW RqJA 540 (Note 1) 370 (Note 2) °C/W Thermal Resistance, Junction-to-Lead RqJL 264 (Note 1) 287 (Note 2) °C/W TJ, Tstg −55 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−4 @ Minimum Pad 2. FR−4 @ 1.0 x 1.0 inch Pad © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 3 6T M G G 1 °C/W Thermal Resistance, Junction-to-Ambient Junction and Storage Temperature Range SC−59 CASE 318D PLASTIC 1 6T = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Publication Order Number: DTA144TT1/D DTA144TT1 DEVICE MARKING AND RESISTOR VALUES Marking R1 (K) R2 (K) Package Shipping† DTA144TT1 6T 47 ∞ SC−59 3000/Tape & Reel DTA144TT1G 6T 47 ∞ SC−59 (Pb−Free) 3000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Min Typ Max Unit Collector−Base Cutoff Current (VCB = 50 V, IE = 0) ICBO − − 100 nAdc Collector−Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO − − 500 nAdc Emitter−Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO − − 0.2 mAdc Collector−Base Breakdown Voltage (IC = 10 mA, IE = 0) V(BR)CBO 50 − − Vdc Collector−Emitter Breakdown Voltage (Note 3) (IC = 2.0 mA, IB = 0) V(BR)CEO 50 − − Vdc hFE 160 350 − VCE(sat) − − 0.25 Vdc Output Voltage (on) (VCC = 5.0 V, VB = 3.5 V, RL = 1.0 kW) VOL − − 0.2 Vdc Output Voltage (off) (VCC = 5.0 V, VB = 0.25 V, RL = 1.0 kW) VOH 4.9 − − Vdc R1 32.9 47 61.1 kW Characteristic OFF CHARACTERISTICS ON CHARACTERISTICS (Note 3) DC Current Gain (VCE = 10 V, IC = 5.0 mA) Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 1.0 mA) Input Resistor 3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0% PD, POWER DISSIPATION (mW) 350 300 250 200 150 100 RqJA= 370°C/W 50 0 −50 0 50 100 TA, AMBIENT TEMPERATURE (5°C) Figure 1. Derating Curve http://onsemi.com 2 150 DTA144TT1 PACKAGE DIMENSIONS SC−59 CASE 318D−04 ISSUE G D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3 HE 2 E 1 DIM A A1 b c D E e L HE b e C A MIN 1.00 0.01 0.35 0.09 2.70 1.30 1.70 0.20 2.50 MILLIMETERS NOM MAX 1.15 1.30 0.06 0.10 0.43 0.50 0.14 0.18 2.90 3.10 1.50 1.70 1.90 2.10 0.40 0.60 2.80 3.00 MIN 0.039 0.001 0.014 0.003 0.106 0.051 0.067 0.008 0.099 INCHES NOM 0.045 0.002 0.017 0.005 0.114 0.059 0.075 0.016 0.110 MAX 0.051 0.004 0.020 0.007 0.122 0.067 0.083 0.024 0.118 L A1 SOLDERING FOOTPRINT* 0.95 0.037 0.95 0.037 2.4 0.094 1.0 0.039 0.8 0.031 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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