IDT 89HPES4T4

89HPES4T4
Data Sheet
4-Lane 4-Port
PCI Express® Switch
Device Overview
◆
The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
◆
Features
◆
◆
◆
High Performance PCI Express Switch
– Four 2.5 Gbps PCI Express lanes
– Four switch ports
– x1 Upstream port
– Three x1 Downstream ports
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates four 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC motherboards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCIPM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
4-Port Switch Core / 4 PCI Express Lanes
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Data Link Layer
Mux / Demux
Mux / Demux
Mux / Demux
Mux / Demux
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
(Port 4)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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© 2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
September 7, 2007
Advance Information
Advance Information*
®
IDT 89HPES4T4 Data Sheet
◆
◆
5 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Each pin has a selectable alternate function
Packaged in a 13mm x 13mm 144-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low
latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 1.1.
The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES4T4 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.
Processor
Advance Information
Processor
Memory
Memory
Memory
Memory
North
Bridge
South
Bridge
x1
PES4T4
x1
GE
LOM
x1
GE
LOM
x1
1394
Figure 2 I/O Expansion Application
SMBus Interface
The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O
expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.
Hot-Plug Interface
The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
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September 7, 2007
IDT 89HPES4T4 Data Sheet
General Purpose Input/Output
The PES4T4 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alternate functions may be enabled via software or serial configuration EEPROM.
Pin Description
Signal
Type
Name/Description
PE0RP[0]
PE0RN[0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0.
PE0TP[0]
PE0TN[0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0.
PE2RP[0]
PE2RN[0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PE2TP[0]
PE2TN[0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2.
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3.
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pair for port 4.
PEREFCLKP
PEREFCLKN
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes.
Advance Information
The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Table 1 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
Table 2 SMBus Interface Pins
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IDT 89HPES4T4 Data Sheet
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
Advance Information
Signal
Table 3 General Purpose I/O Pins
Signal
Type
Name/Description
APWRDISN
I
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
CCLKDS
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES4T4 and initiates a PCI Express fundamental reset.
Table 4 System Pins (Part 1 of 2)
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IDT 89HPES4T4 Data Sheet
Signal
Type
Name/Description
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES4T4 executes the reset procedure and remains in a reset
state with the Master SMBus active. This allows software to read and write
registers internal to the device before normal device operation begins. The
device exits the reset state when the RSTHALT bit is cleared in the
PA_SWCTL register by the SMBus master.
SWMODE[2:0]
I
Switch Mode. These configuration pins determine the PES4T4 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
WAKEN
I/O
Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through WAKEDIR bit setting in
the WAKEUPCNTL register.
Signal
Type
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Advance Information
Table 4 System Pins (Part 2 of 2)
Name/Description
Table 5 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 6 Power and Ground Pins
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IDT 89HPES4T4 Data Sheet
Pin Characteristics
Note: Some input pads of the PES4T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
PCI Express Interface
SMBus
Type
Buffer
I/O
Type
PE0RN[0]
I
CML
Serial Link
PE0RP[0]
I
PE0TN[0]
O
PE0TP[0]
O
PE2RN[0]
I
PE2RP[0]
I
PE2TN[0]
O
PE2TP[0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PEREFCLKN
I
PEREFCLKP
I
LVPECL/
CML
Diff. Clock
Input
I/O
LVTTL
STI1
Pin Name
MSMBCLK
Internal
Resistor
Refer toTable 8
MSMBDAT
I/O
General Purpose I/O
GPIO[9,7,2:0]
I/O
LVTTL
High Drive
pull-up
System Pins
APWRDISN
I
LVTTL
Input
pull-down
CCLKDS
I
pull-up
CCLKUS
I
pull-up
PERSTN
I
RSTHALT
I
pull-down
SWMODE[2:0]
I
pull-down
WAKEN
EJTAG / JTAG
1.
I
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
JTAG_TRST_N
Schmitt Trigger Input (STI).
STI
I/O
JTAG_TCK
Notes
open-drain
LVTTL
STI
pull-up
STI
pull-up
I
STI
pull-up
I
STI
pull-up
Table 7 Pin Characteristics
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Advance Information
Function
IDT 89HPES4T4 Data Sheet
Logic Diagram — PES4T4
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 2
PEREFCLKP
PE0TP[0]
PEREFCLKN
PE0TN[0]
PE0RP[0]
PE2TP[0]
PE0RN[0]
PE2TN[0]
PE2RP[0]
PE3TP[0]
PCI Express
Switch
SerDes Output
Port 3
PE3RP[0]
PE3RN[0]
PE4TP[0]
PCI Express
Switch
SerDes Input
Port 4
PCI Express
Switch
SerDes Output
Port 2
PE2RN[0]
PE3TN[0]
PCI Express
Switch
SerDes Input
Port 3
PCI Express
Switch
SerDes Output
Port 0
PE4TN[0]
PES4T4
PCI Express
Switch
SerDes Output
Port 4
PE4RP[0]
PE4RN[0]
5
GPIO[9,7,2:0]
General Purpose
I/O
JTAG_TCK
Master
SMBus Interface
JTAG_TDI
MSMBCLK
JTAG_TDO
MSMBDAT
JTAG Pins
JTAG_TMS
JTAG_TRST_N
System
Pins
CCLKDS
CCLKUS
VDDCORE
RSTHALT
VDDI/O
PERSTN
SWMODE[2:0]
VDDPE
3
VDDAPE
WAKEN
VSS
APWRDISN
Power/Ground
VTTPE
Figure 3 PES4T4 Logic Diagram
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Advance Information
Reference
Clocks
IDT 89HPES4T4 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
Parameter
Description
Min
Typical
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
PEREFCLK
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
50
0.6
Table 8 Input Clock Requirements
frequency is 100 MHz.
2.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC
coupling required.
AC Timing Characteristics
Parameter
Description
Min
Typical
Max
Units
1101
ps
400.12
ps
0.252
UI
PCIe Transmit
TTX-RISE, TTX-FALL
Rise / Fall time of TxP, TxN outputs
UI
Unit Interval
80
399.88
TTX-MAX-JITTER
Transmitter Total Jitter (peak-to-peak)
TTX-EYE
Minimum Tx Eye Width (1 - TTX-MAX-JITTER)
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
LTLAT-10
Transmitter data latency (for n=10)
LTLAT-20
Transmitter data latency (for n=20)
TTX-SKEW
Transmitter data skew between any 2 lanes
TTX-IDLE-SET-TOIDLE
400
0.75
UI
0.15
UI
9
11
bits
9
11
bits
500
1300
ps
Maximum time to transition to a valid electrical idle after
sending an Electrical Idle ordered set
4
6
ns
TEIExit
Time to exit Electrical Idle (L0s) state into L0
12
16
ns
TBTEn
Time from asserting Beacon TxEn to beacon being transmitted on the lane
30
80
ns
TRxDetectEn
Pulse width of RxDetectEn input
10
10.2
ns
TRxDetect
RxDetectEn falling edge to RxDetect delay
1
2
ns
9.8
PCIe Receive
LRLAT-10
Recover data latency for n=10
28
29
bits
LRLAT-20
Recover data latency for n=20
49
60
bits
Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
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Advance Information
1. The input clock
IDT 89HPES4T4 Data Sheet
Parameter
TRX-SKEW
Description
Min
Typical
Max
Units
20
ns
200
µs
Receiver data skew between any 2 lanes
3
TBDDly
Beacon-Activity on channel to detection of Beacon
TRX-IDLE_ENTER
Delay from detection of Electrical Idle condition on the
channel to assertion of TxIdleDetect output
10
20
ns
TRX-IDLE_EXIT
Delay from detection of L0s to L0 transition to de-assertion of TxIdleDetect output
5
10
ns
TRX-MAX-JITTER
Receiver total jitter tolerance
0.65
UI
TRX-EYE
Minimum Receiver Eye Width
TRX-EYE-MEDIAN-to-
Maximum time between jitter median and max deviation
from median
MAX JITTER
0.35
UI
0.325
UI
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
measured between 20% and 80% points. Will depend on package characteristics.
2.
Measured using PCI Express Compliance Pattern.
3.
This is a function of beacon frequency.
Signal
Symbol
Reference
Min Max Unit
Edge
Advance Information
1. As
Timing
Diagram
Reference
GPIO
GPIO[9,7,2:0]1
Tpw_13b2
None
50
—
ns
See Figure 4.
Table 10 GPIO AC Timing Characteristics
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK
Tdo_13a
Tdo_13a
GPIO (synchronous output)
Tpw_13b
GPIO (asynchronous input)
Figure 4 GPIO AC Timing Waveform
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IDT 89HPES4T4 Data Sheet
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
25.0
50.0
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
11.3
ns
—
11.3
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
JTAG_TCK rising
Thld_16b
JTAG_TDO
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 11 JTAG AC Timing Characteristics
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
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Advance Information
1.
IDT 89HPES4T4 Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
0.9
1.0
1.1
V
3.135
3.3
3.465
V
VDDCORE
Internal logic supply
VDDI/O
I/O supply except for SerDes LVPECL/CML
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 12 PES4T4 Operating Voltages
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES4T4, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels.
The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 13 PES4T4 Operating Temperatures
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Advance Information
Power-Up/Power-Down Sequence
IDT 89HPES4T4 Data Sheet
Power Consumption
Parameter
Typ.
Max.
Unit
Conditions
tbd
tbd
mA
Tambient = 25oC
Max. values use the maximum voltages listed in Table 12. Typical values use the typical voltages listed
in that table.
Normal mode
tbd
tbd
mA
Standby mode1
tbd
—
mA
IDDPE,
tbd
tbd
mA
IDD APE
tbd
tbd
mA
ITTPE
tbd
tbd
mA
tbd
tbd
W
tbd
—
W
IDDI/O
IDDCore
Power
Dissipation
Normal mode
1
Standby mode
Advance Information
Table 14 PES4T4 Power Consumption
1.
All ports in D1 state.
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IDT 89HPES4T4 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12.
Note: See Table 7, Pin Characteristics, for a complete I/O listing.
Serial Link
Parameter
Min1
Description
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
Advance Information
I/O Type
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 15 DC Electrical Characteristics (Part 1 of 2)
13 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 15 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
14 of 23
September 7, 2007
Advance Information
Other I/Os
IDT 89HPES4T4 Data Sheet
Package Pinout — 144-BGA Signal Pinout for PES4T4
The following table lists the pin numbers and signal names for the PES4T4 device.
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
A1
VSS
C11
VDDCORE
F9
VDDCORE
J7
VSS
A2
VDDI/O
C12
VSS
F10
VDDI/O
J8
VDDCORE
A3
APWRDISN
D1
JTAG_TDO
F11
VDDI/O
J9
VSS
A4
VTTPE
D2
MSMBCLK
F12
GPIO_01
J10
VSS
A5
VTTPE
D3
VDDCORE
G1
VSS
J11
VDDI/O
A6
PE0TP00
D4
VSS
G2
JTAG_TRST_N
J12
GPIO_09
A7
VDDPE
D5
VSS
G3
VSS
K1
VSS
A8
PE0RP00
D6
VSS
G4
VDDCORE
K2
VDDCORE
A9
VDDI/O
D7
VDDCORE
G5
VSS
K3
VDDI/O
A10
SWMODE_0
D8
VSS
G6
VDDCORE
K4
VDDCORE
A11
SWMODE_1
D9
VSS
G7
VSS
K5
VDDPE
A12
VSS
D10
VSS
G8
VDDCORE
K6
VSS
B1
VDDCORE
D11
PERSTN
G9
VSS
K7
VDDPE
B2
WAKEN
D12
RSTHALT
G10
VDDCORE
K8
VSS
B3
CCLKUS
E1
JTAG_TDI
G11
VSS
K9
VDDCORE
B4
VDDPE
E2
MSMBDAT
G12
GPIO_02
K10
VDDI/O
B5
VDDPE
E3
VDDI/O
H1
PEREFCLKP
K11
VSS
B6
PE0TN00
E4
VDDCORE
H2
VDDI/O
K12
VSS
B7
VDDPE
E5
VSS
H3
VDDAPE
L1
PE2RN00
B8
PE0RN00
E6
VDDCORE
H4
VSS
L2
VSS
B9
CCLKDS
E7
VSS
H5
VSS
L3
PE2TP00
B10
SWMODE_2
E8
VSS
H6
VSS
L4
VSS
B11
VSS
E9
VSS
H7
VDDCORE
L5
PE3TN00
B12
VSS
E10
VDDCORE
H8
VSS
L6
VDDAPE
C1
JTAG_TMS
E11
VSS
H9
VSS
L7
PE3RN00
C2
VSS
E12
GPIO_00
H10
VDDCORE
L8
VTTPE
C3
VSS
F1
JTAG_TCK
H11
VSS
L9
PE4RP00
C4
VDDCORE
F2
VDDI/O
H12
GPIO_07
L10
VSS
C5
VDDAPE
F3
VDDCORE
J1
PEREFCLKN
L11
PE4TN00
C6
VDDAPE
F4
VSS
J2
VSS
L12
VDDCORE
C7
VSS
F5
VDDCORE
J3
VSS
M1
PE2RP00
C8
VDDCORE
F6
VSS
J4
VSS
M2
VSS
C9
VDDCORE
F7
VDDCORE
J5
VSS
M3
PE2TN00
C10
VSS
F8
VSS
J6
VDDCORE
M4
VTTPE
1
1
1
1
Alt
1
Table 16 PES4T4 144-pin Signal Pin-Out (Part 1 of 2)
15 of 23
September 7, 2007
Advance Information
Pin
IDT 89HPES4T4 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
M5
PE3TP00
M7
PE3RP00
M9
PE4RN00
M11
PE4TP00
M6
VSS
M8
VDDAPE
M10
VSS
M12
VSS
Alt
Table 16 PES4T4 144-pin Signal Pin-Out (Part 2 of 2)
Pin
GPIO
Alternate
E12
GPIO_00
P2RSTN
F12
GPIO_01
P4RSTN
G12
GPIO_02
IOEXPINTN0
H12
GPIO_07
GPEN
J12
GPIO_09
P3RSTN
Table 17 PES4T4 Alternate Signal Functions
Power Pins
VDDCore
VDDCore
VDDI/O
VDDPE
VDDAPE
VTTPE
B1
F9
A2
A7
C5
A4
C4
G4
A9
B4
C6
A5
C8
G6
E3
B5
H3
L8
C9
G8
F2
B7
L6
M4
C11
G10
F10
K5
M8
D3
H7
F11
K7
D7
H10
H2
E4
J6
J11
E6
J8
K3
E10
K2
K10
F3
K4
F5
K9
F7
L12
Table 18 PES4T4 Power Pins
16 of 23
September 7, 2007
Advance Information
Alternate Signal Functions
IDT 89HPES4T4 Data Sheet
Vss
Vss
Vss
Vss
A1
D10
G11
K1
A12
E5
H4
K6
B11
E7
H5
K8
B12
E8
H6
K11
C2
E9
H8
K12
C3
E11
H9
L2
C7
F4
H11
L4
C10
F6
J2
L10
C12
F8
J3
M2
D4
G1
J4
M6
D5
G3
J5
M10
D6
G5
J7
M12
D8
G7
J9
D9
G9
J10
Advance Information
Ground Pins
Table 19 PES4T4 Ground Pins
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
APWRDISN
I
A3
System
CCLKDS
I
B9
CCLKUS
I
B3
GPIO_00
I/O
E12
GPIO_01
I/O
F12
GPIO_02
I/O
G12
GPIO_07
I/O
H12
GPIO_09
I/O
J12
JTAG_TCK
I
F1
JTAG_TDI
I
E1
JTAG_TDO
I
D1
JTAG-TMS
O
C1
JTAG-TRST_N
I
G2
MSMBCLK
I/O
D2
MSMBDAT
I/O
E2
General Purpose Input/Output
JTAG
SMBus
Table 20 89PES4T4 Alphabetical Signal List (Part 1 of 2)
17 of 23
September 7, 2007
Signal Name
I/O Type
Location
Signal Category
PE0RN00
I
B8
PCI Express
PE0RP00
I
A8
PE0TN00
O
B6
PE0TP00
O
A6
PE2RN00
I
L1
PE2RP00
I
M1
PE2TN00
O
M3
PE2TP00
O
L3
PE3RN00
I
L7
PE3RP00
I
M7
PE3TN00
O
L5
PE3TP00
O
M5
PE4RN00
I
M9
PE4RP00
I
L9
PE4TN00
O
L11
PE4TP00
O
M11
PEREFCLKN
I
J1
PEREFCLKP
I
H1
PERSTN
I
D11
System
RSTHALT
I
D12
System
SWMODE_0
I
A10
SWMODE_1
I
A11
SWMODE_2
I
B10
I/O
B2
WAKEN
VDDCORE,
VDDAPE, VDDI/O,
VDDPE, VTTPE
See Table 18 for a listing of power pins.
VSS
See Table 19 for a listing of ground pins.
Advance Information
IDT 89HPES4T4 Data Sheet
Table 20 89PES4T4 Alphabetical Signal List (Part 2 of 2)
18 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
PES4T4 Pinout — Top View
2
3
A
4
5
X
X
6
7
8
9
10
11
12
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
X
L
L
X
M
1
2
3
4
VDDCore (Power)
VDDI/O (Power)
M
5
x
6
7
VTTPE (Power)
8
9
10
Vss (Ground)
11
12
Signals
VDDPE (Power)
VDDAPE (Power)
19 of 23
September 7, 2007
Advance Information
1
IDT 89HPES4T4 Data Sheet
Advance Information
PES4T4 Package Drawing — 144-Pin BC144/BCG144
20 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Advance Information
PES4T4 Package Drawing — Page Two
21 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Revision History
August 16, 2007: Initial publication of advanced data sheet.
Advance Information
September 7, 2007: Added Power-Up/Power Down Sequence.
22 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Ordering Information
A
AAA
NNAN
AA
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Device
Revision
AA
Legend
A = Alpha Character
N = Numeric Character
A
Package Temp Range
Blank
Commercial Temperature
(0°C to +70°C Ambient)
BC
BC144 144-ball CABGA
BCG
BCG144 144-ball CABGA, Green
ZA
ZA revision
4T4
4-lane, 4-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES4T4ZABC
144-pin BC144 package, Commercial Temperature
89HPES4T4ZABCG
144-pin Green BC144 package, Commercial Temperature
®
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23 of 23
for Tech Support:
email: [email protected]
phone: 408-284-8208
September 7, 2007
Advance Information
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