For Communications Equipment
MN6152U
PLL LSI with Built-In Prescaler
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for VDD=2.0 V, F IN=100 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Pin Assignment
XIN
1
16
OR
XOUT
2
15
OV
FV
3
14
LC
VDD
4
13
FR
DOP
5
12
PS
VSS
6
11
LE
LD
7
10
DATA
FIN
8
9
Features
Low power supply voltage: VDD =1.8 to 2.5V
Low power consumption: 5mW (VDD =2.0V,
FIN =100MHz)
High-speed operation:
FIN =175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and reference frequency dividing stages
(TOP VIEW)
SSOP016-P-0225
CLK
FIN
PS
LE
DATA
CLK
XOUT
XIN
8
12
11
10
9
2
1
Amplifier
Amplifier
Prescaler and
phase matching
Data control
Phase
matching
Swallow
counter
14-bit programmable
counter
18-bit latch
18-bit shift register
17-bit latch
17-bit programmable counter
Control
3
5
16
15
7
14
13
FV
DOP
OR
OV
LD
LC
FR
MN6152U
For Communications Equipment
Block Diagram
Phase comparator
For Communications Equipment
MN6152U
Pin Descriptions
Pin No.
1
Symbol
XIN
2
XOUT
Function Description
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
XOUT=Oscillator circuit output pin.
Frequency divider output signal in comparator stage.
3
FV
4
V DD
Power supply
5
D OP
Low-pass filter connection pin. Use a passive filter.
6
V SS
Ground
7
LD
8
FIN
9
CLK
Phase comparator input monitor.
Phase comparator output pin:
"H" level for locked; "L"level for unlocked.
Frequency divider input pin in comparating stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
10
DATA
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
11
LE
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
12
PS
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
FR
14
LC
15
OV
16
OR
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
Phase comparator output pin for external charge pump.
MN6152U
For Communications Equipment
MN6152 Frequency Dividing Data Settings
The following formula shows frequency divider operation.
FIN ={ (16 × N) + A} × (XIN ÷ R)
where
FIN
: VCO output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
XIN
: Reference oscillator frequency
R
: Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB
14 bits
Programmable counter setting (N)
4 bits
LSB
Swallow counter setting (A)
For Communications Equipment
MN6152U
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
VDD
Rating
– 0.3 to +3.5
Unit
Input pin voltage
VI
VSS – 0.3 to V DD +0.3
V
Output pin voltage
VO
VSS – 0.3 to V DD +0.3
Power dissipation
PD
20
Operating ambient temperature
Topr
–20 to +60
Storage temperature
Tstg
–55 to +125
mW
˚C
Operating Conditions
VSS=0V, Ta=–20 to +60˚C
Parameter
Power supply voltage
Symbol
VDD
Test Conditions
min
1.8
typ
2.0
max
2.5
Unit
V
min
typ
max
2.5
Unit
mA
10
µA
Electric Characteristics
VDD=2V, Ta=–20 to +60˚C
Parameter
Power supply voltage
Symbol
IDD
Test Conditions
FIN =100MHz, XIN =20MHz,
PS="H"
IDstop
Input Pins
CLK, DATA, LE, and PS
PS ="L" (at power save operation)
VDD=1.8 to 2.5V
"H" level input voltage
VIH
VDD – 0.2
VDD
"L" level input voltage
VIL
VSS
0.2
Input leakage current
ILI
Input Pin
FIN
±1.0
V
µA
VDD=1.8 to 2.5V
Input voltage
VIN
Input current
IIF
Pull-up resistor present
Input leakage current
ILIF
VIN =0 or 2V (PS="H")
0.4
Vp-p
–100
µA
(PS="L")
Maximum operating frequency
FINMAX
VIN =0.4 Vp-p
Minimum operating frequency
FINMIN
VIN =0.4 Vp-p
Input Pin
XIN
±20
175
µA
MHz
10
MHz
VDD=1.8 to 2.5V
Input voltage
VIN
Input current
IIX
Pull-up resistor present
0.4
Vp-p
2.5
mA
(PS="L")
Input leakage current
Maximum operating frequency
VLIX
VIN =0 or 2V
XINMAX
VIN =0.4 Vp-p
5.0
20
µA
MHz
MN6152U
For Communications Equipment
Electrical Characteristics
VDD=2V, Ta=–20 to +60˚C
Parameter
Symbol
Test Condition
Crystal Oscillator Pins X IN, X OUT VDD=1.8 to 2.5V
Crystal oscillator frequency
Output Pins
fXtal
FV, FR, LC, OV
min
typ
max
20
MHz
VDD =1.8 to 2.5V
"H" level output voltage
VOH
IOH = –100µA
VDD– 0.3
VDD
"L" level output voltage
VOL
IOL= 100µA
V SS
0.3
Output Pin
VXOH
IXOH= –500µA
VDD– 0.3
VDD
"L" level output voltage
VXOL
IXOL= 500µA
V SS
0.3
DOP
V
VDD=1.8 to 2.5V
"H" level output voltage
IDOH
VDop=1.6V
–100
"L" level output voltage
IDOL
VDop=0.4V
100
Output Pin
V
XOUT VDD=1.8 to 2.5V
"H" level output voltage
Output Pin
Unit
OR
µA
VDD=1.8 to 2.5V
"L" level output voltage
IORL
Setup time *1
VOR=0.4V
100
µA
tsul
500
ns
tsu2
500
ns
tH
500
ns
Hold time * 1
Note*1: The following timing chart shows the setup and hold times.
DATA
50%
tsu1
tH
CLK
tsu2
LE
For Communications Equipment
MN6152U
Frequency Divider Setting
R-side latch
CLK
1
DATA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB
17
18
19
18
19
LSB
LE
N-side latch
CLK
1
DATA
2
3
4
5
6
7
8
9
10
MSB
11
12
13
14
15
16
17
20
LSB
LE
· Input the data MSB first.
· The data is read at the rising edges of the CLK signal.
· Drive the LE pin at "L" level when writing data.
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of
our other products.
MN6152U
For Communications Equipment
Package Diemnsions (Unit: mm)
SSOP016-P-0225
6.5±0.2
16
9
+0.10
0.15 -0.05
6.3±0.2
4.3±0.2
1.0±0.1
0 to 10°
0.8
0.15
0.35±0.10
1.55±0.30
8
(0.45)
0.1±0.1
1
1.45±0.20
0.5±0.1
SEATING PLANE